JPH04177439A - Single chip microcomputer - Google Patents

Abstract

PURPOSE:To extend a memory space without adding any special decoding circuit by storing the data which decides a boundary between the internal and external memory spaces and qualifying the decision of the memory space by using the stored data. CONSTITUTION:The data which decides a boundary between the internal and external memory spaces is stored and a control signal is produced. That is, a latch 10 is provided to store the data that decides a boundary between both memory spaces together with an AND logic 11 and an OR logic 12 which monitor the bit of the MSB of a program address bus 13 and the bit lower than this MSB by one rank. When the output of the latch 10 is set at a low level, the output of the logic 11 is also set at a low level. Then use value of a memory space control signal 14 is decided by the MSB value of the bus 13.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a single-chip φ microcomputer, and more particularly to a memory space control circuit that allows internal memory space to be replaced by external memory space by software.

[Conventional technology]

A single-chip microcomputer has a central processing unit that processes data, a memory unit that stores programs and processing data, an input/output unit that exchanges data with the outside, etc. on a single integrated circuit. Since stored program control devices can perform various types of processing by changing the program,
It is used as a control component in various fields.

In recent years, with advances in integrated circuit technology, the performance of microcomputers has been increasing. At the same time, the number of highly functional devices being applied is increasing. In order to control highly functional devices, a large amount of program memory is required, and to meet this demand, products with large built-in program memory capacities are being developed one after another. Therefore, it is desirable to have a large usable program memory area.

FIG. 5 shows a memory space map of a conventional single-chip microcomputer.

In FIG. 5, there are conventional single-chip microcomputers in which only the internal memory space 23 corresponding to the built-in internal memory 22 is used as the program memory area, and in addition to the internal memory space 23, external memory 24
and an external memory space 27 corresponding to the external memory 26 without built-in program memory.
Only program memory area (ROMLES)
S) etc.

[Problem to be solved by the invention]

In such conventional single-chip microcomputers, in order to expand the memory space, the number of bits in the address of the program memory was increased or banks were switched. However, with the conventional configuration, it is necessary to output an additional address signal and a control signal for bank switching from the microcomputer. For this reason, some of the terminal functions before expansion will be lost due to expansion of the memory space. Further, there are also problems in that it is necessary to increase the number of bits of the address decoder and to add a circuit for decoding bank switching signals outside the microcomputer.

SUMMARY OF THE INVENTION An object of the present invention is to provide a single-chip microcomputer that solves the above problems and allows memory space to be expanded without losing some of the terminal functions or adding special decoding circuits. It's about doing.

[Means to solve the problem]

The configuration of the single-chip microcomputer of the present invention includes means for storing data that determines the boundary between an internal memory space and an external external memory space, and a means for modifying memory space determination using this stored data. It is characterized by

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing a single-chip microcomputer according to an embodiment of the present invention.

In FIG. 1, the single-chip microcomputer of this embodiment has a central processing section 1.0 that performs data processing and controls the entire circuit. Data memory section 2 for storing processed data. Internal program memory section for storing programs 3.
Input/output unit for exchanging data with the outside 4. 5. A memory space control unit that stores data that determines the boundary between internal memory space and external memory space and generates control signals. It is configured to include a clock generation section 6 that generates an internal clock. Here, each section except the clock generating section 6 transfers data via the internal bus 7. Further, the external memory 8 exchanges data with the input/output section 4 via an external bus 9.

FIG. 2 shows a detailed circuit diagram of the memory space control unit 5 of the embodiment shown in FIG. FIG. 3 shows a detailed circuit diagram of a conventional memory space control section. FIG. 4 shows a memory space map of the embodiment shown in FIG. FIG. 5 shows a memory space map of a conventional example.

Here, for the sake of simplicity, a single-chip microcomputer with a program memory address of 4 bits and a built-in memory with a capacity equivalent to half of the total memory space will be described.

Further, in this embodiment, a circuit in which half of the internal memory space can be replaced with an external memory space will be described.

As shown in FIG. 3, in the past, a buffer IS was provided to monitor the most significant bit (hereinafter referred to as MSB) of the program address bus 13, and the output of this buffer 15 was used as the memory space control signal 14, as shown in FIG. The information is transmitted to the central processing unit 1 as shown. When the memory space control signal 14 is at a high level, the central processing unit 1 controls access to the external memory, and when the signal is at a low level, controls access to the internal memory.

As shown in FIG. 5, half of the entire memory space with larger addresses is allocated to the external memory space 25, and half of the smaller address is allocated to the internal memory space 23.

On the other hand, in this embodiment, as shown in FIG. 2, a latch 10. AND logic 11. which monitors the MSB of the program address bus 13 and the bit one lower than the MSB. OR logic 1
It is composed of 2. The case where the low level is stored in the latch 10 is the state of setting 1 in FIG. When the output of the latch 10 is low level, the output of the AND logic 11 is also low regardless of the value of the program address bus 13.
The MS on the program address bus 13 becomes OW level.
The value of H determines the value of the output of the OR logic 12, i.e., the memory space control signal 14, and the same control as in the conventional example is performed.

Therefore, of the entire memory space, half of the larger addresses are allocated to the external memory space 16, and half of the smaller addresses are allocated to the internal memory space 17. That is, external memory 1
8 is allocated to the external memory space 16, and internal memory 19 is allocated to the internal memory space 17.

Next, the case where the high level is stored in the latch 10 is the state of setting 2 in FIG. As in the case of setting 1, when the MSB of the program address bus 13 is at a high level (D, the output of the OR logic 12 is at a high level, that is, the memory space control signal 14 is at a high level, and the external memory is accessed. The output of latch 10 is H
Since it is at high level, the M of program address bus 13
Even when the SB is at Low level, if the bit one lower than the MSB is at High level, the output of AND logic 11 becomes High level, and the output of OR logic 12, that is, the memory space control signal 14 becomes High level, and the external memory is not accessed. go to. Therefore, program address 13
Only when the MSB and the bit one bit below it are both at a low level, the memory space control signal 14 goes to a low level and the internal memory is accessed. in this way,
External memory space 16 and internal memory space 17 in setting 1
The larger half of the addresses in is allocated to the external memory space 20 of setting 2, and the remaining 1/4 of the entire memory space is allocated to the internal memory space 21.

As explained above, it is possible to switch half of the internal memory space to the external memory space depending on the data stored in the latch 10, and by adding external memory to an address that overlaps with the internal memory, the internal memory and external memory can be switched as appropriate. It becomes possible to use memory separately. Therefore, it is possible to add external memory and use the added memory as needed without increasing the number of bits in the address of the program memory or switching banks.

This effect is especially significant when the built-in memory capacity is large, as is the case today.

In this embodiment, we have described a configuration in which half of the internal memory space is switched to the external memory space, but it is also possible to control the internal memory space in more detail by adding a latch, decoding the latch output, and combining AND logic and OR logic. It is also possible to switch the entire internal memory to external memory.

〔Effect of the invention〕

As explained above, the present invention makes it possible to replace an appropriate portion of the internal memory space with the external memory space using software, so there is no need to increase the number of bits in the program memory address or switch banks. However, it is now possible to expand external memory with the same capacity as the internal memory at maximum, without losing the pin function before memory space expansion (increasing the number of bits of the external address decoder, changing banks, etc.). The effect is that the memory space can be expanded without adding circuitry to decode signals.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a single-chip fist microcomputer according to an embodiment of the present invention, FIG. 2 is a circuit diagram of the memory space control section shown in FIG. 1, and FIG. 3 is a circuit diagram of the memory space control section of the conventional example. In the circuit diagram, FIG. 4 is a memory space map of the embodiment shown in FIG. 1, and FIG. 5 is a memory space map of the conventional example. 1...Central processing unit, 2...Data memory unit, 3...
・Internal program memory section, 4...Input/output section, 5...
・Memory space control unit, 6... Clock generation unit, 7...
・Internal bus, 8...external memory, 9...external bus,
10...Latch, 11...AND logic, 12...
OR logic, 13...Program address bus, 14.
...Memory space control signal, 15...Buffer, 16.
20, 25.27...External memory space, 17.21.
23...Internal memory space, 18.24.26...External memory, 19.22...Internal memory.

Claims (1)

[Claims] A single-chip microcomputer comprising: means for storing data that determines a boundary between an internal memory space and an external memory space; and means for modifying a memory space determination using the data stored by the means.