JPS63159966A - Single-chip microcomputer - Google Patents

Abstract

PURPOSE:To reduce the load capacity of a data bus and to increase the working speed of the titled single-chip microcomputer by using a 1st memory means which is capable of both writing and reading tasks and a 2nd memory means which is capable of conducting only a writing task and which outputs write information to a prescribed logic circuit. CONSTITUTION:A memory cell array 7 serving as a 1st memory circuit which is capable of both writing and reading tasks is connected to a data bus 13 via a write buffer 11 and a read buffer 12. At the same time, the input of an output data latch 3 serving as a 2nd memory circuit which is capable of only a writing tasks is connected to the bus 13 together with the output of the latch 3 connected to an output terminal 1 via an output buffer 2 respectively. A CPU writes data in both the latch 3 and the array 7 when the data is written in the terminal 1 and then reads out the contents of the array 7 when the contents of the latch 3 are read out. Thus it is possible to decrease the number of read buffers connected to the bus 13 and therefore to reduce the load capacity of the bus 13. Then the working speed is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a single-chip microcomputer.

(Prior Art) In general, a single-chip microcomputer uses a CP
In addition to U, it is composed of a program memory for storing instructions, a data memory for storing calculation results and constants, and peripheral circuits such as an input/output board and a timer. Single-chip microcomputers contribute to increasing the functionality and reducing costs of applied equipment, and recently there has been a trend toward more functions, multiple input/output ports, and higher speeds.

FIG. 2 is a block diagram showing an example of the configuration of an output port section in a conventional single-chip microcomputer.

The data bus 31 is connected to an output data latch 23 that stores data to be output, and the output of the output data latch 23 is connected to the output terminal 21 via an output buffer 22. The latch clock signal of the output data latch 23 is
The output data latch 23 is allocated to the output of the address decoder 29 that decodes the address and the write clock signal 2.
This is the output of the AND circuit 25 which receives 7 as an input. The output data latch 23 is connected to the data bus 31 via a read buffer 24, so that the data stored in the output data latch 23 can be read. Read buffer 24
The read clock signal is sent to an AND circuit 26 which receives the output of the address decoder 29 and the read clock signal 28.
This is the output of Address bus 32 is address decoder 2
9 is connected. The range surrounded by the dotted line 30 is the output port, and a single-chip microcomputer generally includes a large number of output ports each assigned to a different address. In addition to these output ports, single-chip microcomputers also have memory circuits such as various writeable and readable flip-flops, and built-in peripheral circuits such as timers that are controlled by the outputs of these memory circuits. ing. Predetermined addresses are also assigned to these memory circuits, and data is written or the stored contents are read out to the CPU side according to instructions.

The operation of the circuit shown in FIG. 2 will be explained. When the CPU of this single-chip microcomputer outputs data to the output terminal 21, by putting the address assigned to the output terminal 21 on the address bus 32, the output of the address decoder 29 becomes active, and the write clock signal 27 Since the output of the AND circuit 25 becomes active synchronously, the data on the data bus 31 is latched in the output data latch 23, and the data latched in the output data latch 23 is output to the output terminal 21 via the output buffer 22. .

Furthermore, when the CPU reads out the data latched in the output data latch 23 in order to use the stored data for calculations, etc., the address assigned to the output terminal 21 is placed on the address bus 32, so that the address decoder 29 outputs becomes active, and the output of the AND circuit 26 becomes active in synchronization with the read clock signal 28, so that the data latched in the output data latch 23 is output to the data bus 31 via the read buffer 24.

(Problems to be Solved by the Invention) In the conventional single-chip microcomputer described above, each memory circuit built into the peripheral circuit has a read buffer for outputting stored data to the data bus, and The operating speed of a chip microcomputer is usually affected by the load capacity of the data bus built into the single chip microcomputer, so if the number of peripheral circuits increases, the number of read buffers connected to the data bus will increase. Due to the output load capacity of the read buffer, the load capacity of the data bus increases and the operating speed decreases. This increases the on-chip area of the buffer, the output load capacitance of the read buffer also increases, and when more read buffers are connected to the data bus, the Since the output load capacitance of the read buffer becomes part of the load capacitance of the data bus, there is a drawback that it is not very effective in increasing the operating speed.

[Means for solving problems]

The single-chip microcomputer of the present invention has a first storage means that is assigned a predetermined address and is capable of writing data and reading stored data according to instructions from the CPU; and a second storage means that can only be written by a command from the CPU and outputs the written information to a predetermined logic circuit.

(Function) Therefore, the number of read buffers connected to the data bus can be reduced, the load capacity of the data bus can be reduced, and
It becomes possible to increase the operating speed of single-chip microcomputers.

(Example) Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a portion of an embodiment of a single-chip microcomputer according to the present invention.

A memory cell array 7, which is a first memory circuit that can be written to and read from by instructions from a single-chip microcomputer, is connected to a data bus 13 via a write buffer 11 and a read buffer 12. The address decoder 8 outputs a selection signal group 17 for selecting each of all bits in the memory cell array, and the selection signal group 17 is input to an OR circuit 18 . The write clock signal of the write buffer 11 is the write clock signal 6 and the OR circuit 18.
The read clock signal of the read buffer 12 is the output of the AND circuit 15 which inputs the output of the read clock signal IO and the output of the OR circuit 18.
This is the output of 6. Further, the input of the output data latch 3, which is a second memory circuit that can be written to by a command, is connected to the data bus 13, and the output is connected to the output terminal 1 via the output buffer 2. The latch clock signal of the output data latch 3 is the output of an AND circuit 4 which receives the write clock signal 6 and the output of the address decoder 5 as inputs. Inputs of address decoder 5 and address decoder 8 are connected to address bus 14 . The range indicated by dotted line 15 is one output port, and this single-chip microcomputer has many other peripheral circuits such as output ports assigned to different addresses. This is an example.

Next, the circuit operation of this embodiment will be explained.

(+) cp of this single chip microcomputer
When u outputs data to output terminal 1. In this case, by putting the address assigned to the output terminal 1 on the address bus 14, the output of the address decoder 5 becomes active. Therefore, since the output of the AND circuit 4 becomes active in synchronization with the write clock signal 6, the data on the data bus 13 is stored in the output data latch 3, and the data stored in the output data latch 3 is transferred via the output buffer 2. and is output to output terminal 1. Furthermore, since the address space allocated to the memory cell array 7 includes the address allocated to the output terminal 1, when the address allocated to the output terminal 1 is placed on the address bus 14, the address decoder 8 decodes the address bus 14. and select signal group 1
7, the signal at the same address as the output terminal l is made active. Therefore, output terminal 1 in memory cell array 7
The bit at the same address is selected, and roughly OR circuit 1
8 becomes active, the output of the AND circuit 15 becomes active in synchronization with the write clock signal 6, and the data on the data bus 13 is transferred to the same address as the output terminal 1 in the memory cell array 7 via the write buffer 11. written to the bits of That is, when the CPU outputs data to the output terminal 1, the data is written to both the output data latch 3 and the bit assigned to the same address as the output terminal 1 in the memory cell array 7.

(2) CP of this single-chip microcomputer
When U reads the contents of output data latch 3. In this case, the address assigned to output terminal 1 is transferred to address bus 1.
4, the address decoder 8 decodes the address bus 14 and activates the signal of the same address as the output terminal 1 among the selection signal group 17. Following,
The bit at the same address as output terminal 1 in the memory cell array 7 is selected, and the output of the OR circuit 18 becomes active, so the output of the AND circuit 16 becomes active in synchronization with the read clock signal 10, and the output of the AND circuit 16 becomes active in synchronization with the read clock signal 10. The data stored in the bit at the same address as the output terminal 1 in 7 is output to the data bus 13 via the read buffer 12. When the address assigned to the output terminal 1 is placed on the address bus 14, the output of the address decoder 5 becomes active, but since there is no circuit to read the data stored in the output data latch 3, the data stored in the output data latch 3 is not stored. The data is the data bus! 3 will not be output. In other words, when the CPU reads the contents of the output data latch 3, it reads the contents stored in the bit at the same address as the output terminal 1 in the memory cell array 7, which stores the same contents as the output data latch 3. I will put it out.

Generally, single-chip microcomputers have a built-in cell array as data memory (dynamic random access memory, static random access memory, etc.) whose circuit configuration is designed so that the area on the chip is smaller than that of ordinary logic elements. In most cases, writing/reading of the memory cell array can be realized by adding the memory cell array 7 shown in FIG. The circuitry required for data memory can also be used for data memory, reducing chip area. Furthermore, the write information of the output data latch 3 may be output to the logic circuit.

[Effects of the Invention] As explained above, the present invention provides a first storage means in a single-chip microcomputer to which a predetermined address is assigned and which is capable of writing data and reading stored data according to instructions from the CPU. , a second memory means which is assigned the same address as the first memory means, can only be written by a CPU instruction, and outputs the written information to a predetermined logic circuit, and the CPU of the single-chip microcomputer When writing data to the logic circuit, it is written to both the second storage means and the first storage means, and when reading the data written to the logic circuit, it is not read from the second storage means. By reading from the first storage means, the number of read buffers connected to the data bus is reduced, the load capacity of the data bus is reduced, and the operating speed of the single-chip microcomputer can be increased. There is.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a part of an embodiment of the single-chip microcomputer of the present invention, and FIG. 2 is a block diagram of an example of the configuration of an output port section in a conventional single-chip microcomputer. l...Output terminal, 2...Output buffer, 3...Output data latch, 4, 15.16-...AND circuit, 6...Write clock signal, 5.8--Address decoder, 7 Axis/memory cell array, 18--OR circuit, 10--read clock signal, 11--axis write buffer, 12--read buffer, 13--data bus, 14φ--address bus, 15--output port .

Claims (1)

[Claims] In a single-chip microcomputer, a first chip is assigned a predetermined address and is capable of writing data and reading stored data according to instructions from the CPU.
and a second storage means which is assigned the same address as the first storage means, can only be written by a CPU instruction, and outputs the written information to a predetermined logic circuit. Single chip microcomputer.