JPH07334420A - Extended memory control circuit - Google Patents

Abstract

PURPOSE:To provide an extended memory control circuit capable of easily managing the extended memory space and reducing restriction to the constitution of address space of a CPU. CONSTITUTION:When a CPU 1 sends address data corresponding to an I/O address to an address bus AB and sends the address data of an extended memory space to be accessed to a data bus DB, an address control means 8 gives the address data of the extended memory space sent to the data bus DB to a memory means 2A. Thereby, the CPU 1 can access the extended memory space.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an extended memory control circuit for managing an extended memory space in a control device using a microcomputer (CPU).

[0002]

2. Description of the Related Art Conventionally, a control device using a microcomputer may require a memory capacity wider than the address space of a CPU. When expanding the memory space in this way, it has been common to use the following bank switching method.

In FIG. 3, the CPU address space is 64 kilobytes (hereinafter referred to as KB, addresses 0000H to FFF).
In the case of (up to FH), it is a memory map showing an example in which the RAM space is expanded to 128 KB and bank switching is performed. FIG. 4 is a circuit diagram showing a memory control circuit corresponding to FIG.

As shown in FIG. 3, a CPU address space 10 is a 32 KB RAM space 12 (8000H to FF).
FFH), and 32 KB ROM space 14 (0000H
.About.7FFFH). RAM space 12
A 32 KB bank B0 is allocated in the memory space of the RAM 2 of FIG. Further, the memory space of the RAM2 is a bank B having the same capacity (32 KB) as the bank B0.
1, B2, and B3 are assigned. These banks B0 to B3 form an extended RAM space 20 for a total of 128 KB.

An extended address of 2 bits is assigned to each of the four banks B0 to B3. That is, the bank B0 is "00", the bank B1 is "01", and the bank B2 is
"10" is assigned to the bank B and "11" is assigned to the bank B3. To switch banks, the upper addresses A15 and A16 of RAM2 are used as the extension addresses,
This is performed by using the lower addresses A0 to A14 as normal addresses.

As shown in FIG. 4, the CPU 1 has a RAM 2
Of the data bus D when accessing each bank B0 to B3 of
B has an extended address 2 corresponding to the bank to be accessed
Bit data is sent and held in the port PT, and normal address data is sent to the address bus AB. This allows the full width of address data to be stored in the RAM.
2 to access any bank.

[0007]

The above-mentioned conventional techniques have the following drawbacks. First, the CPU
1 accesses the banks B0 to B3 configured in the RAM 2 to operate, and performs bank management operations such as checking which bank is being accessed by reading the data held by the port PT. There is a need to do. This is to prevent access to the wrong bank space for some reason. Execution of such a bank management operation is not preferable because the software configuration becomes complicated.

Second, the RAM is provided in the address space of the CPU 1.
When allocating the space 12 and the ROM space 14, it may be desired to secure the ROM space 14 as large as possible. However, in such a case, when the RAM space 10 in the address space of the CPU 1 becomes smaller, the capacity of each bank also becomes smaller inevitably. Therefore, the expansion RAM space 20 which is the expansion memory space has a large number of small capacities. Since it is composed of banks, considering the complexity of bank management, the RAM space 1 in the address space of the CPU 1
It was difficult to set 2 to be small, that is, to set the ROM space 14 to be large. Due to such circumstances, there is a restriction on the configuration of the address space of the CPU.

The present invention has been made under the circumstances described above, and an object thereof is to provide an extended memory control circuit in which management of the extended memory space is easy and there are few restrictions on the configuration of the address space of the CPU. To do.

[0010]

The extended memory control circuit of the present invention has a CPU, a memory means, and an address control means, and the memory space of the memory means is at least CP.
It is divided into a work area assigned to the U address space and an extended memory space. When the CPU accesses the work area, the CPU sends the address data corresponding to the work area to the address bus to extend the extended memory. When accessing the space, predetermined I / O address data is sent to the address bus and address data corresponding to the extended memory space is sent to the data bus, and the address control means corresponds to the work area on the address bus. When the address data to be transmitted is transmitted, the data on the address bus is given to the memory means, and a predetermined I / O is applied to the address bus.
When the address data is sent, the data of the data bus is given to the memory means.

In the extended memory control circuit of the present invention, the address control means has a selection signal generating section, a data holding section and an address selecting section, and the selection signal generating section is a CP.
The data holding unit holds a data input from the data bus, and generates a selection signal that becomes active only when the CPU accesses a predetermined I / O address assigned to the U address space. When the selection signal is in the active state, the address selection section gives the data held by the data holding section to the memory means as address data, and when the selection signal is in the inactive state, the address selection section stores the address data of the address bus in the memory. It is characterized by giving to means.

[0012]

When the CPU sends the address data corresponding to the predetermined I / O address to the address bus and the address data of the extended memory space to be accessed to the data bus, the address control means sends it to the data bus. The address data of the expanded memory space thus created is given to the memory means. This allows the CPU to access the extended memory space.

Also, in the extended memory control circuit of the present invention, when the address control means has a selection signal generation section, a data holding section, and an address selection section, the CPU
When the address data corresponding to the predetermined I / O address is sent to the address bus and the address data of the extended memory space to be accessed is given to the data holding means via the data bus, the selection signal generating means is activated. A state selection signal is given to the address selection means. The address selecting means selects the address data of the extended memory space held in the data holding means and supplies it to the memory means. This allows the CPU to access the extended memory space.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a schematic configuration diagram showing an embodiment of an extended memory control circuit of the present invention, and FIG. 2 is a memory map corresponding to the embodiment.

First, the memory configuration will be described with reference to FIG. As shown in FIG. 2, the address space 40 of the 64 KB CPU is at least the RAM space 42 (C0
00H-FFFFH), ROM space 44 (0000H-
XXXXXH) and the I / O address space 46 (XXXX + 1H-) configured in the case of the memory mapped I / O system
BFFFH). However, the above "XXX
XH ″ is an address determined by the capacity of the ROM space 44. Further, one arbitrarily selected I / O address data Di in the I / O address space 46 is selected.
(For example, BFFFH) is assigned.

On the other hand, the memory space 50 of the RAM (memory means) corresponds to at least the work area 52 corresponding to the RAM space 42 and accessed by the original address data, and the I / O address space 46. It is divided into an extended RAM space (extended memory space) 54 accessed by an extended address described later.

Next, the circuit configuration will be described with reference to FIG. In FIG. 1, each control signal is displayed as low active (negative logic), but in the following description, a symbol indicating negative logic is omitted for simplicity of description.

The CPU 1 gives a read signal RD and a write signal WR, which are control signals, to the RAM (memory means) 2A and sends and receives data via the data bus DB. The memory capacity of the RAM 2A is, for example, 64 KB, which is the same as the address space of the CPU 1.

The well-known chip select signal generating section 3 decodes the address data transmitted on the address bus AB and generates a chip select signal CS1 which becomes active when the work area 52 of the RAM 2A is accessed. is there.

The data holding unit 4 is composed of well-known ports, latches, etc., and temporarily holds the data sent on the data bus DB according to the control signal LS given from the CPU 1. is there.

The selection signal generating section 5 decodes the address data transmitted on the address bus AB to generate a selection signal SE which becomes active when the expansion RAM space 54 of the RAM 2A is accessed. is there.

The address selection unit 6 inputs the data held in the data holding unit 4 and the address data of the address bus AB, and if the selection signal SE is in the active state, the former data is In the inactive state, the latter data is selected and sent to the address terminal of the RAM 2A.

The OR gate 7 shifts the RAM 2A to the operating state by applying the chip select signal CS to the RAM 2A when either one of the chip select signal CS1 and the select signal SE becomes the active state ("L"). Is. It should be noted that both the chip select signal CS1 and the select signal SE do not become active at the same time.

Address control means 8 is constituted by the data holding section 4, the selection signal generating section 5, and the address selecting section 6 described above.
Is configured.

The ROM 9 stores a program, and the CPU 1 operates according to the program in the ROM 9.

Next, the operation will be described with reference to FIGS. When accessing the work area 52 shown in FIG. 2, the CPU 1 transfers the address data (C000H to FFFFH) corresponding to the work area 52 to the address bus AB.
Send to. The chip select signal generator 3 decodes the address data and supplies the chip select signal CS1 in the active state (“L”) to the chip select input terminal CS of the RAM 2A via the OR gate. On the other hand, since the selection signal SE is inactive (“H”), the address selection unit 6 selects the address data input to the address bus AB side and sends it to the RAM 2A. As a result, RAM2
The work area 52 of A is accessed.

On the other hand, when the expansion RAM space 54 shown in FIG. 2 is accessed, the CPU 1 sends out predetermined I / O address data Di to the address bus AB, and the address (0000) of the expansion RAM space 54 to be accessed.
H to BFFFH) is sent to the data bus DB. In this embodiment, the bit width of the address data is 16 bits, which is twice the bit width of the data bus DB, which is 8 bits.
The address data may be divided into upper and lower parts and held in the data holding section 4.

The selection signal generator 5 to which the predetermined I / O address data Di is input generates the selection signal SE in the active state (“L”) and supplies it to the address selector 6. As a result,
The address selection unit 6 selects the extended address data held in the data holding unit 4 and supplies it to the RAM 2A. At this time, the chip select input terminal CS of the RAM 2A is
The selection signal SE in the active state (“L”) is OR gate 7
Have been entered through. As a result, the expanded RAM space 54 of the RAM 2A is accessed.

Further, when accessing the ROM not shown in FIG. 1, it is sufficient to access the address (0000H to XXXXXH) corresponding to the ROM space 44 shown in FIG. 2, which is the same as the normal operation. Therefore, the description is omitted.

As described above, according to this embodiment,
The CPU 1 sends the predetermined I / O address data Di to the address bus AB, and at the same time, the extended R to be accessed.
When the address data of the AM space (extended memory space) 54 is sent to the data bus DB, the address control means 8 gives the address data of the extended RAM space 54 sent to the data bus DB to the RAM (memory means) 2A. As a result, the CPU 1 can access the expansion RAM space 54.

Therefore, as compared with the conventional bank switching, it is not necessary to provide the bank in the memory space of the RAM (memory means). Memory space)
Management becomes easier. Secondly, since the extended RAM space (extended memory space) can be freely set in the RAM (memory means), there are few restrictions on the configuration of the CPU address space.

The selection signal generator 5 can arbitrarily use a decoder or a decoding circuit formed by combining arbitrary logic elements. The data holding unit 4
Elements such as a port, a latch, and a register may be arbitrarily selected or used in combination, and as these elements, those provided outside the CPU 1 may be used as shown in the above-described embodiments. However, the one included in the CPU 1 may be used. The address selection unit 6
It is possible to configure by combining a digital multiplexer or arbitrary logic elements.

In this embodiment, the address control means 8
Is configured by the data holding unit 4, the selection signal generation unit 5, and the address selection unit 6, but the present invention is not limited to this, and it goes without saying that it can be realized by appropriately combining arbitrary logic circuits.

The present invention is a CPU using the address bus (16 bits) having the bit width shown in the above embodiment.
It is not limited to the memory means and memory means, but any CPU
And memory means can be used. For example, the memory capacity of the memory means 2A may be larger than the address space of the CPU 1. In that case, the address controller 8
It may be constructed so that it can process address data having a bit width corresponding to the number of address terminals of the memory means 2A. That is, the data holding unit 4 and the address selecting unit 6
Memory means 2A so that they can be retained and selected.
The address data having a bit width corresponding to the number of the address terminals may be processed.

In this embodiment, the address space of the CPU 1 has the structure shown in FIG.
Allocation of the M space 44 and the I / O address space 46 may be arbitrary. Further, the predetermined I / O address data Di is
It may be arbitrarily selected from the I / O address space and is not particularly limited.

[0036]

As described above in detail, according to the extended memory control circuit of the present invention, it is not necessary to provide a bank in the memory space of the memory means. Management of the memory space becomes easy, and restrictions on the configuration of the CPU address space are reduced,
The extended memory space can be freely configured.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of an embodiment of an extended memory control circuit of the present invention.

FIG. 2 is a memory map in the same embodiment.

FIG. 3 is a memory map when conventional bank switching is used.

FIG. 4 is a circuit diagram showing an example of a conventional circuit for performing bank switching.

[Description of Reference Signs] 1 CPU 2A RAM (memory means) 8 address control means 4 data holding unit 5 selection signal generation unit 6 address selection unit 40 CPU address space 42 RAM space 46 I / O address space 50 RAM memory space 52 Work area 54 Extended RAM space (extended memory space) DB data bus AB address bus CS1 chip select signal SE select signal Di predetermined I / O address data

Claims (2)

[Claims] 1. A CPU, a memory means, and an address control means, wherein a memory space of the memory means is at least the CP.
It is divided into a work area assigned to the U address space and an extended memory space. When the CPU accesses the work area, the CPU sends address data corresponding to the work area to an address bus. When accessing the extended memory space, a predetermined I / O address data is sent to an address bus, and address data corresponding to the extended memory space is sent to a data bus. When address data corresponding to the work area is sent to the bus,
An extended memory control circuit, wherein data of an address bus is given to the memory means, and when the predetermined I / O address data is sent to the address bus, data of the data bus is given to the memory means. . 2. The address control means includes a selection signal generation section,
It has a data holding unit and an address selection unit, and the selection signal generation unit generates a selection signal that becomes active only when the CPU accesses a predetermined I / O address assigned to the address space of the CPU. The data holding unit holds data input from a data bus, and the address selecting unit addresses the data held by the data holding unit when the selection signal is in an active state. 2. The extended memory control circuit according to claim 1, wherein the extended memory control circuit is provided as data to the memory means, and when the selection signal is in an inactive state, the address data of an address bus is provided to the memory means.