JPH09244963A - Ic memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an efficient IC memory for an ECC(error correction code) without the need of storage capacity more than required. SOLUTION: This IC memory for storing the ECC added to main data is provided with mutually independent plural memory parts 2 and 5 for which a data length per address corresponds to the bit length of the ECC and state switching parts 3 and 6 respectively provided corresponding to the respective memory parts 2 and 5 for switching the operating state of the corresponding memory parts corresponding to selection signals from the outside respectively inputted to mutually independent input terminals at the time of reading and writing the data to the respective memory parts 2 and 5. The respective state switching parts 3 and 6 switch the corresponding memory parts 2 and 5 to an active state or a standby state from the inputted selection signals and the respective selection signals are respectively set to the respective state switching parts 3 and 6 so as to switch the desired one memory part 2 or 5 to the active state.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC memory used as a memory card in a PC card conforming to the PCMCIA standard, and is particularly necessary when constructing a memory card that requires higher reliability. I used to store redundant data of ECC (error correction code)
It relates to the C memory.

[0002]

2. Description of the Related Art FIG. 8 shows an IC using a conventional SRAM.
It is the schematic which showed the structural example of the pin in a memory. In FIG. 8, the IC memory 70 includes a plurality of data input / output pins I / O, a plurality of address input pins A, a write enable input pin / WE, an output enable input pin / OE, and a chip select input pin / WE. It has a CS, a pin VDD connected to the + side of the power supply voltage, and a pin GND connected to the-side of the power supply voltage.

The write enable input pin / WE is
It is used to set the IC memory 70 to either write or read operation, and the output enable input pin / OE is used to switch whether or not to interrupt each data input / output pin I / O. It Also,
The chip select input pin / CS is used to switch the memory to either an active state where it can perform read and write operations or a standby state where it cannot read and write. Where VDD and GND
Is a terminal for supplying power to the so-called IC memory 70. For example, VDD is connected to + DC5V and GND is grounded. In addition, / used in the above-mentioned / WE, / OE and / CS indicates the inversion of the signal level.

The IC memory 70 has the output enable input pin / OE and the chip select input pin / OE.
When both CS are "L" and the write enable input pin / WE is "H", a read cycle mode for performing a read operation is set, which is designated by the address data input to each address input pin A. The data stored at the address is output from the data input / output pin I / O. Further, the IC memory 70 is in the write cycle mode for performing the write operation when the output enable input pin / OE, the chip select input pin / CS and the write enable input pin / WE are all "L", and The data input to the data input / output pin I / O is stored in the address designated by the address data input to each address input pin A. In this way, the chip select input pin / CS
Becomes "L", the IC memory 70 becomes the active state.

Further, the IC memory 70 enters the standby state when either the output enable input pin / OE or the chip select input pin / CS becomes "H", but the output enable input pin / OE becomes "H" and chip select input pin / CS is "L"
At this time, the current consumption of the IC memory 70 does not change, and each data input / output pin I / O is simply cut off. On the other hand, when the chip select input pin / CS becomes “H”, each data input / output pin I / O is cut off, and
The current consumption of the IC memory 70 is greatly reduced.

[0006]

Here, in the IC memory 70 using the SRAM as described above, most of the defects in the medium capacity of 4 Mbit and the large capacity of 16 Mbit are 1 bit. This is an error, and a known method using ECC is performed when correcting the 1-bit error. In this method, the main data is redundant data E
CC is added. For example, when the number of bits of main data is 8 bits, when the error detection is performed by 1 bit and the error correction is performed by 1 bit, the number of bits used for ECC becomes 4 bits, 2 bit error detection,
At the same time, when error correction is performed by 1 bit, the number of bits used for ECC is 5 bits.

Thus, for example, when the number of bits of the main data is 8 bits and the number of bits of the ECC is 5 bits, 5 bits of ECC are added to 8 bits of the main data and 13 bits are written and read as one unit. Need to do. However, an IC memory having a configuration in which 5-bit data is stored in one address (hereinafter referred to as × 5 bit configuration) is not generally used, and a configuration in which 8-bit data is stored in one address (hereinafter , X8-bit configuration) is common, for example, as a main memory for storing main data, 4Mbit (512K)
B × 8 bit) IC memory is required, ECC
Also as an ECC memory for storing the data of
The same IC memory as the main memory is required.

Therefore, in a memory card of a PC card conforming to the PCMCIA standard, when the reliability is improved by using the ECC, an IC memory having a storage capacity larger than necessary is required as the ECC memory. As a result, the mounting area is widened even when the main memory and the ECC memory are mounted, and the efficiency is deteriorated in all aspects. For these reasons, in order to improve the reliability by using the ECC, there is a problem that the ECC memory unnecessarily increases its cost and becomes expensive. The present invention has been made to solve such a problem, and as an ECC memory,
An object of the present invention is to obtain an efficient IC memory which does not require a storage capacity larger than necessary.

[0009]

SUMMARY OF THE INVENTION The present invention is an IC memory used to store an ECC added to main data,
Alternatively, it is done in an IC memory using SRAM, which is used to store the ECC added to the main data. That is, according to the present invention, in such an IC memory, a plurality of independent memory units, for example, a pair of memory units whose data length per address corresponds to the bit length of the ECC, are provided corresponding to the respective memory units. At the same time, at the time of reading and writing data to each memory unit, a state switching unit that switches the operating state of the corresponding memory unit in accordance with external selection signals input to input terminals that are independently provided, According to the input selection signal, each of the state switching units puts the corresponding memory unit into either an active state in which data can be written and read, or a standby state in which data cannot be written and read. With switching
The respective selection signals are output to the desired 1
The present invention provides an IC memory, which is set so that two memory units are switched to an active state.

The data length per address is EC
A plurality of memory units independent of each other corresponding to the bit length of C, and an operation state of the corresponding memory units according to external selection signals input to input terminals at the time of reading and writing data to each memory unit. And a state switching unit for switching the state of the corresponding memory unit in accordance with the input selection signal in each of the state switching units, in an active state in which data can be written and read, or in which data cannot be written and read. It is also possible to switch to any one of the standby states and to switch only one desired memory unit to the active state. Further, the IC memory as described above is formed in the same package as the IC memory for storing the main data.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described in detail based on an embodiment shown in the drawings. Embodiment 1. FIG. 1 is a schematic diagram showing an example when an SRAM is used in the IC memory according to the first embodiment of the present invention. In FIG. 1, an IC memory 1 includes a first memory 4 having a first memory section 2 and a first state switching section 3, and a second memory having a second memory section 5 and a second state switching section 6. It consists of 7. The first memory unit 2 and the second memory unit 5 in FIG. 1 have respective functional parts provided in a conventional IC memory using SRAM, but here, in order to make the description easy to understand, Omitted.

The first memory 4 and the second memory 7 form a pair of independent memories having the same structure as the conventional IC memory, and the first memory section 2 and the second memory section 5 are formed. The data length of one address corresponds to the bit length of ECC, the first state switching unit 3 is connected to the first memory unit 2, and the second state switching unit is connected to the second memory unit 5. The part 6 is connected. In addition, IC memory 1
Are a plurality of data input / output pins I / O, a plurality of address input pins A, a write enable input pin / WE, an output enable input pin / OE, a first chip select input pin / CS1, and a second Chip select input pin / CS2 and pin VDD connected to + side of power supply voltage
And a pin GND connected to the negative side of the power supply voltage.

The data input / output pin I / O, the address input pin A, the write enable input pin / WE and the output enable input pin / OE are connected to the first memory section 2 and the second memory section 5, respectively. They are connected in parallel inside the IC memory 1, the first chip select input pin / CS1 is connected to the first state switching unit 3, and the second chip select input pin / CS2 is the second state. It is connected to the switching unit 6. The above / W
Used in E, / OE, / CS1 and / CS2 /
Indicates the inversion of the signal level.

The write enable input pin / WE is
The output enable input pin / OE is used to set the first memory unit 2 and the second memory unit 5 to either write or read operation, and the output enable input pin / OE is used to store data from the data input / output pins I / O. It is used to switch whether to block input / output. Further, the first chip select input pin / CS1 connects the first memory unit 2 to
The second chip select input pin / CS2 is used to switch the second memory unit 5 into either an active state in which read and write operations can be performed or a standby state in which read and write operations cannot be performed. Here, VDD and GND are terminals for supplying power to the so-called IC memory 1, for example, VDD is connected to + DC5V and GND is grounded.

When the first chip select input pin / CS1 goes "L", the first state switching section 3 activates the first memory section 2 to set the first chip select input pin / CS.
When CS1 becomes “H”, the first memory unit 2 is put in a standby state. When the output enable input pin / OE is "L" and the write enable input pin / WE is "H" when the first memory unit 2 is in the active state,
It becomes the mode of the read cycle to perform the read operation,
The data stored at the address designated by the address data input to each address input pin A is
The data is output from each data input / output pin I / O. When the output enable input pin / OE and the write enable input pin / WE are both "L" when in the active state, the first memory unit 2 enters a write cycle mode in which a write operation is performed. The data input to each data input / output pin I / O is stored in the address designated by the address data input to each address input pin A.

Similarly, the second state switching section 6 activates the second memory section 5 when the second chip select input pin / CS2 becomes "L", and the second chip select input pin / CS2 becomes low. When it becomes “H”, the second memory unit 5
To wait. When the output enable input pin / OE is "L" and the write enable input pin / WE is "H" in the active state, the second memory unit 5 performs a read cycle of a read operation. The mode is entered, and the data stored at the address designated by the address data input to each address input pin A is output from each data input / output pin I / O.
Further, the second memory unit 5 is
When the output enable input pin / OE and the write enable input pin / WE are both "L", a write cycle mode for performing a write operation is set, and the data input to each of the data input / output pins I / O is The data is stored in the address designated by the address data input to each address input pin A.

The first memory unit 2 is in the standby state when either the output enable input pin / OE or the first chip select input pin / CS1 becomes "H". Pin / OE
Is "H" and the first chip select input pin / CS1
Is "L", the current consumption of the first memory unit 2 does not change, and the input / output of data from the first memory unit 2 performed at each data input / output pin I / O is simply blocked. On the other hand, when the first chip select input pin / CS1 becomes “H”, the input / output of data from the first memory unit 2 performed by each data input / output pin I / O is blocked, and the first memory The current consumption of the unit 2 is greatly reduced, which is effective when data is saved by backing up with a battery or the like. The same applies to the second memory unit 5.

The first chip select input pin /
CS1 and the second chip select input pin / CS2 are
A chip select signal is input so that the first memory unit 2 and the second memory unit 5 are not activated at the same time. That is, the first chip select input pin / CS1 and the second chip select input pin / CS2 are not simultaneously supplied with the "L" chip select signal. The first memory unit 2 and the second memory unit 5 form a memory unit, the first state switching unit 3 and the second state switching unit 6 form a state switching unit, and the chip select signal forms a selection signal. The first chip select input pin / CS1 and the second chip select input pin / CS2 form an input terminal for inputting the select signal.

Here, for example, when error detection is performed for 2 bits and error correction is performed for 1 bit at the same time, the following (1)
The number of ECC bits is determined so as to satisfy the expression. 2 ^(k-1) -1 ≧ m + k (1) In the above equation (1), k is the number of bits of ECC and m is the number of bits of main data. From the above formula (1), when the bit number m of the main data is 8 bits, the bit number k of the ECC becomes 5 bits, and E becomes 8 bits of the main data.
It is necessary to add 5 bits of CC and write and read 13 bits as one unit. In this case, the first memory unit 2 and the second memory in the IC memory 1 used as a memory for ECC are used, as compared with the conventional IC memory having a × 8 bit structure which constitutes a main memory for storing main data. The section 5 has a × 5 bit configuration.

As described above, the IC memory 1 is the SRAM
The two memories, that is, the first memory 4 and the second memory 7 having the same structure as the conventional IC memory using the above, are paired and have the same size as the conventional IC memory used for storing the main data. It is housed and formed in the package.

Next, the IC memory 1 shown in FIG.
An example of using it as a memory for CC will be described. FIG. 2 shows a configuration in which 16-bit data is stored at one address in conformity with the PCMCIA standard (hereinafter referred to as × 16.
2 is a schematic diagram showing an example when the IC memory 1 shown in FIG. 1 is used as a memory for ECC in a memory card having a bit configuration). Further, FIGS. 3 and 4 show each I according to the signal level of the chip select signal input to each chip select input pin in the example shown in FIG.
It is a figure showing operation of C memory. 2 to 4, the same components as those in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted here. Further, in FIG. 3 and FIG. 4, each output enable input pin / OE is "L" for the sake of easy understanding of the description, and only the flow of address data, main data and ECC is shown.

FIG. 2 shows a state in which the IC memory 1 is used as an ECC memory as opposed to the conventional IC memories 51 and 52 which constitute the main memory for storing main data. In a memory card having a × 16-bit configuration, the storage capacity is increased by increasing the pair of IC memories having a × 8-bit configuration, so that the IC memories 51 and 52 having a × 8-bit configuration form a pair. The first memory 4 of the IC memory 1 is used as the conventional IC memory 51, and the second memory 7 of the IC memory 1 is used as the ECC memory for the conventional IC memory 52.

In this case, in the IC memory 1 and the conventional IC memories 51 and 52, each address input pin A, VDD
The pin, the GND pin, the write enable input pin / WE, and the output enable input pin / OE are connected in parallel. Further, each data input / output pin I / O of the IC memory 51 is connected to a first ECC circuit 55 provided in the memory card for adding ECC to the main data, and each data input / output pin of the IC memory 52 is connected. Each I / O is connected to a second ECC circuit 56 provided in the memory card for adding ECC to the main data. Further, each data input / output pin I / of the IC memory 1
O is connected to the first and second ECC circuits 55 and 56, respectively.

The chip select input pin / CS51 of the IC memory 51 is connected to the first chip select input pin / CS51 connected to the first state switching section 3 in the first memory 4.
CS1 is connected and chip select input pin / CS51
The chip select signal that is input to is also input to the first chip select input pin / CS1 at the same time. From this fact, when the chip select input pin / CS51 becomes "L", the IC memory 51 becomes active, and when it becomes "H", the IC memory 51 becomes in the standby state. The one memory unit 2 is in the active or standby state at the same time.

Similarly, the chip select input pin / CS52 of the IC memory 52 is connected to the second chip select input pin / CS2 connected to the second state switching section 6 in the second memory 7. From this, the IC memory 52
Then, the second memory unit 5 in the second memory 7 can be in the active or standby state at the same time. The above / C
The symbol / used in S51 and / CS52 indicates the inversion of the signal level.

With the above configuration, as shown in FIG.
When the chip select signal of "L" is input to the chip select input pin / CS51 and the first chip select input pin / CS1, the IC memory 51 and the first memory unit 2 become active and each address input pin At the address indicated by the address data input to A,
The IC memory 51 is connected to the 8th memory via the first ECC circuit 55.
The first memory unit 2 stores bit main data, and the first memory unit 2 receives the IC memory 51, which is input from the first ECC circuit 55.
A 5-bit ECC corresponding to the main data stored in is stored. At this time, chip select input pin / CS52
And "H" on the second chip select input pin / CS2
The chip select signal is input, and the IC memory 52 and the second memory unit 5 are in the standby state.

Next, as shown in FIG. 4, the chip select input pin / CS51 and the first chip select input pin / CS51
When the "H" chip select signal is input to CS1 and the "L" chip select signal is input to the chip select input pin / CS52 and the second chip select input pin / CS2, the IC memory 51 and the first memory The IC memory 52 and the second memory unit 5 become active while the section 2 is in the standby state, and the address indicated by the address data input to each address input pin A is
The IC memory 52 is connected to the 8th memory via the second ECC circuit 56.
The bit memory main data is stored, and the second memory unit 5 receives the IC memory 52 input from the second ECC circuit 56.
A 5-bit ECC corresponding to the main data stored in is stored.

The IC memory 1 is the same as the conventional I memory.
It is formed in a package having the same size as the C memories 51 and 52. For example, if the conventional IC memories 51 and 52 each have a storage capacity of 4 Mbits, the IC memory 5
1, 52 are data input / output pins I / O 8 pins, address input pins A 19 pins, power supply pins VDD and GND pins 1 each, write enable input pin / WE, output Enable input pin /
A 32 pin package consisting of 1 pin each of OE and chip select input pin / CS is used.

On the other hand, each of the first memory section 2 and the second memory section 5 in the IC memory 1 has a structure of × 5 bits, and the IC memory 1 has the data input / output pin I /
5 pins of O, 19 pins of address input pin A, 1 pin of each of VDD and GND pins for power supply, write enable input pin / WE, output enable input pin / OE, first and second chips Select input pin /
3 consisting of 1 pin for each of CS1 and / CS2 and 2 free pins
It is formed of a 2-pin package.

Next, in FIGS. 2 to 4 described above, an example in which two 5-bit ECCs are stored for one address in the IC memory for one ECC according to the present invention is shown. 5 bits ECC for address 1
An example will be described in which two addresses are stored and the number of addresses is doubled. FIG. 5 shows a memory card having a structure in which 8-bit data is stored at one address, and the IC shown in FIG.
It is the schematic which showed the example when the memory 1 is used as a memory for ECC. 6 and 7 are diagrams showing the operation of each IC memory according to the signal level of the chip select signal input to each chip select input pin in the example shown in FIG. 5 to 7, the same components as those in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted here. Further, in FIG. 6 and FIG.
For the sake of clarity, each output enable input pin / OE is "L" and the address data,
A flow of only main data and ECC is shown.

FIG. 5 shows a state in which one of the IC memories 1 is used as an ECC memory as opposed to the conventional IC memories 61 and 62 which constitute the main memory for storing main data. In a memory card having a × 8-bit configuration, the storage capacity is increased by increasing the IC memory having a × 8-bit configuration one by one. Therefore, the first memory 4 of the IC memory 1 is different from the conventional IC memory 61. In contrast to the conventional IC memory 62, the second memory 7 of the IC memory 1 is used as an ECC memory.

In this case, in the IC memory 1 and the conventional IC memories 61 and 62, each data input / output pin I / O,
Each address input pin A, VDD pin, GND pin, write enable input pin / WE and output enable input pin / OE are connected in parallel. Further, each data input / output pin I / O in each IC memory 1, 61, 62 is provided with an ECC circuit 6 provided in the memory card for adding ECC to main data.
5 is connected.

Further, the chip select input pin / CS61 of the IC memory 61 is connected to the first chip select input pin / CS61 connected to the first state switching section 3 in the first memory 4.
CS1 is connected and chip select input pin / CS61
The chip select signal that is input to is also input to the first chip select input pin / CS1 at the same time. From this, when the chip select input pin / CS61 becomes "L", the IC memory 61 becomes active, and when it becomes "H", I
If the C memory 61 is set to the standby state, the IC memory 61 and the first memory unit 2 are simultaneously set to the active or standby state.

Similarly, the chip select input pin / CS62 of the IC memory 62 is connected to the second chip select input pin / CS2 connected to the second state switching section 6 in the second memory 7, and the IC memory 62 and second memory unit 5
Can be active or standby at the same time. In addition, / used in the above-mentioned / CS61 and / CS62 indicates the inversion of the signal level.

With the above structure, as shown in FIG.
When an "L" chip select signal is input to the chip select input pin / CS61 and the first chip select input pin / CS1, the IC memory 61 and the first memory unit 2 are activated and each address input pin At the address indicated by the address data input to A,
The IC memory 61 stores the 8-bit main data via the ECC circuit 65, and the first memory unit 2 stores the ECC data.
The 5-bit ECC corresponding to the main data input from the circuit 65 and stored in the IC memory 61 is stored.
At this time, the chip select input pin / CS62 and the second
The chip select signal of "H" is input to the chip select input pin / CS2, and the IC memory 62 and the second memory section 5 are in the standby state.

Further, as shown in FIG. 7, the chip select input pin / CS61 and the first chip select input pin / CS61
When the "H" chip select signal is input to CS1 and the "L" chip select signal is input to the chip select input pin / CS62 and the second chip select input pin / CS2, the IC memory 61 and the first memory The IC memory 62 and the second memory section 5 become active while the section 2 is in the standby state, and the address indicated by the address data input to each address input pin A becomes
The IC memory 62 stores the 8-bit main data via the ECC circuit 65, and the second memory unit 5 stores the ECC data.
A 5-bit ECC corresponding to the main data stored in the IC memory 62, which is input from the circuit 65, is stored.

As described above, according to the IC memory of the first embodiment of the present invention, the first state switching section 3 has
According to a chip select signal from the outside input to the first chip select input pin / CS1 at the time of reading and writing data to the first memory unit 2, the first memory unit 2 is set to the active state or the standby state. , And similarly, the second state switching unit 6 causes the second state switching unit 6 to switch to the second state.
In accordance with an external chip select signal input to the second chip select input pin / CS2 at the time of reading and writing data to the memory unit 5, the second memory unit 5 is
Switch to either the active state or the standby state.

From the above, among the first state switching section 3 and the second state switching section 6, for the desired state switching section,
By setting the chip select signal so that the state of the corresponding memory unit is set to the active state, the first memory unit 2 and the second memory unit 5 can share the address, and for one address. Independent ECC can be stored in the first memory unit 2 and the second memory unit 5, respectively. Further, different addresses independent of each other are provided to the first memory unit 2 and the second memory unit 5, and one EC is provided for one address.
If C is stored, the number of addresses of the IC memory for storing ECC can be doubled.

Further, the first memory section 2 and the second memory section 5
Since the data length per address in (1) is set to the ECC bit length, it is possible to eliminate the inefficiency of using a conventional IC memory having a storage capacity larger than necessary. For these reasons, the IC memory for ECC can be used more efficiently than the conventional IC memory, and the cost can be reduced.

Further, the first state switching section 3 and the second state switching section 6 each have an independent chip select input pin for inputting the chip select signal, from which the main data is stored. By inputting the chip select signal input to the chip select input pin included in the conventional IC memory using the SRAM that constitutes the main memory for One IC that constitutes the memory
One of the first memory unit 2 and the second memory unit 5 can be associated with the memory and used as an ECC memory for storing ECC data. For this reason, one IC memory 1 can be used as an ECC memory for two IC memories used in the main memory, and can be used as compared with a conventional IC memory having a storage capacity larger than necessary. It is possible to improve efficiency.

Further, since the IC memory 1 is formed in a package having the same size as the above-mentioned conventional IC memory used as a main memory, ECC is used in a memory card such as a PC card conforming to the PCMCIA standard. In order to improve reliability, in addition to not requiring an IC memory having a storage capacity larger than necessary as an ECC memory, in mounting the main memory and the ECC memory,
Efficient implementation can be performed. In this way, it is possible to obtain an efficient IC memory for ECC that can improve efficiency from all points, and it is possible to reduce costs.

In the first embodiment, one IC memory 1 is provided with the first memory section 2 and the first state switching section 3.
The first memory 4 including the above and the second memory 7 including the second memory unit 5 and the second state switching unit 6 are provided as an example, but the present invention is not limited to this. One IC memory 1 may include three or more memories including a memory unit and a state switching unit. Further, although the case where the SRAM is used is shown in the first embodiment, a memory such as a DRAM may be used.

In the first embodiment, the first
Although the memory 4 and the second memory 7 are each provided with a state switching unit, one state switching unit 90 may be provided for the first memory unit 2 and the second memory unit 5, and in this case, the one state switching unit 90 is provided. The state switching unit 90 is connected to the first memory unit 2 and the second memory unit 5, respectively, and either the first memory unit 2 or the second memory unit 7 is selected according to a selection signal input from one input terminal. Exclusively activate one desired memory unit.

[0044]

As is apparent from the above description, according to the IC memory of the present invention, each of the state switching units is externally input at the time of reading and writing the data to each of the memory units. According to the selection signal, the corresponding memory unit is switched to either the active state in which data can be written or read, or the standby state in which data cannot be written and read,
By setting the selection signal so that the state of the corresponding memory unit is activated to a desired one of the state switching units, the memory units can share the address. The same number of ECCs as the number of memory units can be stored for one address.

Further, if each memory section is provided with a different address independent from each other without sharing the address and one ECC is stored at one address, an IC memory for storing the ECC The number of addresses can be increased to the number obtained by multiplying the number of memory units. Further, since the data length per address in each memory unit is set to the ECC bit length, it is possible to eliminate the inefficiency of using a conventional IC memory having a storage capacity larger than necessary. from these things,
The IC memory of the present invention, as an IC memory for ECC,
The IC memory can be used more efficiently than the conventional IC memory and the cost can be reduced.

Further, each state switching section has an independent input terminal for inputting the selection signal, corresponding to each memory section. From this fact, the main memory for storing the main data. One IC memory forming a main memory by inputting a chip select signal input to a chip select input terminal provided in a conventional IC memory On the other hand, one of the above memory units can be associated and used as an ECC memory for storing ECC data. Therefore, I of the present invention
Multiple I's used in main memory for one C memory
It can be used as an ECC memory for the C memory, and the efficiency can be improved as compared with the case of using a conventional IC memory having a storage capacity larger than necessary.

Further, since the IC memory of the present invention is formed in the same package as the conventional IC memory used for the main memory, the ECC is used in the memory card in the PC card conforming to the PCMCIA standard or the like. In order to improve reliability by using an IC memory having a storage capacity larger than necessary as an ECC memory, in addition to mounting the main memory and the ECC memory,
Efficient implementation can be performed. In this way, it is possible to obtain an efficient IC memory for ECC that can improve efficiency from all points, and it is possible to reduce costs.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing an example of an IC memory according to a first embodiment of the present invention.

FIG. 2 is a schematic diagram showing an example in which the IC memory 1 shown in FIG. 1 is used as a memory for ECC.

FIG. 3 is a diagram showing an operation of each IC memory according to a signal level of each chip select input pin in FIG.

FIG. 4 is a diagram showing an operation of each IC memory according to a signal level of each chip select input pin in FIG.

5 is a schematic diagram showing another example in which the IC memory 1 shown in FIG. 1 is used as a memory for ECC.

FIG. 6 is a diagram showing an operation of each IC memory according to a signal level of each chip select input pin in FIG.

FIG. 7 is a diagram showing an operation of each IC memory according to a signal level of each chip select input pin in FIG.

FIG. 8 is a schematic diagram showing an example of a conventional IC memory.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 IC memory, 2 1st memory part, 3 1st state switching part, 4 1st memory, 5 2nd memory part, 6
Second state switching unit, 7 second memory, / CS1 first chip select input pin, / CS2 second chip select input pin

Claims (4)

[Claims] 1. An IC memory used for storing an ECC added to main data, comprising: a plurality of independent memory units whose data length per address corresponds to the bit length of the ECC; and each of the memory units. Corresponding to each of the memory units, and switches the operating state of the corresponding memory unit according to external selection signals input to input terminals independently of each other at the time of reading and writing data to each memory unit. Each of the state switching units has an active state in which data can be written and read, or a standby state in which data cannot be written and read, according to the input selection signal. While switching to any one of the states, the selection signals are transmitted to the respective state switching units by one desired memory. An IC memory, which is set so as to switch each memory unit to an active state. 2. An IC memory using an SRAM, which is used to store an ECC added to main data, comprising: a pair of independent memory units in which a data length per address corresponds to a bit length of the ECC. , Corresponding to the respective memory units, and corresponding to the memory units according to external selection signals input to input terminals independently provided at the time of reading and writing data to the memory units. And a state switching unit for switching the operating state of, each of the state switching units, according to the input selection signal, the corresponding memory unit is in an active state in which writing and reading of data, or writing and reading of data. While switching to either of the standby states in which reading is not possible, the selection signals are sent to the state switching units. Then, an IC memory is set such that one desired memory unit is switched to an active state. 3. An IC memory used for storing an ECC added to main data, wherein a plurality of memory units each having a data length per address corresponding to a bit length of the ECC and independent memory units are provided. When reading and writing the data in
A state switching unit that switches the operating state of the corresponding memory unit in accordance with an external selection signal input to each input terminal, and each state switching unit switches the corresponding memory unit in accordance with the input selection signal. In addition to switching to an active state in which data can be written and read or a standby state in which data cannot be written and read, only one desired memory unit is switched to an active state. IC memory. 4. The IC memory according to any one of claims 1 to 3, wherein the IC memory is formed in the same package as an IC memory storing main data to which the ECC is added. IC memory characterized by.