JPH04132480A - Picture display system - Google Patents

Abstract

PURPOSE:To reduce the capacity required for an address conversion RAM by dividing display addresses into horizontal and vertical directions and connecting horizontal and vertical display address conversion RAMs to each display address bus so as to apply conversion processing to the horizontal and vertical display addresses. CONSTITUTION:The system is provided with a horizontal display address counter 2 receiving a display clock from a display clock generating circuit 1 and outputting a horizontal display address, a vertical display address counter 3 outputting a vertical display address, a horizontal display address conversion RAM 6 whose address input receives a horizontal display address, a vertical display address conversion RAM 7 whose address input receives a vertical display address, a picture memory 10, a D/A converter 11 converting a picture data read from the picture memory 10 into a video signal and sending the video signal to a display device and a microcomputer 12 controlling the changeover of changeover devices 4, 5, 8, 9 to switch the data in the RAMs 6, 7. Thus, the capacity required for an address conversion RAM is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image display method, and more particularly to a display method that moves a display position of a display image, and enlarges/reduces the display image.

[Conventional technology]

In the conventional technology, as shown in FIG. 2, a display address counter 102 that receives a display clock from a display clock generation circuit 101 generates a display address, and this display address is passed through a display address switch 103 and then displayed. The address conversion RAM 104 converts and outputs the display address according to the internal data, and inputs the converted display address to the address terminal of the image memory 106 through the memory address switch 105. The image memory outputs image data according to the input display address, and the DA converter 1
07, it was converted into a video signal and output.

To change the position, size, etc. of the displayed image, use the microprocessor 108 to switch the display address switch 103 and the memory address switch 105 to change the address bus of the address conversion RAM 104 and the address bus of the microprocessor sensor 108. and the data bus of the address conversion RAM 104 and the microprocessor 108.
After the microprocessor 108 changes the data inside the address conversion RAM 104,
The display address switch 103 and memory address switch 105 were returned to their initial states again, and images were displayed.

[Problem to be solved by the invention]

In the conventional image display method described above, all display address values generated by the display address counter 102 are converted by the address conversion RAM 104, so the address conversion RAM requires a large capacity. For example, in the case of a display device with a resolution of 640 horizontal dots x 400 vertical lines, the address conversion RAM would require a large capacity of 4,608,000 bits.

An object of the present invention is to provide an image display method that can significantly reduce the capacity required for address conversion RAM.

[Means to solve the problem]

The image display method of the present invention includes: a horizontal display address counter that receives a display clock at its input and outputs a horizontal display address; a vertical display address counter that receives a display clock at its input and outputs a vertical display address; A horizontal display address conversion memory to which a horizontal display address is connected; a vertical display address conversion memory to which the vertical display address is connected to an address input; a data bus of the horizontal display address conversion memory and data of the vertical display address conversion memory. The present invention is characterized by comprising: an image memory to which each bus is connected to an address input and outputs image data according to the input address; and rewriting means for rewriting the contents of the horizontal and vertical display address conversion memories, respectively.

According to the image display method of the present invention, the rewriting means includes a microprocessor, an address bus from the horizontal display address counter,
a horizontal display address bus switch for switching between the address bus from the microprocessor; a vertical display address bus switch for switching between the address bus from the vertical display address counter and the address bus from the microprocessor; and a vertical display address bus switch for switching between the address bus from the vertical display address counter and the address bus from the microprocessor; a horizontal memory address switch connected to the translation memory and switching a data bus to the image memory and a data bus to the microprocessor; and a horizontal memory address switch connected to the vertical display address translation memory and switching the data bus to the image memory and the microprocessor. a vertical memory address switch for switching a data bus to a data bus; The present invention is characterized in that it controls switching of the horizontal display address conversion memory and the vertical display address conversion memory, and rewrites data in the horizontal display address conversion memory and the vertical display address conversion memory.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a circuit block diagram of an embodiment of the present invention.

This image display method consists of a display clock generation circuit 1 that generates a display clock, a horizontal display address counter 2 that receives a display clock from the display clock generation circuit and outputs a horizontal display address, and a display clock generation circuit 1 that generates a display clock. a vertical display address counter 3 that receives a display clock and outputs a vertical display address; a horizontal display address bus switch 4 that switches between an address bus from the horizontal display address counter 2 and an address bus from a microprocessor 12 (described later); A vertical display address bus switch 5 that switches between the address bus from the display address counter 3 and the address bus from the microprocessor 12, a horizontal display address conversion RAM 6 to which a horizontal display address is connected to the address input, and a vertical display address bus to which the address input is connected. A horizontal memory address switch connected to the vertical display address conversion RAM 9 to which addresses are connected, the image memory 10, and the horizontal display address conversion RAM 6, and which switches the data bus to the image memo 1/O and the data bus to the microprocessor 12. 8, a vertical memory address switch 9 which is connected to the vertical display address conversion RAM 7 and switches the data bus to the image memory 10 and the data bus to the microprocessor 12, and a vertical memory address switch 9 which is connected to the vertical display address conversion RAM 7 and which switches the data bus to the image memory 10 and the data bus to the microprocessor 12; DA that converts into a signal and sends it to a display device (not shown)
It includes a converter 11 and a microprocessor 12 that controls switching of the switchers 4, 5, 8.9, and rewrites data in the RAM 6.7.

Horizontal display address bus switch 4. Vertical display address bus switch 5. Horizontal memory address switch 8° Vertical memory address switch 9. The microprocessor 12 constitutes rewriting means.

In this example, the horizontal resolution of the display device is 640
It is assumed that the resolution dot in the vertical direction is 400 lines. Therefore, the horizontal display address requires 10 bits and the vertical display address requires 9 bits.

Next, the operation of this embodiment will be explained.

A display clock generation circuit 1 generates a display dot clock and inputs it to a horizontal display address counter 2 and a vertical display address counter 3, respectively.

The horizontal display address counter 2 counts the display addresses of dots in the horizontal direction from 0 to 639 in synchronization with the horizontal scanning period, and outputs the count to a 10-bit horizontal display address bus. The horizontal display address bus switch 4 has a first input connected to the display address bus from the horizontal display address counter 2 and a second input connected to the address bus from the microprocessor 12. Either the first or second input address bus is selected and output to the address terminal of the horizontal display address conversion RAM 6.

During the image display period, the horizontal display address bus switch 4 is switched and connected to the horizontal display address counter 2, so that a display address synchronized with the horizontal scanning cycle of the display device is input to the horizontal display address conversion RAM 6. , the data inside the horizontal display address conversion RAM 6 is read out accordingly. The data read from the horizontal display address conversion RAM 6 has a bus width of 10 bits and is input to the horizontal memory address switch 8. During the image display period, the horizontal memory address switch 8 outputs the 10-bit data input from the horizontal display address conversion RAM 6 to the lower 10-bit data bus of the image memory. By the address given to the lower side of image memo position 0,
Image data is read in the horizontal direction.

On the other hand, regarding the display in the vertical direction, the vertical display address counter 3 similarly currents the address of the display line from O to 399 in synchronization with the vertical scanning period, and outputs it to the 9-pin vertical display address bus. During the image display period, the vertical display address from the vertical display address counter 3 is input to the address of the vertical display address conversion RAM 7 via the vertical display address bus switch 5, and the vertical display address conversion R is performed according to the input vertical display address.
Nine bits of data are read from AM1 and input to the upper address bus of image memory 10 via vertical memory address switch 9.

By performing the above-described horizontal display and vertical display according to the screen scan of the display device, image data is read from the image memo January 0, and the read image data is converted into a video signal by the DA converter 11. It is converted and output to a display device.

Since the display address input to the image memory 10 is data read from the horizontal and vertical display address conversion RAM 6.7, the display address input to the image memory 10 is the data read from the horizontal and vertical display address conversion RAM 6.
By rewriting the data inside M6.7, the horizontal and vertical display addresses given to the image memory 10 can be changed. Therefore, by changing the internal data of the horizontal and vertical display address conversion RAM 6.7, it becomes possible to change the display position in the horizontal and vertical directions, enlarge or reduce the display image, etc.

To rewrite the internal data in the horizontal and vertical display address conversion RAM 6.7, the microprocessor 12 switches the horizontal and vertical display address bus switch 45 to rewrite the address bus of the microprocessor 12 and the horizontal and vertical display address conversion RAM 6. After connecting the data bus of the microprocessor 12 and the data bus of the horizontal and vertical display address conversion RAM 6.7 by switching the horizontal and vertical memory address switch 8.9, According to the processing for the display image, the data in the horizontal and vertical display address conversion RAM 6.7 is rewritten, and the horizontal and vertical display address bus switchers 4 and 5 are switched again to the horizontal and vertical display address counters 2 and 3.
8. Switch to side, horizontal and vertical memory address switcher.
9 to the address bus side of the image memory 10.

Through the above-described operations, processes such as moving the display position and enlarging/reducing the display image are performed in the horizontal and vertical directions.

As mentioned above, in this embodiment, since the resolution of the display device is 640 dots horizontally and 400 lines vertically, the horizontal display address requires 10 bits and the vertical display address requires 9 bits. Therefore, the capacity required for each of the horizontal and vertical display address conversion RAMs is: Horizontal display address conversion RAM = 640 x 10 = 6,400 bits Vertical display address conversion RAM = 400 x 9 = 3.600 bits The total of both is: It becomes 10,000 bits.

In this way, in the case of a display device with a resolution of 640 dots horizontally and 400 lines vertically, 4,608,000 bits are conventionally required, but this can be reduced to 10,000 bits in this embodiment.

〔Effect of the invention〕

As explained above, the present invention divides display addresses into horizontal and vertical directions, connects horizontal and vertical display address conversion RAMs to each display address bus, and performs conversion processing of display addresses in the horizontal and vertical directions. According to
It is possible to move the position of the displayed image, enlarge it, reduce it, etc., and at the same time, it has the effect of greatly reducing the capacity required for the address conversion RAM.

[Brief explanation of drawings]

FIG. 1 is a circuit block diagram of an embodiment of an image display method according to the present invention, and FIG. 2 is a circuit block diagram of a conventional example. ■...Display clock generation circuit 2...Horizontal display address counter 3...Vertical display address counter 4...Horizontal display address bus switch 5...Vertical display Atlus bus switch 6
... Horizontal display address conversion RAM 7 ... Vertical display address conversion RAM 8 ... Horizontal memory address switch 9 ... Vertical memory address switch, image memory, DA converter, microprocessor・Display clock generation circuit ・Display address counter ・Display address switch ・Display address conversion RAM ・Memory address switch ・Image memory ・DA converter ・Microprocessor ・Nosa

Claims (2)

[Claims] (1) A horizontal display address counter that receives a display clock at its input and outputs a horizontal display address, a vertical display address counter that receives a display clock at its input and outputs a vertical display address, and the horizontal display address is connected to the address input. a vertical display address conversion memory whose address input is connected to the vertical display address, and a data bus of the horizontal display address conversion memory and a data bus of the vertical display address conversion memory, each having an address input. 1. An image display system comprising: an image memory that is connected to an input address and outputs image data according to an input address; and rewriting means that rewrites the contents of the horizontal and vertical display address conversion memories, respectively. (2) The rewriting means includes a microprocessor, an address bus from the horizontal display address counter,
a horizontal display address bus switch for switching between the address bus from the microprocessor; a vertical display address bus switch for switching between the address bus from the vertical display address counter and the address bus from the microprocessor; and a vertical display address bus switch for switching between the address bus from the vertical display address counter and the address bus from the microprocessor; a horizontal memory address switch connected to the translation memory and switching a data bus to the image memory and a data bus to the microprocessor; and a horizontal memory address switch connected to the vertical display address translation memory and switching the data bus to the image memory and the microprocessor. a vertical memory address switch for switching a data bus to a data bus; 1. An image display method characterized by controlling switching of the horizontal display address conversion memory and the vertical display address conversion memory and rewriting data in the horizontal display address conversion memory and the vertical display address conversion memory.