JPH0377358A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPH0377358A JPH0377358A JP21361189A JP21361189A JPH0377358A JP H0377358 A JPH0377358 A JP H0377358A JP 21361189 A JP21361189 A JP 21361189A JP 21361189 A JP21361189 A JP 21361189A JP H0377358 A JPH0377358 A JP H0377358A
- Authority
- JP
- Japan
- Prior art keywords
- analog
- circuits
- circuit
- digital
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 38
- 239000000758 substrate Substances 0.000 abstract description 23
- 238000000034 method Methods 0.000 abstract 1
- 238000000926 separation method Methods 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 5
- 239000002184 metal Substances 0.000 description 4
- 238000002955 isolation Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は半導体集積回路、特にアナログ回路並びにデ
ィジクル回路が混在する大規模半導体集積回路に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to a large-scale semiconductor integrated circuit in which analog circuits and digital circuits coexist.
第2図は従来のアナログ回路並びにディジタル回路が混
在する半導体集積回路を示す断面図である。FIG. 2 is a sectional view showing a conventional semiconductor integrated circuit including both analog circuits and digital circuits.
図において、(3)は半導体基板、(4a)は半導体基
板(3)内部に形成するディジタル回路、(4b〉は半
導体基板(3)外部にディジタル回路(4a)上に積層
させるディジタル回路、(5a)は半導体基板(3)内
部にディジタル回路(4a)とは別の場所に形成するア
ナログ回路、(5b)は半導体基板+31外部にアナロ
グ回路(5a)上に積層させるアナログ回路、(6)は
ディジタル回路(4a)、 (4b)とアナログ回路(
5a)、 (5b)との電気的接続をとる金属配線、(
7)は金属配線(6)とは半導体基板(3)、ディジク
ル回路(4a)、 (4b)及びアナログ回路(5a)
、 (5b)とを分離するための絶縁膜である。In the figure, (3) is a semiconductor substrate, (4a) is a digital circuit formed inside the semiconductor substrate (3), (4b> is a digital circuit laminated on the digital circuit (4a) outside the semiconductor substrate (3), 5a) is an analog circuit formed inside the semiconductor substrate (3) at a location different from the digital circuit (4a); (5b) is an analog circuit layered on the analog circuit (5a) outside the semiconductor substrate +31; (6) are digital circuits (4a), (4b) and analog circuits (
5a), metal wiring for electrical connection with (5b), (
7) Metal wiring (6) means semiconductor substrate (3), digital circuit (4a), (4b), and analog circuit (5a)
, (5b).
次に作用について説明する。Next, the effect will be explained.
従来のアナログ回路並びにディジタル回路が混在する半
導体集積回路は上記のように構成され、半導体基板(3
)内部にディジタル回路(4a)並びに、アナログ回路
(5a)を形成し、ディジタル回路(4a)上にゲート
電極、配線、あるいは絶縁膜等を積層し、ディジタル回
路(4b)を形成する。一方、アナログ回路(5a)上
にも、必要なゲート電極配線、あるいは絶縁膜等を積層
し、アナログ回路(5b〉を形威し、ディジタル回路(
4a)、 (4b)とアナログ回路(5a)、 (5b
)との電気的接続は金属配線(6)で行っていた。A conventional semiconductor integrated circuit in which analog circuits and digital circuits coexist is constructed as described above, and has a semiconductor substrate (3
) A digital circuit (4a) and an analog circuit (5a) are formed inside, and a gate electrode, wiring, an insulating film, etc. are laminated on the digital circuit (4a) to form a digital circuit (4b). On the other hand, the necessary gate electrode wiring or insulating film, etc. are laminated on the analog circuit (5a) to form the analog circuit (5b), and the digital circuit (5b) is formed.
4a), (4b) and analog circuits (5a), (5b)
) was made using metal wiring (6).
従来のアナログ回路並びにディジタル回路が混在する半
導体集積回路は以上のように構成されており、アナログ
回路とディジタル回路を同一半導体基板上に形成してい
るので、ディジタル回路からのノイズがアナログ回路に
悪影響を及ぼし、正常な動作ができなくなるため、アナ
ログ回路の囲りにガードリングをとるなどしてノイズ対
策を施しているが、ディジタル回路からの悪影響を完全
に防ぐことは困難である等の問題点があった。Conventional semiconductor integrated circuits that include both analog and digital circuits are configured as described above, and because the analog and digital circuits are formed on the same semiconductor substrate, noise from the digital circuits has a negative impact on the analog circuits. However, there are problems such as the difficulty of completely preventing the negative effects from digital circuits. was there.
この発明は上記のような問題点を解消するためになされ
たもので、ノイズ発生源となるディジタル回路からアナ
ログ回路を分離独立させることを目的とする。The present invention has been made to solve the above-mentioned problems, and its purpose is to make an analog circuit separate and independent from a digital circuit which is a source of noise generation.
〔課題を解決するための手段〕
この発明に係るアナログ回路並びにディジタル回路が混
在する半導体集積回路はノイズ発生源となるディジタル
回路からアナログ回路を絶縁膜さらに半導体基板により
分離させ、3次元の位置に形成してディジタル回路から
独立させる。[Means for Solving the Problems] A semiconductor integrated circuit in which analog circuits and digital circuits are mixed according to the present invention separates the analog circuit from the digital circuit, which is a source of noise, by an insulating film and a semiconductor substrate, and separates the analog circuit from the digital circuit, which is a source of noise, by using an insulating film and a semiconductor substrate, and separates the analog circuit from the digital circuit, which is a source of noise. form and be independent from digital circuits.
〔作 用)
この発明におけるアナログ回路の形成は電源供給あるい
は接地された半導体基板により、ディジタル回路と分離
し3次元の位置に作り込むようにしたものである。[Function] The analog circuit in this invention is formed in a three-dimensional position separated from the digital circuit by a semiconductor substrate supplied with power or grounded.
以下、この発明の一実施例を図により説明する。 Hereinafter, one embodiment of the present invention will be described with reference to the drawings.
第1図はアナログ回路並びにディジタル回路が混在する
半導体集積回路を示す断面図である。FIG. 1 is a cross-sectional view showing a semiconductor integrated circuit in which analog circuits and digital circuits coexist.
図において、(31,(4a)、 (4b)、 (5a
)、 (5b)、 (6)(7)は第2図の従来例に示
したものと同等であるので説明を省略する。(1)はデ
ィジタル回路(4a)(4b)とアナログ回路(5a)
、 (5b)を分離する分離用絶縁膜、(2)はアナロ
グ回路(5a)、 (5b)を3次元の位置に形成する
ための電源供給又は接地されたアナログ回路用半導体基
板である。In the figure, (31, (4a), (4b), (5a
), (5b), (6) and (7) are the same as those shown in the conventional example of FIG. 2, so their explanations will be omitted. (1) is a digital circuit (4a) (4b) and an analog circuit (5a)
, (5b), and (2) is a semiconductor substrate for analog circuits that is supplied with power or grounded for forming analog circuits (5a) and (5b) in three-dimensional positions.
次に作用について説明する。Next, the effect will be explained.
上記のように構成されたアナログ回路並びにディジタル
回路が混在する半導体集積回路においては半導体基板(
3)内部に形成するディジタル回路(4a)上にゲート
電極、配線あるいは絶縁膜等を積層しディジタル回路(
4b)を形成する。さらに、アナログ・ディジタルの分
離用絶縁膜(1)を積層させ、エツチング後アナログ回
路用半導体基板(2)を形成し、その内部及び上部にア
ナログ回路(5a)、 (5b)を作り込む構造をとっ
ている。In a semiconductor integrated circuit in which analog circuits and digital circuits configured as described above coexist, a semiconductor substrate (
3) Layer gate electrodes, wiring, insulating films, etc. on the digital circuit (4a) formed inside to form the digital circuit (4a).
4b). Furthermore, an insulating film for analog/digital isolation (1) is laminated, and after etching, a semiconductor substrate for analog circuits (2) is formed, and analog circuits (5a) and (5b) are built inside and on the substrate. I'm taking it.
なお、上記実施例ではアナログ回路と3次元の位置に形
成する例を示したが、ディジタル回路を3次元の位置に
形成しても良く同様の効果を奏する。In the above embodiment, an example was shown in which the digital circuit is formed in a three-dimensional position with the analog circuit, but the digital circuit may be formed in a three-dimensional position and the same effect can be obtained.
さらに、ディジタル回路のみで構成する半導体集積回路
ではチップ全体に影響を与える回路、例えばクロンク発
生回路等、チップ動作のタイミングを作り出す回路を他
の回路とは別の3次元の位置に形成しても良く、他の回
路から悪影響を受けないという効果を奏する。Furthermore, in semiconductor integrated circuits consisting only of digital circuits, circuits that affect the entire chip, such as clock generator circuits and other circuits that create the timing of chip operation, may be formed in a three-dimensional position separate from other circuits. This has the advantage of not being adversely affected by other circuits.
以上のようにこの発明によれば、ノイズ発生源となるデ
ィジタル回路から電源供給あるいは接地された半導体基
板によりアナログ回路を分離独立させたので、ディジタ
ル回路からのノイズからアナログ回路を保護できるとと
もにアナログ回路を3次元の位置に形成したので、チッ
プ面積が縮小され、大規模半導体集積回路が実現できる
。As described above, according to the present invention, the analog circuit is separated and independent from the digital circuit, which is a source of noise, by a semiconductor substrate that is powered or grounded, so the analog circuit can be protected from noise from the digital circuit, and the analog circuit Since they are formed in three-dimensional positions, the chip area can be reduced and a large-scale semiconductor integrated circuit can be realized.
第1図は、この発明の一実施例によるアナログ回路並び
にディジタル回路が混在する半導体集積回路を示す断面
図、第2図は従来のアナログ回路並びにディジタル回路
が混在する半導体集積回路を示す断面図である。
図において、(1)は分離用絶縁膜、(2)はアナログ
回路用半導体基板、(3)は半導体基板、(4a)、
(4b)はディジタル回路、(5a)、 (5b)はア
ナログ回路、(6)は金属配線である。
なお、図中、同一符号は同一、又は相当部分を示す。FIG. 1 is a sectional view showing a semiconductor integrated circuit in which analog circuits and digital circuits are mixed according to an embodiment of the present invention, and FIG. 2 is a sectional view showing a conventional semiconductor integrated circuit in which analog circuits and digital circuits are mixed. be. In the figure, (1) is an isolation insulating film, (2) is a semiconductor substrate for analog circuits, (3) is a semiconductor substrate, (4a),
(4b) is a digital circuit, (5a) and (5b) are analog circuits, and (6) is metal wiring. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
積回路において、ディジタル回路からアナログ回路を分
離独立させるために、アナログ回路をディジタル回路と
は別の3次元の位置に作り込む構造を少なくとも備えた
ことを特徴とする半導体集積回路。In a semiconductor integrated circuit in which analog circuits and digital circuits coexist, the semiconductor integrated circuit is characterized by having at least a structure in which the analog circuit is built in a three-dimensional position separate from the digital circuit in order to separate the analog circuit from the digital circuit. semiconductor integrated circuits.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21361189A JPH0377358A (en) | 1989-08-19 | 1989-08-19 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21361189A JPH0377358A (en) | 1989-08-19 | 1989-08-19 | Semiconductor integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0377358A true JPH0377358A (en) | 1991-04-02 |
Family
ID=16642048
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP21361189A Pending JPH0377358A (en) | 1989-08-19 | 1989-08-19 | Semiconductor integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0377358A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5856701A (en) * | 1993-12-29 | 1999-01-05 | Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno | Dielectrically isolated power semiconductor devices |
-
1989
- 1989-08-19 JP JP21361189A patent/JPH0377358A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5856701A (en) * | 1993-12-29 | 1999-01-05 | Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno | Dielectrically isolated power semiconductor devices |
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