JPH04162652A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH04162652A JPH04162652A JP28974290A JP28974290A JPH04162652A JP H04162652 A JPH04162652 A JP H04162652A JP 28974290 A JP28974290 A JP 28974290A JP 28974290 A JP28974290 A JP 28974290A JP H04162652 A JPH04162652 A JP H04162652A
- Authority
- JP
- Japan
- Prior art keywords
- conductive layer
- contact hole
- side direction
- length
- part conductive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特に下部導電層と上部導電
層とを電気的に接続するために設けられるコンタクトホ
ールの形状に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to the shape of a contact hole provided for electrically connecting a lower conductive layer and an upper conductive layer.
従来の半導体装置においては、第4図(a)。 In the conventional semiconductor device, FIG. 4(a).
(b)に示すように、コンタクトホールの長辺方向の長
さaと、短辺方向の長さbとの比a / bについて格
別の考慮がなされていないので、この値が大きいコンタ
クトホールが存在していた。ところが、このような形状
のコンタクト領域の上部導電層4bに第4図(b)に示
すように、カバー絶縁膜の形成工程などで力Fが加わる
と、上部導電層4bに第5図に示すように変形し、程度
のひどい場合には完全に上部導電層ははがれてしまう。As shown in (b), since no special consideration has been given to the ratio a/b between the length a in the long side direction of the contact hole and the length b in the short side direction, the contact hole with a large value is It existed. However, when a force F is applied to the upper conductive layer 4b of the contact region having such a shape as shown in FIG. In severe cases, the upper conductive layer may be completely peeled off.
上述した従来の半導体装置では、コンタクトホールの長
辺方向の長さaと、短辺方向の長さbとの比a / b
が大きいコンタクトホールが存在しているなめ、上部導
電層に、コンタクトホールの長辺方向と垂直な方向の力
が横から加わると、上部導電層の変形がおこり、程度が
ひどい場合には上部導電層のはがれが発生るという問題
点があった。In the conventional semiconductor device described above, the ratio of the length a in the long side direction of the contact hole to the length b in the short side direction is a / b
If a force in the direction perpendicular to the long side of the contact hole is applied from the side to the upper conductive layer where there is a large contact hole, the upper conductive layer will be deformed, and in severe cases, the upper conductive layer will be deformed. There was a problem in that the layers peeled off.
本発明の半導体装置は、コンタクトホールの長辺方向の
長さaと短辺方向の長さbとの比a / bが3より大
きいコンタクトホールを有しないというものである。ま
た、上部導電層と下部導電層との接触面積を大きくする
場合にはコンタクトホールを分割してa / b <
3であるコンタクトを複数個同一のコンタクト領域に設
けるというものである。The semiconductor device of the present invention does not have a contact hole in which the ratio a/b of the length a in the long side direction and the length b in the short side direction of the contact hole is greater than 3. In addition, when increasing the contact area between the upper conductive layer and the lower conductive layer, the contact hole is divided so that a/b <
In this method, a plurality of contacts of 3 are provided in the same contact area.
次に本発明の実施例について図面を参照して説明する。 Next, embodiments of the present invention will be described with reference to the drawings.
第1図(a>は本発明の第1の実施例を示す平面図、第
1図(b)は第1図(a)のA−A線断面図である。FIG. 1(a) is a plan view showing a first embodiment of the present invention, and FIG. 1(b) is a sectional view taken along the line A--A in FIG. 1(a).
コンタクト領域の上部導電層4bと下部導電層3bとは
、3つの正方形状のコンタクトホール1部で接続されて
いる。The upper conductive layer 4b and the lower conductive layer 3b in the contact region are connected through a portion of three square contact holes.
第2図は上部導電層の剥離確$Pとコンタクトホールの
形状(a/b)の相関を示す図である。FIG. 2 is a diagram showing the correlation between the peeling probability $P of the upper conductive layer and the shape (a/b) of the contact hole.
但し、上部導電層は厚さ1μmのA1膜とし、カバー絶
縁膜として厚さ1.1μmの酸窒化シリコン膜を設けた
ものについての特性図である。0くa / b < 3
のとき、剥離確率Pはほぼ0になる。However, this is a characteristic diagram in which the upper conductive layer is an A1 film with a thickness of 1 μm, and a silicon oxynitride film with a thickness of 1.1 μm is provided as a cover insulating film. 0kua/b<3
At this time, the peeling probability P becomes almost 0.
第3図(a)は本発明の第2の実施例を示す平面図、第
3図(b)は第3図(a)のB−B線断面図である。FIG. 3(a) is a plan view showing a second embodiment of the present invention, and FIG. 3(b) is a sectional view taken along the line B--B in FIG. 3(a).
第1の実施例との違いは、コンタクトホールの形状が楕
円形であることである。コンタクトホールの形状が正方
形もしくは長方形でなく、円形もしくは楕円形にすると
、上部導電層のはがれる確率は一層低くなる。The difference from the first embodiment is that the contact hole has an elliptical shape. If the shape of the contact hole is circular or oval rather than square or rectangular, the probability that the upper conductive layer will peel off is further reduced.
以上説明したように本発明の半導体装置は、コンタクト
ホールの長辺方向の長さaと短辺方向の長さbとの比a
/ bが3より大きいコンタクトホールを設けないこ
とにより、上部導電層にコンタクトホールを設けないこ
とにより、上部導電層にコンタクトホールの長辺方向と
垂直な方向の力が横から加わっても上部導電層のはがれ
が起こりにくくなり、半導体装置の歩留りが向上すると
いう効果を有する。As explained above, in the semiconductor device of the present invention, the ratio a of the length a in the long side direction of the contact hole to the length b in the short side direction is
By not providing a contact hole with / b greater than 3, by not providing a contact hole in the upper conductive layer, the upper conductive layer can be maintained even if a force in a direction perpendicular to the long side of the contact hole is applied from the side to the upper conductive layer. This has the effect that layer peeling is less likely to occur and the yield of semiconductor devices is improved.
第1図(a)は本発明の第1の実施例を示す平面図、第
1図(b)は第1図(a)のA−A線断面図、第2図は
上部導電層の剥離確率Pとコンタクトホールの形状a
/ bの相関関係を示す図、第3図(a)は第2の実施
例を示す平面図、第3図(b)は第3図(’a >のB
−B線断面図、第4図(a)は従来例を示す平面図、第
4図(b)は第4図(a)のC−C線断面図、第5図は
上部導電層の剥離状態を示す断面図である。
1・・・コンタクトホール、2・・・層間絶縁膜、3a
・・・下部導電層(配線領域)、3b・・・下部導電層
、4a・・・上部導電層(配線領域)、4b・・・上部
導電層(コンタクト領域)、5・一基板。FIG. 1(a) is a plan view showing the first embodiment of the present invention, FIG. 1(b) is a sectional view taken along line A-A in FIG. 1(a), and FIG. 2 is a peeling of the upper conductive layer. Probability P and contact hole shape a
Figure 3 (a) is a plan view showing the second embodiment, Figure 3 (b) is a diagram showing the correlation between
-B sectional view, FIG. 4(a) is a plan view showing the conventional example, FIG. 4(b) is a C-C sectional view of FIG. 4(a), and FIG. 5 is peeling of the upper conductive layer. It is a sectional view showing a state. 1... Contact hole, 2... Interlayer insulating film, 3a
... lower conductive layer (wiring region), 3b ... lower conductive layer, 4a ... upper conductive layer (wiring region), 4b ... upper conductive layer (contact region), 5. one substrate.
Claims (1)
接続するために設けられるコンタクトホールにおいて、
前記コンタクトホールの長辺方向の長さaと短辺方向の
長さbとの比a/bがすべてのコンタクトホールにおい
て0<a/b<3であることを特徴とする半導体装置。 2、0<a/b<3であるコンタクトホールが、同一の
コンタクト領域に複数個設けられている請求項1記載の
半導体装置。[Claims] 1. In a contact hole provided for electrically connecting an upper conductive layer and a lower conductive layer of a semiconductor device,
A semiconductor device characterized in that a ratio a/b of the length a in the long side direction and the length b in the short side direction of the contact hole satisfies 0<a/b<3 for all the contact holes. 2. The semiconductor device according to claim 1, wherein a plurality of contact holes where 2,0<a/b<3 are provided in the same contact region.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP28974290A JPH04162652A (en) | 1990-10-25 | 1990-10-25 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP28974290A JPH04162652A (en) | 1990-10-25 | 1990-10-25 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04162652A true JPH04162652A (en) | 1992-06-08 |
Family
ID=17747175
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP28974290A Pending JPH04162652A (en) | 1990-10-25 | 1990-10-25 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04162652A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002169179A (en) * | 2000-12-01 | 2002-06-14 | Hitachi Ltd | Liquid crystal display |
WO2010134267A1 (en) * | 2009-05-19 | 2010-11-25 | パナソニック株式会社 | Semiconductor device |
-
1990
- 1990-10-25 JP JP28974290A patent/JPH04162652A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002169179A (en) * | 2000-12-01 | 2002-06-14 | Hitachi Ltd | Liquid crystal display |
WO2010134267A1 (en) * | 2009-05-19 | 2010-11-25 | パナソニック株式会社 | Semiconductor device |
JPWO2010134267A1 (en) * | 2009-05-19 | 2012-11-08 | パナソニック株式会社 | Semiconductor device |
US8405224B2 (en) | 2009-05-19 | 2013-03-26 | Panasonic Corporation | Semiconductor device comprising multilayer interconnect structure with overlapping vias |
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