JPS6354763A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a laminated semiconductor device which can be composed in a simple process for a complementary MOS integrated circuit by independently forming an n-type semiconductor element in a first layer and a p-type semiconductor element in a second layer, and newly providing a layer of metal connections between the first layer and the second layer. CONSTITUTION:A metal connection layer 4 is formed through a first insulating layer 3 on an n-type semiconductor integrated circuit layer 1a, and a p-type semiconductor integrated circuit layer 2a is formed through 4 second insulating layer 5 thereon. Interlayer connections 6 which arrive from the layer 2a at the layer 4 and the layer 2a are provided. For example, the layer 1a is first formed, and the layer 3 is then formed. Then, metal connections of two layers are formed, and the layer 5 is again formed. Then, a single crystal silicon layer is formed on the layer 5, and the layer 2a is formed here. Then, a contact hole which arrives from the layer 2a at the layer 1a is opened, and interlayer connections 6, 6a-6c are formed. At this time, they are contacted with metal connections 4a-4c by the holes as required.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a stacked semiconductor device, and particularly to a complementary MO
The present invention relates to a method of configuring elements in an S-storage circuit and a method of wiring them.

[Conventional technology]

Diagram M2 shows a cross-sectional view of a conventional stacked semiconductor device. In the figure, Il+ is the first complementary MOSO8
This is called the first layer below the target circuit layer. ), and the eighth complementary MOS integrated circuit layer 12)C and the second
It is called a layer. ) is provided. 1111 is the wiring layer provided in the first layer, and the penalty is the wiring layer provided in the second layer, V1
21 is the active region of the n-type semiconductor element in the first layer; 21 is the active region of the n-type semiconductor element in the second layer; (131 is the first
The active region of the n-type semiconductor element in the second layer is the active region of the n-type semiconductor element in the second layer.
Insulating film of the layer, the report shows the entire insulating film of the second layer.

In this case, the 1M1 layer and the second layer are connected by interlayer arrangement (6).

[Problem that the invention seeks to solve]

Conventional stacked semiconductor devices simply connect different layers via through holes or contact holes to increase the degree of stacking, and they only use p-type semiconductors and n-type semiconductors, which are common in complementary λFOE integrated circuits. The connections and wiring between drain electrodes and between gate and co-poles, as well as their connections and wiring, had not been realized efficiently.

In view of the above-mentioned problems, the present invention aims to provide a stacked semiconductor device which can be constructed with a complementary MOS integrated circuit through a simple process.

[Means to resolve the issue]

In the stacked semiconductor device according to the VC of the present invention, an n-type semiconductor element and a second Vcp-type semiconductor element are separately formed in the first layer, and a metal wiring layer is newly added between the first layer and the second layer. It has been established.

[Effect]

In the stacked semiconductor device according to the present invention, the metal wiring is provided in a new layer l/i: without a step difference due to an active region, etc., so that the metal wiring itself can be made thinner, and the degree of integration can be increased. First, by connecting the interlayer wiring connecting the first layer and the second layer to the metal wiring, intra-circuit wiring with a short connection distance can be achieved.

〔Example〕

Hereinafter, one embodiment of this invention will be explained with reference to the drawings. FIG. 1 shows a cross-sectional view of a stacked semiconductor device VC, which is an embodiment of the present invention.

In the figure, (4a) to (4c) are metal wirings.

In this example, first, a normal MOS device process is performed to form an nl MOS integrated layer (la)'z shadow, an insulating layer +
31'i: The relief is formed using silicon oxide or the like. Next, two layers of metal wiring using the normal process? Then, a VCL and an insulating layer 151k are formed facing forward. Next, in order to form a p-type MOS integrated layer (2a), a VC first crystal silicon layer is formed on the insulating layer 16), and a p-type MO61 layered layer (2a) is formed thereon using a normal MOS device process. Form.

Next, a contact hole is made from the layer (2a) to the layer (la) by reactive ion etching, etc., and the contact hole f is filled with aluminum, high melting point metal silicide, etc. by full sputtering method or CVD method, etc.
6) (Ha) (tlb) (6c) f complete. At this time, contact is made with the metal wirings (4a), (4b), and (4c) through the contact holes as necessary.

In this way, the gate electrode 1JFA of the first layer n-type semiconductor element
and the gate electrode of the second layer p-cell semiconductor device according to JP-A Wiring (6).
), the drain electrode (12a) of the first layer n-type semiconductor element and the drain electrode (H
By connecting a) with an interlayer wiring (6a), a simple Vc complementary MOS inverter ta can be formed. Similarly, the gate electrode (15b) and (25b)' are connected by the i-layer interlayer 31 (6b), and the drain electrode (12c) and (21110)'
A complementary MOEI inverter can be configured by connecting with one interlayer wiring (6C). And the wiring between j (6a)
If you connect (6C) with the metal wiring (4a) of the desired layer, two elements will be formed with a short pebble? You can now connect.

In this case, it is assumed that the source electrode of the first n-type semiconductor element is grounded, and the source electrode of the 21st dp-type semiconductor element is supplied with a power supply voltage.

In the above embodiment, the complementary MOS inverter was described, but the complementary MOS inverter is the complementary MOS inverter.
In the OR gate and the composite gate, young fruits are produced similarly or even more so.

In the above example, the metal wiring itself had two layers, but it does not matter how many layers there are.

If necessary, metal wiring may be added on the surface of the first layer n-type semiconductor integrated circuit layer. Although a semiconductor element is formed, the reverse may be used.

[Results of invention]

As described above, according to the present invention, to form a complementary MOS integrated circuit ft trench, the process steps that conventionally required two types of semiconductor elements (p-type and n-type) in each layer have been replaced with one type of semiconductor element in each layer. Since the metal wiring in each layer can be newly formed in six layers, complementary type 1K can be realized with significantly simpler process steps than conventional stacked semiconductor devices.
OS (JG product circuit? Can be created.

In addition, since the metal wiring is formed in a crystalline layer with no steps due to active regions, etc., metal wiring? It can be made thinner and the degree of integration can be increased.

Furthermore, since the p-type semiconductor element and the n-type semiconductor element are separated by an insulating layer and a metal wiring layer, a latch-up phenomenon peculiar to complementary MOS integrated circuits occurs. No more waking up.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing a stacked semiconductor device according to an embodiment of the present invention, and FIG. 2 is a sectional view showing a conventional λ stone type semiconductor device. In the figure, 111 is a first semiconductor integrated circuit layer, (21
is the second semiconductor integrated circuit layer, +31 and +41 are insulating layers, +51 is a metal wiring layer, (6) is a - wiring, ll2) is an active region of an n-type semiconductor, and 0 and y are a p-type semiconductor element In the active region, (Jo·2θ is a gate electrode, and l141 is an M-type well. In the figure, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] an n-type semiconductor integrated circuit layer consisting of an n-type semiconductor element, an insulating film, wiring, etc.; a metal wiring layer provided on the n-type semiconductor integrated circuit layer via a first insulating layer; and a metal wiring layer provided on the metal wiring layer. a p-type semiconductor element provided through a second insulating layer,
a p-type semiconductor integrated circuit layer consisting of an insulating film, wiring, etc.; from the p-type semiconductor integrated circuit layer to the metal wiring layer;
Complementary type M with interlayer wiring reaching the type semiconductor integrated circuit layer
A semiconductor device characterized by forming an OS integrated circuit