JPH0357636B2 - - Google Patents
Info
- Publication number
- JPH0357636B2 JPH0357636B2 JP30678986A JP30678986A JPH0357636B2 JP H0357636 B2 JPH0357636 B2 JP H0357636B2 JP 30678986 A JP30678986 A JP 30678986A JP 30678986 A JP30678986 A JP 30678986A JP H0357636 B2 JPH0357636 B2 JP H0357636B2
- Authority
- JP
- Japan
- Prior art keywords
- ceramic
- plating
- glass
- circuit board
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000919 ceramic Substances 0.000 claims description 61
- 238000000034 method Methods 0.000 claims description 53
- 239000011521 glass Substances 0.000 claims description 37
- 238000007747 plating Methods 0.000 claims description 35
- 239000000758 substrate Substances 0.000 claims description 31
- 230000004913 activation Effects 0.000 claims description 14
- 238000004519 manufacturing process Methods 0.000 claims description 13
- 229910052751 metal Inorganic materials 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 12
- 239000000654 additive Substances 0.000 claims description 7
- 230000000996 additive effect Effects 0.000 claims description 7
- 238000007772 electroless plating Methods 0.000 claims description 7
- 238000010304 firing Methods 0.000 claims description 6
- 238000009713 electroplating Methods 0.000 claims description 5
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 20
- 230000008569 process Effects 0.000 description 17
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 8
- 239000004020 conductor Substances 0.000 description 8
- 229910052802 copper Inorganic materials 0.000 description 8
- 239000010949 copper Substances 0.000 description 8
- 238000007789 sealing Methods 0.000 description 7
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 6
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 6
- 238000007796 conventional method Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- 239000005394 sealing glass Substances 0.000 description 5
- QAOWNCQODCNURD-UHFFFAOYSA-N sulfuric acid Substances OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 5
- 230000003746 surface roughness Effects 0.000 description 5
- 239000003054 catalyst Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 3
- 230000001133 acceleration Effects 0.000 description 3
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 3
- 239000012299 nitrogen atmosphere Substances 0.000 description 3
- 238000010899 nucleation Methods 0.000 description 3
- 230000006911 nucleation Effects 0.000 description 3
- 239000011368 organic material Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 2
- GNTDGMZSJNCJKK-UHFFFAOYSA-N divanadium pentaoxide Chemical compound O=[V](=O)O[V](=O)=O GNTDGMZSJNCJKK-UHFFFAOYSA-N 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000007788 roughening Methods 0.000 description 2
- 230000001235 sensitizing effect Effects 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 1
- 206010070834 Sensitisation Diseases 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 150000001339 alkali metal compounds Chemical class 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910021538 borax Inorganic materials 0.000 description 1
- 229910052878 cordierite Inorganic materials 0.000 description 1
- JSKIRARMQDRGJZ-UHFFFAOYSA-N dimagnesium dioxido-bis[(1-oxido-3-oxo-2,4,6,8,9-pentaoxa-1,3-disila-5,7-dialuminabicyclo[3.3.1]nonan-7-yl)oxy]silane Chemical compound [Mg++].[Mg++].[O-][Si]([O-])(O[Al]1O[Al]2O[Si](=O)O[Si]([O-])(O1)O2)O[Al]1O[Al]2O[Si](=O)O[Si]([O-])(O1)O2 JSKIRARMQDRGJZ-UHFFFAOYSA-N 0.000 description 1
- KZHJGOXRZJKJNY-UHFFFAOYSA-N dioxosilane;oxo(oxoalumanyloxy)alumane Chemical compound O=[Si]=O.O=[Si]=O.O=[Al]O[Al]=O.O=[Al]O[Al]=O.O=[Al]O[Al]=O KZHJGOXRZJKJNY-UHFFFAOYSA-N 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052839 forsterite Inorganic materials 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- HCWCAKKEBCNQJP-UHFFFAOYSA-N magnesium orthosilicate Chemical compound [Mg+2].[Mg+2].[O-][Si]([O-])([O-])[O-] HCWCAKKEBCNQJP-UHFFFAOYSA-N 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 229910052863 mullite Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000000053 physical method Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000005488 sandblasting Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 239000000565 sealant Substances 0.000 description 1
- 230000008313 sensitization Effects 0.000 description 1
- 239000004328 sodium tetraborate Substances 0.000 description 1
- 235000010339 sodium tetraborate Nutrition 0.000 description 1
- -1 steatite Chemical compound 0.000 description 1
- 210000002784 stomach Anatomy 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
- H05K3/181—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating
- H05K3/182—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating characterised by the patterning method
- H05K3/184—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating characterised by the patterning method using masks
Landscapes
- Manufacturing Of Printed Wiring (AREA)
Description
【発明の詳細な説明】
［技術分野］
この発明は、電子基材として使用されるセラミ
ツクス配線回路板に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a ceramic printed circuit board used as an electronic substrate.
［背景技術］
セラミツクス配線回路板を作製するにあたり、
最近、スルーホール部のメタライジングの信頼性
が高く、金属部の厚みの制御が容易であるという
利点から、めつきによる回路形成法が注目されて
いる。中でも、低コスト化の要望に対しては、フ
ルアデイテイブ法が有効であるとして注目されて
いる。従来、この方式でセラミツクス配線回路板
を作成するには、たとえば第５図に示すような工
程で実施されていた。[Background technology] In producing a ceramic printed circuit board,
Recently, a method of forming a circuit by plating has been attracting attention because of the advantages that metallizing of through-hole parts is highly reliable and the thickness of the metal part can be easily controlled. Among these, the fully additive method is attracting attention as being effective in meeting the demand for cost reduction. Conventionally, in order to produce a ceramic wiring circuit board using this method, the process was carried out, for example, as shown in FIG.
すなわち、先ずセラミツクスと、後に処理する
めつきとの密着性を強固なものとするために、そ
の表面を化学的に粗面化したセラミツクス基板を
用意する。つぎにその表面に、金属を受容するよ
うにパラジウム（Pd）などの核付け処理を施し
た後、めつきレジストとして感光性の有機材料を
使用して、露光現象により所定のパターニングを
行う。 That is, first, a ceramic substrate whose surface is chemically roughened is prepared in order to strengthen the adhesion between the ceramic and the plating that will be treated later. Next, the surface is nucleated with palladium (Pd) or the like to accept metal, and then a photosensitive organic material is used as a plating resist to form a predetermined pattern by exposure.
つぎに、めつきレジスト形成部以外のPd等の
核付け処理を施されたセラミツクス部に無電極め
つきを施し、必要ならば、さらに電解めつきを施
し回路形成した後、めつきレジストを除去して所
定の回路板を得るのである。 Next, electrodeless plating is applied to the ceramic parts that have been subjected to nucleation treatment with Pd, etc., other than the plating resist forming area, and if necessary, further electrolytic plating is applied to form a circuit, and then the plating resist is removed. A predetermined circuit board is obtained.
このように従来法では、パターニングから、回
路保護工程に至るまでの工程数が多く、低コスト
化のために工程数の削減が望まれていた。 As described above, the conventional method requires a large number of steps from patterning to a circuit protection step, and it has been desired to reduce the number of steps in order to reduce costs.
［発明の目的］
この発明は、以上のような現状に鑑みてなされ
たものであり、セラミツクス配線回路板をめつき
によるアデイテイブ法で製造するに当たり、パタ
ーニングから回路保護工程に至るまでの工程数を
削減し、低コストで製造できるセラミツクス配線
回路板の製造方法を提供することを目的としてい
る。[Purpose of the Invention] This invention has been made in view of the above-mentioned current situation, and is intended to reduce the number of steps from patterning to circuit protection when manufacturing ceramic printed circuit boards using an additive method using plating. The purpose of the present invention is to provide a method for manufacturing a ceramic printed circuit board that can be manufactured at low cost.
［発明の開示］
この発明は、回路部をめつきによるアデイテイ
ブ法によつて形成するセラミツクス配線回路板の
製法において、粗面化されたセラミツクス基板を
用意し、つぎにセラミツクス基板面に金属が受容
されるように活性化処理を施した後、回路部とな
る部分以外の部分にめつきレジストとしてガラス
ペーストを付けて焼成するか、または用意された
セラミツクス基板の回路部となる部分以外の部分
に、先ずめつきレジストとしてガラスペーストを
付けて焼成した後、金属が受容されるように活性
化処理を施し、しかる後無電解めつきによつて回
路部を形成し、必要ならば、さらに電解めつきを
施すことを特徴とするセラミツクス配線回路板の
製法を提供するものである。[Disclosure of the Invention] The present invention provides a method for manufacturing a ceramic wiring circuit board in which a circuit portion is formed by an additive method using plating, in which a roughened ceramic substrate is prepared, and then a metal is received on the surface of the ceramic substrate. After activating the ceramic substrate, apply glass paste as a plating resist to the parts other than the part that will become the circuit part and bake it, or apply it to the part of the prepared ceramic substrate other than the part that will become the circuit part. First, a glass paste is applied as a plating resist and fired, followed by an activation treatment to accept the metal.Then, a circuit part is formed by electroless plating, and if necessary, further electrolytic plating is applied. The present invention provides a method for manufacturing a ceramic printed circuit board characterized by applying a hardening.
なお、本発明を実施するに先立つて、焼結セラ
ミツクス基板の準備が必要であるが、焼結基板の
材質としては、アルミナ、フオルステライト、ス
テアタイト、ジルコニア、ムライト、コージエラ
イト、チタニア等の酸化物系セラミツクスが主と
して使用されるが、炭化物系および、窒化物系セ
ラミツクス基板もあり、これらの何れも対象とな
し得る。 Before carrying out the present invention, it is necessary to prepare a sintered ceramic substrate, and examples of the material for the sintered substrate include oxides such as alumina, forsterite, steatite, zirconia, mullite, cordierite, and titania. Although ceramics are mainly used, there are also carbide and nitride ceramic substrates, and any of these can be used.
第１図ａ，ｂは、本発明にかかるセラミツクス
配線回路板の製造工程の、それぞれ異なる実施例
を示すブロツク図である。以下、第１図ａ，ｂに
それぞれ示したブロツク図に従つて詳しく説明す
る。 FIGS. 1a and 1b are block diagrams showing different embodiments of the manufacturing process of a ceramic wiring circuit board according to the present invention. A detailed explanation will be given below with reference to the block diagrams shown in FIGS. 1a and 1b, respectively.
本発明において使用するセラミツクス基板は、
後に施すめつき層との密着性を強固なものとする
ために、予じめ、その表面を粗面化する必要があ
る。粗面化法としては、サンドブラスト法のよう
に物理的に行う方法、あるいは、アルカリ金属化
合物、フツ化水素（HF）、五酸化バナジウム
（V2O5）、ホウ砂、リン酸などの溶液、融液を用
いて化学的に行うものとがあるが、スルーホール
部や、大面積の基板に亙つて均一に粗面化が行え
る化学的手法を用いる方が好ましい。 The ceramic substrate used in the present invention is
In order to ensure strong adhesion with the plating layer that will be applied later, it is necessary to roughen the surface in advance. Surface roughening methods include physical methods such as sandblasting, or solutions of alkali metal compounds, hydrogen fluoride (HF), vanadium pentoxide (V 2 O 5 ), borax, phosphoric acid, etc. Although there is a method of chemically roughening using a melt, it is preferable to use a chemical method that can uniformly roughen the through-hole portion or a large area of the substrate.
＜第１図ａによる方法＞
前述のいずれかの方法で粗面化されたセラミツ
クス基板に先ず、金属を受容するように活性化処
理を施す。この活性化処理は、無電解めつきの活
性核となり得る金属を付ける処理である。活性核
となり得る金属としては、そのような機能を有す
るものであれば使用可能であり、限定するもので
はない。活性化処理の方法としては、従来より用
いられているセンシタイジング＝アクチベーシヨ
ン法またはキヤタライジング＝アクセレーシヨン
法により、活性核としてたとえば、Pdを基板表
面に付与する。<Method according to FIG. 1a> First, a ceramic substrate whose surface has been roughened by any of the methods described above is subjected to an activation treatment so as to receive metal. This activation treatment is a treatment for attaching a metal that can serve as an active nucleus for electroless plating. Any metal that can serve as an active nucleus can be used as long as it has such a function, and is not limited to any particular metal. As a method for the activation treatment, for example, Pd is applied as an active nucleus to the substrate surface by a conventionally used sensitizing=activation method or catalystizing=acceleration method.
つぎに、ガラスペーストを回路導体部となる部
分以外の部分にスクリーン印刷し、焼成する。こ
のガラスがめつきレジストとして作用する。 Next, glass paste is screen printed on the parts other than the parts that will become the circuit conductor parts, and fired. This glass acts as a plating resist.
従来法では、前述の如く有機材料をめつきレジ
ストとして使用するため、高信頼性を要求される
場合は、セラミツクス配線回路板に対して、熱に
弱い有機材料をそのまま基板上に残存させておく
ことができず、したがつてアデイテイブ法で回路
導体部を形成後、有機系めつきレジストを剥離除
去しなければならなかつた。しかし、本発明にか
かる方法では、無機材料であるガラスをレジスト
として用いるため、熱等によつて信頼性が損なわ
れることはないので、レジスト除去の工程が削減
される。また、回路部分をセラミツクスで封着す
るような場合は、さらに効果的である。 In the conventional method, as mentioned above, an organic material is used as a plating resist, so if high reliability is required, the heat-sensitive organic material is left on the ceramic printed circuit board as it is. Therefore, after forming the circuit conductor portion by an additive method, the organic plating resist had to be peeled off. However, in the method according to the present invention, since glass, which is an inorganic material, is used as a resist, the reliability is not impaired by heat or the like, so that the process of removing the resist is reduced. Further, it is even more effective when the circuit portion is sealed with ceramics.
すなわち、セラミツクスで封着する場合、第３
図に示すように、回路形成がなされたセラミツク
ス基板４および、封着用セラミツクス基板５の両
面にガラスペーストを塗布して仮焼成した後、両
基板を重ね合わせて本焼成し、封着を行うが、本
方法では、第４図に示したようにアデイテイブ法
による回路形成時にレジストとして用いるガラス
をそのまま封着剤としても利用できるため、さら
に１工程を削減できる。第４図ａは、封着用セラ
ミツクス５の断面図であり、この図で２は封着用
のガラス層てある。第４図ｂはセラミツクス封着
されたセラミツクス配線回路板の一例を示す断面
図である。 In other words, when sealing with ceramics, the third
As shown in the figure, glass paste is applied to both sides of the ceramic substrate 4 on which circuits are formed and the ceramic substrate 5 for sealing, and after pre-firing, the two substrates are stacked and fired for final baking to seal them. In this method, as shown in FIG. 4, the glass used as a resist during circuit formation by the additive method can also be used as a sealant as is, so that one step can be further reduced. FIG. 4a is a cross-sectional view of the sealing ceramic 5, and in this figure, reference numeral 2 denotes a sealing glass layer. FIG. 4b is a sectional view showing an example of a ceramic wiring circuit board sealed with ceramics.
なお、ここで使用するガラスペーストには特に
指定はないが、エネルギーコストの点から、低温
焼結ガラスを用いるのが好ましい。 Note that although there is no particular specification for the glass paste used here, it is preferable to use low-temperature sintered glass from the point of view of energy cost.
ガラスペーストには、空気中で焼成するもの
と、窒素雰囲気中でも焼成可能なものがあるが、
空気焼成タイプのガラスを用いた場合には、つぎ
の「核の活性化工程」を行う必要がある。すなわ
ち、空気中での焼成は、予じめセラミツクス基板
に核付けされたPdを酸化してしまい、その活性
度を奪つてしまうためである。これに対して窒素
中で焼成する場合は、予じめセラミツクス基板に
核付けされたPdは、何らその活性度を失うこと
はないので活性化工程は不要である。 Some glass pastes can be fired in air, while others can be fired in a nitrogen atmosphere.
When air firing type glass is used, it is necessary to perform the following "nucleus activation step". That is, firing in air oxidizes the Pd that has been nucleated on the ceramic substrate in advance, thereby depriving it of its activity. On the other hand, when firing in nitrogen, the Pd that has been nucleated on the ceramic substrate in advance does not lose any of its activity, so no activation step is necessary.
なお、核の活性化工程では、例えば、５〜50％
濃度の硫酸に１〜30分間浸漬して処理すればよ
い。 In addition, in the nuclear activation step, for example, 5 to 50%
It can be treated by immersing it in concentrated sulfuric acid for 1 to 30 minutes.
つぎに、無電解めつきを行う。無電解めつきで
付ける金属については特に指定はなく、用途に応
じて選ばれるが、低コスト、高導電性という点か
ら、銅を使用するのが好ましい。銅をめつきする
ためには無電解銅めつき浴を用いるのが一般的で
ある。 Next, electroless plating is performed. The metal to be applied by electroless plating is not particularly specified and is selected depending on the application, but it is preferable to use copper because of its low cost and high conductivity. For plating copper, it is common to use an electroless copper plating bath.
なお、めつき皮膜の厚みが要求される場合に
は、さらに電解めつきを行つてめつき厚を増し、
セラミツクス配線回路板を得る。 In addition, if a thicker plating film is required, further electrolytic plating is performed to increase the plating thickness.
A ceramic wiring circuit board is obtained.
＜第１図ｂによる方法＞
前述のいずれかの方法で粗面化されたセラミツ
クス基板に、ガラスペーストを回路導体部となる
部分以外の部分にスクリーン印刷で焼成する。こ
のガラスがめつきレジストとして作用する。<Method according to FIG. 1b> On a ceramic substrate whose surface has been roughened by any of the methods described above, a glass paste is fired by screen printing on the portions other than the portions that will become the circuit conductor portions. This glass acts as a plating resist.
ガラスペーストの種類については特に指定はな
いが、エネルギーコストの点から低温焼成ガラス
を用いることが好ましい。また、焼成後の表面が
平滑となるガラスペーストを用いるとさらに好ま
しい結果が得られる。 Although there is no particular specification regarding the type of glass paste, it is preferable to use low-temperature fired glass from the viewpoint of energy cost. Moreover, more preferable results can be obtained by using a glass paste that has a smooth surface after firing.
つぎに核付け処理を行う。その方法としては、
キヤタライジング＝アクセレーシヨン法を用い
る。 Next, a nucleation process is performed. The method is as follows:
Catalyzing = acceleration method is used.
なお、キヤタリスト中のPdの濃度を適正範囲
に管理することにより、核付けする基板の表面粗
さの程度に応じて選択的な活性化が可能となる。
すなわち、本工程における基板面は、粗面化され
たセラミツクス面と、めつきレジストとして用い
る表面平滑なガラス面を有しており、Pdの濃度
を適正範囲に調整したキヤタリスト中に浸漬した
場合、粗面化されているセラミツクス面にPdが
付与され、表面平滑なガラス面にはほとんどPd
が付着し．い。 Note that by controlling the concentration of Pd in the catalyst within an appropriate range, selective activation can be performed depending on the degree of surface roughness of the substrate to be nucleated.
That is, the substrate surface in this step has a roughened ceramic surface and a smooth glass surface used as a plating resist, and when immersed in a catalyst with a Pd concentration adjusted to an appropriate range, Pd is added to the roughened ceramic surface, and almost all Pd is added to the smooth glass surface.
is attached. stomach.
したがつて、次工程の無電解めつき処理の際に
は、Pdが付与されたセラミツクス面（すなわち、
回路部）のみに、選択的に金属が折出することに
なる。なお、キヤタリストによりPdを付与した
後、アクセレータにより、Pdの活性化を行う。 Therefore, during the next step of electroless plating, the Pd-applied ceramic surface (i.e.,
Metal is selectively precipitated only in the circuit area). Note that after Pd is assigned by the catalyst, Pd is activated by the accelerator.
つぎに無電解めつきを行い、必要ならばさらに
電解めつきを施してセラミツクス配線回路板を得
る。 Next, electroless plating is performed, and if necessary, further electrolytic plating is performed to obtain a ceramic printed circuit board.
以上のようにして得られたセラミツクス配線回
路板の例を断面図で示したのが第２図である。こ
の図で１は粗面化されたセラミツクス基板、２は
ガラス層、３は回路部であり、導体層で形成され
ている。 FIG. 2 shows a cross-sectional view of an example of the ceramic printed circuit board obtained as described above. In this figure, 1 is a ceramic substrate with a roughened surface, 2 is a glass layer, and 3 is a circuit section, which is formed of a conductor layer.
以上に説明したように、たとえば第１図ａ，ｂ
のいずれかの方法をとることにより、従来法に比
べ工程数を削減でき、製造コストが低減できる効
果が得られる。なお、めつきレジストとして、無
機質のガラスを使用するので、信頼性が改善され
る効果もある。 As explained above, for example, Fig. 1 a, b
By adopting either method, the number of steps can be reduced compared to conventional methods, and the effect of reducing manufacturing costs can be obtained. Note that since inorganic glass is used as the plating resist, reliability is also improved.
以下に本発明に係るセラミツクス配線回路板の
製法を、実施例に基づき説明する。 The method for manufacturing a ceramic printed circuit board according to the present invention will be described below based on examples.
実施例 １
第１図ａに示したプロセスに従つて実施し、第
２図に示した構成のセラミツクス配線回路板を得
た。以下、図面に基づいて説明する。Example 1 The process shown in FIG. 1a was followed to obtain a ceramic wiring circuit board having the structure shown in FIG. 2. The following will explain based on the drawings.
まず高温リン酸溶液にて、表面粗さRmaxが３
〜5μｍになるように化学的に粗面化した96％
Al2O3基板１を用意し、センシタイジング＝アク
チベーシヨン法により、Pdの核付け処理を行つ
た。 First, with a high temperature phosphoric acid solution, the surface roughness Rmax is 3.
96% chemically roughened to ~5μm
An Al 2 O 3 substrate 1 was prepared, and Pd was nucleated by a sensitizing/activation method.
つぎに、めつきレジストとして用いるガラスペ
ーストを＃250〜325メツシユのスクリーンで印刷
し、空気中450℃で焼成し、膜厚12μｍのガラス
層２を形成した。そして酸化されたPdを活性化
するために、15％硫酸に約15分間浸漬した後、高
速無電解銅めつき液によつて10μｍの厚みの導体
層３を形成し、セラミツクス配線回路板を得た。 Next, a glass paste used as a plating resist was printed with a #250-325 mesh screen and baked in air at 450°C to form a glass layer 2 with a thickness of 12 μm. Then, in order to activate the oxidized Pd, it was immersed in 15% sulfuric acid for about 15 minutes, and then a conductor layer 3 with a thickness of 10 μm was formed using a high-speed electroless copper plating solution to obtain a ceramic printed circuit board. Ta.
本法により、従来法に比べ１工程を削減するこ
とができた。 With this method, one step could be reduced compared to the conventional method.
実施例 ２ 第２図ａに示したプロセスに従つて実施した。Example 2 It was carried out according to the process shown in Figure 2a.
まず、水酸化ナトリウムの高温融液にて、表面
粗さRmaxが２〜3μｍになるように化学的に粗面
化した96％Al2O3基板１を用意し、センシタイジ
ング＝アクチベーシヨン法により、Pdの核付け
処理を行つた。 First, a 96% Al 2 O 3 substrate 1 was chemically roughened with a high-temperature melt of sodium hydroxide so that the surface roughness Rmax was 2 to 3 μm, and sensitization = activation was performed. Pd nucleation treatment was performed using a method.
つぎに、めつきレジストとして用いるガラスペ
ーストを＃250〜325メツシユのスクリーンで印刷
し、N2雰囲気中500℃で焼成し、膜厚12μｍのガ
ラス層２を形成した。つぎに高速無電解銅めつき
液を使用して銅膜厚10μｍの回路部３を形成し、
セラミツクス配線回路板を得た。 Next, a glass paste used as a plating resist was printed with a #250-325 mesh screen and fired at 500°C in an N 2 atmosphere to form a glass layer 2 with a thickness of 12 μm. Next, a circuit portion 3 with a copper film thickness of 10 μm is formed using a high-speed electroless copper plating solution.
A ceramic wiring circuit board was obtained.
このプロセスでは、ガラスペーストとしてN2
雰囲気中で焼成可能なものを用いたので、Pd核
が、その活性度を保持しており、実施例１のプロ
セスよりさらに「核の活性化工程」を削減するこ
とができた。 This process uses N2 as a glass paste
Since a material that can be fired in an atmosphere was used, the Pd nuclei maintained their activity, and the "nucleus activation step" could be further reduced than in the process of Example 1.
実施例 ３ 第１図ｂに示したプロセスに従つて実施した。Example 3 It was carried out according to the process shown in Figure 1b.
まず、高温リン酸溶液にて、表面粗さRmax
が、３〜5μｍになるように化学的に粗面化した
Al2O3基板１を用意し、めつきレジストとして使
用するガラスペーストを、＃250〜325メツシユの
スクリーンで印刷し、N2雰囲気中500℃で焼成
し、膜厚12μｍのガラス層２を得た。 First, with a high temperature phosphoric acid solution, the surface roughness Rmax
The surface was chemically roughened to a thickness of 3 to 5 μm.
An Al 2 O 3 substrate 1 was prepared, glass paste used as a plating resist was printed on a #250-325 mesh screen, and baked at 500°C in an N 2 atmosphere to obtain a glass layer 2 with a film thickness of 12 μm. Ta.
つぎにキヤタライジング＝アクセレーシヨン法
によりPdの核付けを行つた。このとき、キヤタ
リスト中のPdの濃度を標準の75％程度に希釈し
たものを用いた。アクセレータとして、10％濃度
の硫酸を用い、これに３〜10分間浸漬した。前述
のようにPdは、粗面化されたセラミツクス面に
のみ付与された。 Next, Pd was nucleated using the catalystization/acceleration method. At this time, the concentration of Pd in the catalyst was diluted to about 75% of the standard concentration. As an accelerator, 10% sulfuric acid was used and immersed in this for 3 to 10 minutes. As mentioned above, Pd was applied only to the roughened ceramic surface.
つぎに、高速無電解銅めつきを施し、導体層３
の厚みが10μｍのセラミツクス配線回路板を得
た。 Next, high-speed electroless copper plating is applied to the conductor layer 3.
A ceramic wiring circuit board having a thickness of 10 μm was obtained.
このとき、ガラス面には全く銅は析出しなかつ
た。このプロセスにより、実施例２と同じ工程数
でセラミツクス配線回路板が作成できた。 At this time, no copper was deposited on the glass surface. Through this process, a ceramic printed circuit board could be produced with the same number of steps as in Example 2.
実施例 ４
ガラスペーストとして空気中焼成タイプのもの
を用いた他は、実施例３と同様の方法、すなわち
第１図ｂのプロセスでセラミツクス配線回路板を
得た。第２図ｂのプロセスでは、ガラスペースト
の焼成雰囲気の如何を問わず、従来法に比べて２
工程削減できた。Example 4 A ceramic printed circuit board was obtained by the same method as in Example 3, ie, the process shown in FIG. 1b, except that an air-fired type glass paste was used. The process shown in Figure 2b has a 2.
We were able to reduce the process.
実施例 ５
１〜2mol／の水酸化ナトリウム溶液にて表
面粗さRmaxが、３〜5μｍになるように化学的に
粗面化したAlN基板を用いた他は、実施例３と
同様のプロセスで、第４図ａに示したような、予
じめガラス層２を塗布形成し、仮焼成した封着用
セラミツクス５を用意し、第４図ｂに示した構造
になるように封着を行つた。このプロセスでは、
めつきレジストとして使用したガラスを封着用ガ
ラスとしても利用できるため、従来法では必要で
あつた、有機のめつきレジストを剥離した後、新
たに封着用ガラスをセラミツクス配線回路板に塗
布する工程が削減された。Example 5 The same process as in Example 3 was used except that an AlN substrate was chemically roughened with a 1-2 mol/sodium hydroxide solution so that the surface roughness Rmax was 3-5 μm. As shown in FIG. 4a, a sealing ceramic 5 on which a glass layer 2 had been applied and pre-fired was prepared, and the sealing was performed to obtain the structure shown in FIG. 4b. . In this process,
Since the glass used as a plating resist can also be used as a sealing glass, the process of peeling off the organic plating resist and applying a new sealing glass to the ceramic wiring circuit board, which was necessary in the conventional method, is now possible. reduced.
なお、めつきレジストとして用いるガラスを封
着用ガラスとしても利用する場合は、ガラス層２
の厚みは、導体層３の厚みよりも厚いことが必要
である。 Note that when the glass used as the plating resist is also used as the sealing glass, the glass layer 2
The thickness of the conductor layer 3 needs to be thicker than that of the conductor layer 3.
［発明の効果］
本発明にかかるセラミツクス配線回路板の製法
では、ガラスをめつきレジストとして使用するた
め、有機系のめつきレジストのように剥離する必
要がなく、必要ならば、さらに封着用ガラスとし
ても利用できるので従来法に比べ工程数を削減で
き、低コスト化が実現できる効果がある。[Effects of the Invention] In the method for manufacturing a ceramic wiring circuit board according to the present invention, glass is used as a plating resist, so there is no need to peel it off unlike organic plating resists, and if necessary, a sealing glass is used. Since it can also be used as a method, the number of steps can be reduced compared to conventional methods, which has the effect of lowering costs.
第１図ａ，ｂは本発明にかかるセラミツクス配
線回路板の製造プロセスを示したブロツク図、第
２図は、本発明にかかるプロセスで作成したセラ
ミツクス配線回路板の一例を示す断面図、第３図
は、従来の封止セラミツクス配線回路板の製法の
概要を示す断面図、第４図ａは、本発明にかかる
セラミツクス配線回路板の封着用セラミツクスの
概要を示す断面図、第４図ｂは、本発明にかかる
セラミツクス配線回路板の封着状態を示す断面
図、第５図は、従来のアデイテイブ法によるセラ
ミツクス配線回路板の製造プロセスの一例を示し
たブロツク図である。
１は粗面化セラミツクス基板、２はガラス層、
３は回路部、４はセラミツクス基板、５は封着用
セラミツクス。
1a and 1b are block diagrams showing the manufacturing process of a ceramic wiring circuit board according to the present invention, FIG. 2 is a sectional view showing an example of a ceramic wiring circuit board manufactured by the process according to the invention, and FIG. The figure is a cross-sectional view showing an outline of the manufacturing method of a conventional sealing ceramic wiring circuit board, FIG. FIG. 5 is a block diagram showing an example of a process for manufacturing a ceramic printed circuit board using a conventional additive method. 1 is a roughened ceramic substrate, 2 is a glass layer,
3 is a circuit section, 4 is a ceramic substrate, and 5 is a sealing ceramic.
Claims (1)
て形成するセラミツクス配線回路板の製法におい
て、粗面化されたセラミツクス基板を用意し、つ
ぎにセラミツクス基板面に金属が受容されるよう
に活性化処理を施した後、回路部となる部分以外
の部分にめつきレジストとしてガラスペーストを
付けて焼成するか、または用意されたセラミツク
ス基板の回路部となる部分以外の部分に、先ずめ
つきレジストとしてガラスペーストを付けて焼成
した後、金属が受容されるように活性化処理を施
し、しかる後無電解めつきによつて回路部を形成
し、必要ならば、さらに電解めつきを施すことを
特徴とするセラミツクス配線回路板の製法。1. In a method for manufacturing a ceramic wiring circuit board in which a circuit part is formed by an additive method using plating, a roughened ceramic substrate is prepared, and then an activation treatment is performed so that metal is received on the surface of the ceramic substrate. After applying glass paste as a plating resist to the parts other than the part that will become the circuit part and baking it, or first apply glass paste as a plating resist to the part of the prepared ceramic substrate other than the part that will become the circuit part. After attaching and firing, an activation treatment is performed so that the metal is accepted, and then a circuit part is formed by electroless plating, and if necessary, further electrolytic plating is performed. Manufacturing method for ceramic wiring circuit boards.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30678986A JPS63158894A (en) | 1986-12-23 | 1986-12-23 | Manufacture of ceramic wiring circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30678986A JPS63158894A (en) | 1986-12-23 | 1986-12-23 | Manufacture of ceramic wiring circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63158894A JPS63158894A (en) | 1988-07-01 |
| JPH0357636B2 true JPH0357636B2 (en) | 1991-09-02 |
Family
ID=17961266
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30678986A Granted JPS63158894A (en) | 1986-12-23 | 1986-12-23 | Manufacture of ceramic wiring circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63158894A (en) |
-
1986
- 1986-12-23 JP JP30678986A patent/JPS63158894A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63158894A (en) | 1988-07-01 |
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