JPH0342868A - C-mos thin film transistor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To enhance an n-type impurity concentration and to reduce n-ch source.drain part resistances by forming the upper layer part of the source.drain parts of a n-ch transistor in an n-type impurity high concentration region, and forming the lower layer part of the n-ch, p-ch source.drain parts and n-ch, p-ch gate electrodes in p-type impurity high concentration regions. CONSTITUTION:Polysilicon is deposited on a quartz board 1, and p-ch, n-ch active layers 2 are formed. Then a thermal oxide film 3 is grown on the surface of the polysilicon by thermally oxidizing. Then, polysilicon is deposited to form a gate electrode 4. In this case, a resist pattern 5 formed by a photolithography remains as it is. Thereafter, a resist 6 is formed on the p-ch, P<+> ions 7 are implanted under predetermined conditions to form n-ch source.drain regions. Subsequently, after the whole resist is removed, B<+> ions 9 are implanted under predetermined conditions to simultaneously form p-ch source.drain regions and implant impurity in the electrodes 4 of both transistors. Then, the ions are activated. Here, born 10 is controlled to be implanted in the upper layer of the layer 2 and the lower layer of phosphorus 8 to sufficiently lower sheet resistances of the source.drain parts.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a C-MOS thin film transistor device and a method for manufacturing the same.

[Prior art]

A conventional method for manufacturing a CMOS transistor in a single crystal wafer process has generally been carried out in the following order.

(1) Formation of p-well using wafer n (100) ~ 2Ω equipment (2) Growth of PAD oxide, Si, N, films (3) Active photolithography (4) P-channel photolithography (5) Boron Ion implantation (6) Field oxidation (7) Gate oxide growth (8) VTH control photolithography (9) Boron ion implantation (10) Polysilicon growth (11) Phosphorus diffusion (gate diffusion) (12) Poly Silicon patterning (13) n” diffusion photolithography (14) Arsenic ion implantation: lXl0”aam-” (15
〉 Drive-in (16) p” diffusion photolithography (17) Boron ion implantation: lX10”■-2 (18)
Growth of PSG film (19) Annealing (13) to (19) is the formation of source/drain regions (2)
0) Contact photolithography (21) Formation of AQ wiring (22) Sintering (23) Formation of passivation film As is clear from this process order, reducing the resistance of the gate electrode and forming the source/drain regions are separate processes. It was done.

〔the purpose〕

The first object of the present invention is to perform the above two steps in the same step.

In order to achieve the first objective, P-type and n-type impurities are introduced into the source and drain parts of the nch transistor, and as a result, it is necessary to make the n-type impurity concentration higher than the p-type impurity concentration. However, this alone leaves the problem that the resistance of the source/drain portion is high.

Therefore, a second object of the present invention is to sufficiently lower the resistance of the source/drain portion of the nch.

〔composition〕

One of the aspects of the present invention is to provide a semiconductor device having a thin film-like first semiconductor layer as an active element and a second semiconductor layer formed on the first semiconductor layer with an insulating film interposed therebetween as a gate electrode. −
In a MOS thin film transistor device, the upper layer part of the source/drain part of the nch transistor is an n-type impurity high concentration region, and the lower part of each of the source/drain part of the nch transistor and the source/drain part of the pch transistor and the nch.

The present invention relates to a C-MOS thin film transistor device (1) characterized in that each gate electrode of pch is a p-type impurity high concentration region.

The C-MOS thin film transistor device! In order to manufacture (I), firstly, the n-type impurity is introduced and diffused by controlling the implantation energy only into the upper layer of the source/drain part of the nch transistor, and then the second Source and drain portions of transistors, gate electrodes and source and drain portions of nch transistors,
By controlling the energy of implanting p-type impurities into the gate electrode,
It is sufficient to introduce and diffuse type impurities.

Another aspect of the present invention is that a first semiconductor layer in the form of a thin film is used as an active element, and a second semiconductor layer formed on the first semiconductor layer with an insulating film interposed therebetween is configured as a gate electrode. In a C-MOS thin film transistor device, the upper layer of the source/drain portion of the PCH transistor is a p-type impurity high concentration region, and the lower layer portions of the source/drain portion of the PCH transistor and the source/drain portion of the nch transistor, and the lower layer portions of the source/drain portion of the nch transistor are The present invention relates to a C-MOS thin film transistor device (II) characterized in that each gate electrode of , pch is an n-type impurity high concentration region.

To manufacture the C-MOS thin film transistor device (II), first, the p-type impurity is introduced and diffused only into the upper layer of the source/drain portion of the pCh transistor by controlling the implantation energy of the p-type impurity. Second, n-type impurities may be introduced and diffused into the source/drain portions of the nch transistor, the gate electrode, and the source/drain portions of the pch transistor, and the gate electrode by controlling the implantation energy of the n-type impurities.

A feature of the manufacturing method of the present invention is that the range of impurities is controlled by controlling the implantation energy. Therefore, the type of impurity can be freely selected, but the implantation energy differs depending on the type of impurity.

The present invention will be explained with reference to the drawings (FIGS. 1 to 4).

Reference numeral 1 denotes an insulating substrate made of quartz, glass, etc., on which an active layer 2 made of polysilicon is formed, and a gate oxide film 3 is formed on the surface of this active layer 2 by thermal oxidation. The n-type impurity high concentration region is formed in the upper layer of the source/drain portion of the nch transistor (indicated by 0000 in the figure), and the p-type impurity high concentration region is formed in the source/drain portion of the pQh transistor and the source of the nch transistor.・Each lower layer part of the drain part and nch
, formed on each gate electrode of pch (×××× in the figure)
).

〔Example〕

Example 1 As shown in FIG.
1,200 layers are deposited using the LP-CVD method, and the active layer 2 of the PCH and nch transistors is formed using the photolithography technique. Thermal oxidation was performed at 1020°C in a dry 02 atmosphere to form a thermal oxide film of 800% on the surface of Po1ySi.
grow.

Next, using Po1y5itrLP-CVD method, 30
Gate electrode 4 was deposited using photolithography and etching technology.
form. At this time, the resist pattern 5 formed by photolithography is left as is (FIG. 1). Next, as shown in FIG. 2, a resist 6 is formed on the PCH transistor by photolithography, and phosphorus (P") 7 is implanted by ion implantation at an energy of 80 KeV and a dose of 4 x 10"a.
Inject under the conditions of toa+s/d (Figure 2). In this step, the source and drain regions of the nch transistor are formed. Subsequently, the resist is completely removed by O and plasma ashing, and then boron (B") 9 is implanted by ion implantation at an implantation energy of 40 KaV and a dose of 2.times.10" ato/d (FIG. 3).

In this step, the formation of the source/drain regions of the PCH transistor and the implantation of impurities into the gate electrodes 4 of the PCH and nch transistors are simultaneously performed. The implanted ions are activated at 900°C for 30 minutes in an N3 atmosphere.
Boron 10 implanted at eV and 40 eV is mixed, but at the energy mentioned above, the average ion range of phosphorus is smaller than that of boron, and boron 10 is controlled to be in the upper layer of active layer 2 and phosphorus 8 in the lower layer. Injected.

Therefore, the sheet resistance of the source/drain portions of the active layer 2 was sufficiently low to about 500 Ω. When the average ion ranges are approximately equal to each other, 90 KeV for phosphorus and 30 KaV for boron, only a very high sheet resistance of ~5.OMEGA. is obtained.

Note that the sheet resistance of the gate electrode 4 at this time was ~200Ω8. Finally, 1f between layers! Take 1m membrane 11 and LP-
SiO by CVD method.

is deposited, and contact holes are formed using photolithographic etching technology. AQ is applied to the metal electrode using sputtering method.
The C-MOS transistor device of the present invention is produced by depositing and patterning using photolithography technology! i (Figure 4) is completed.

Example 2 In Example 1, boron 10 was implanted into the gate electrode 4, but a process of implanting phosphorus is also possible.

In other words, the process is exactly the same up to Figure 1, but in Figure 5 boron (
Bo) was implanted at an energy of 25 KeV and a dose of 5
The implantation is performed under the conditions of 10"atoms/d. Next, in the process shown in FIG. 6, phosphorus (P9) is implanted under the conditions of an implantation energy of 100KeV and a dose of 2.times.10"atoms/aJ. The subsequent steps are the same as in Example 1. The difference from Example 1 is that the impurity of the gate electrode mentioned above is phosphorus;
A transistor having a source/drain region in which different types of impurities are mixed is a pchh transistor rather than an nch transistor (see FIG. 7).

Note that the sheet resistance of the gate electrode and the sheet resistance of the source/drain region of the PCH transistor were approximately the same as in Example 1.

〔effect〕

With the configuration and manufacturing method of the present invention, it is now possible to perform the lowering of the resistance of the gate electrode and the formation of the source/drain regions in a single process, whereas conventionally these were performed separately.

Further, the present invention makes the source/drain regions of the nch transistor low resistance by dividing the source/drain portions of the nch transistor into an upper layer portion and a lower layer portion and forming regions with high concentration of n-type impurities and p-type impurities. We were able to.

[Brief explanation of drawings]

1 to 4 are for showing the manufacturing process of the C-MOS thin film transistor device of the present invention, and FIGS. 5 to 7 show modifications thereof. In addition, all are cross-sectional views of the product at each step. DESCRIPTION OF SYMBOLS 1... Substrate 2... Active layer 3... Oxide film 4... Gate electrode 5... Resist pattern 6... Resist 7... Phosphorus ion 8... Phosphorus high concentration region 9. ...Boron ion 10...High concentration region of boron 11...Interlayer insulating film 12...Metal electrode diagram ncn tofusin Aγ

Claims (1)

[Claims] 1. A thin film-like first semiconductor layer as an active element;
In a C-MOS thin film transistor device configured using a second semiconductor layer formed on the upper layer of the semiconductor layer with an insulating film interposed therebetween as a gate electrode, the upper layer of the source/drain portion of the nch transistor is formed as an n-type impurity high concentration region. year,
source/drain part of nch transistor and pc
A C-MO characterized in that the lower layers of the source and drain portions of the h-transistor and the gate electrodes of the nch and pch are made into p-type impurity high concentration regions.
S thin film transistor device. 2. First, the n-type impurity is introduced and diffused by controlling the implantation energy only into the upper layer of the source/drain portion of the nch transistor, and then the second p-type impurity is introduced and diffused.
C according to claim 1, characterized in that the p-type impurity is introduced and diffused into the source/drain portion of the channel transistor, the gate electrode and the source/drain portion of the nch transistor, and the gate electrode by controlling the implantation energy of the p-type impurity. - A method for manufacturing a MOS thin film transistor device. 3. The thin film-like first semiconductor layer is used as an active element, and the first semiconductor layer is used as an active element.
In a C-MOS thin film transistor device configured with a second semiconductor layer formed on top of a semiconductor layer via an insulating film as a gate electrode, the top layer of the source/drain portion of the PCH transistor is formed as a p-type impurity high concentration region. year,
Source/drain part of pch transistor and nc
A C-MO characterized in that the lower layer portions of the source and drain portions of the h-transistor and the gate electrodes of the nch and pch are made into n-type impurity high concentration regions.
S thin film transistor device. 4. First, the p-type impurity is introduced and diffused by controlling the implantation energy only into the upper layer of the source/drain portion of the pch transistor, and then the second n-type impurity is introduced and diffused.
C according to claim 1, characterized in that the n-type impurity is introduced and diffused into the source/drain portion of the ch transistor, the gate electrode, and the source/drain portion of the pch transistor, and the gate electrode by controlling the implantation energy of the n-type impurity. - A method for manufacturing a MOS thin film transistor device.