JPH023915A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To shorten manufacturing process, and reduce the cost of a product by dissociating a part of compound ion, simultaneously implanting two kinds of ion, and forming a double-diffusion layer having different depths dependent on the mass difference. CONSTITUTION:An element isolation oxide film 2, a gate oxide film 3 and a gate electrode 4 are formed on a P-type silicon substrate 1. PF3 ion gas is accelerated to dissociate P ion in a part of the gas, and PF3 ion and P ion are simultaneously implanted. P ion whose mass is small is deeply implanted. PF3 ion whose mass is large is implanted to a shallow depth. A source region 5 and a drain region 6 of high impurity concentration, and a source region 51 and a drain region 61 of low impurity concentration are simultaneously formed by annealing. An interlayer insulating layer 7 is formed; a contact window is made; an electrode 8 of aluminum film is formed on the regions 5, 6. Thereby, the number of impurity introducing processes is reduced, manufacturing process is shortened, and manufacturing cost is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing a semiconductor device in which double diffusion layers are formed in the same region in one diffusion step.

2. Description of the Related Art A conventional method for manufacturing a double diffusion layer will be described with reference to a process cross-sectional view of an N-channel MOS transistor shown in FIG.

First, an element isolation oxide film 2 is formed on a P-type silicon substrate 1 by selective oxidation, a gate oxide film 3 is formed on a transistor formation region, and then a polysilicon film is grown on the surface and photo-etched. After etching the polysilicon film in the portions not covered with the photoresist by a method, the photoresist is removed and the gate electrode 4 is formed (FIG. 2a).

Next, arsenic ions (As+) are implanted to form a source region 5 and a drain region 6 with high impurity concentration (Fig. 2b).
). Subsequently, phosphorus ions (P+) are implanted to deeply form the source region 51 and drain region 61 with low impurity concentration.
(Fig. 2C).

As a result, so-called DDD (D
Source/drain regions having a double diffused drain structure are formed.

After this, an interlayer insulating layer 7 is deposited, a contact window is provided,
An electrode 8 made of, for example, an aluminum film is formed on the source region 5 and drain region 6 to complete an N-channel MO3t transistor (FIG. 2d).

Problems to be Solved by the Invention In such conventional methods, two ion implantation steps are required to form the source/drain regions of the DDD structure, resulting in a long process.

Means for Solving the Problems The method for manufacturing a semiconductor device of the present invention utilizes compound ions for ion implantation, dissociates only a portion of them, and implants two types of ions at the same time. A heavy diffusion layer is formed at the same time.

Effect: According to the semiconductor device manufacturing method of the present invention, since two types of ions with different masses are implanted simultaneously, the degree of acceleration differs due to the difference in mass, and the double diffusion layer is formed due to the difference in implantation depth. It is formed.

Embodiment An embodiment of the method of manufacturing a semiconductor device according to the present invention will be described with reference to the process cross-sectional view of an N-channel MOS transistor shown in FIG. In FIG. 1, the same parts as in FIG. 2 are given the same numbers.

First, an element isolation oxide film 2 is formed on a P-type silicon substrate 1 by selective oxidation, a gate oxide film 3 is formed on a transistor formation region, and then a polysilicon film is formed on the surface. A gate electrode 4 is formed by etching (FIG. 1a).

Next, for example, P at a dose of 3×1015 CI11-3
This method utilizes the fact that F3+ is accelerated with an energy of 100 KeV, and of which, for example, 5 x 10" cm of PF3+ is dissociated into P+ and a part of the product ions are dissociated.

A light amount of P+ was injected to a depth of 0.4 μm,
PF3+, which has a large mass, is shallowly implanted to a depth of 0.2 μm. Thereafter, by performing annealing, the source region 5 and drain region 6 with high impurity concentration and the source region 51 and drain region 61 with low impurity concentration are formed simultaneously (
Figure 1 b). Subsequently, an interlayer insulating layer 7 is formed, a contact window is provided, and an electrode 8 made of an aluminum film is formed on the source region 5 and drain region 6, thereby completing a DDD structure MOS transistor (FIG. 1C). .

In this embodiment, the case of N-channel MO8 was explained, but P-channel MO8゜complementary MO8
Of course, it can also be used to form double diffusion layers in bipolar transistors, etc., and can also be used as an ion source with other compounds such as phosphorus (P) compounds other than PF3+ or boron (B) compounds such as BF2+. It goes without saying that it can be done.

Effects of the Invention According to the method for manufacturing a semiconductor device of the present invention, a double diffusion layer can be formed by simultaneously implanting two types of ions with different masses, so the number of impurity introduction steps can be reduced compared to conventional methods. As a result, manufacturing schedules can be shortened and product prices can be lowered.

[Brief explanation of the drawing]

FIG. 1 is a process cross-sectional view of an N-channel MOS transistor showing one embodiment of the method for manufacturing a semiconductor device of the present invention, and FIG.
The figure is a process cross-sectional view of a conventional N-channel MOS transistor. 1... P-type silicon substrate, 2... Element isolation oxide film, 3... Gate oxide film, 4...
... Gate electrode, 5 ... Source region with high impurity concentration, 51 ... Source region with low impurity concentration, 6
...Drain region with high impurity concentration, 61...
. . . Drain region with low impurity concentration, 7 . . . Interlayer insulating film, 8 . . . Electrode. Name of agent: Patent attorney Toshio Nakao and one other person Fig. Fig. ＼ δ /

Claims (1)

[Claims] By simultaneously implanting two types of ions generated from the same raw material gas into the semiconductor substrate in one ion implantation,
A method for manufacturing a semiconductor device, comprising forming a double diffusion layer.