JPH023270A - HCT semiconductor device manufacturing method - Google Patents
HCT semiconductor device manufacturing methodInfo
- Publication number
- JPH023270A JPH023270A JP63323827A JP32382788A JPH023270A JP H023270 A JPH023270 A JP H023270A JP 63323827 A JP63323827 A JP 63323827A JP 32382788 A JP32382788 A JP 32382788A JP H023270 A JPH023270 A JP H023270A
- Authority
- JP
- Japan
- Prior art keywords
- region
- forming
- film
- substrate
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 21
- 239000004065 semiconductor Substances 0.000 title claims description 20
- 239000000758 substrate Substances 0.000 claims description 27
- 238000000034 method Methods 0.000 claims description 24
- 229910052751 metal Inorganic materials 0.000 claims description 19
- 239000002184 metal Substances 0.000 claims description 19
- 150000004767 nitrides Chemical class 0.000 claims description 11
- 238000010438 heat treatment Methods 0.000 claims description 8
- -1 arsenic ions Chemical class 0.000 claims description 5
- 150000002500 ions Chemical class 0.000 claims description 5
- 229910052698 phosphorus Inorganic materials 0.000 claims description 4
- 239000011574 phosphorus Substances 0.000 claims description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 3
- 229910052785 arsenic Inorganic materials 0.000 claims description 2
- 230000001681 protective effect Effects 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 1
- 230000003647 oxidation Effects 0.000 claims 1
- 238000007254 oxidation reaction Methods 0.000 claims 1
- 229920002120 photoresistant polymer Polymers 0.000 description 30
- 238000005468 ion implantation Methods 0.000 description 9
- 238000005530 etching Methods 0.000 description 6
- 230000005669 field effect Effects 0.000 description 4
- 238000000576 coating method Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000012938 design process Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/0188—Manufacturing their isolation regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
- H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
- H10D84/85—Complementary IGFETs, e.g. CMOS
- H10D84/858—Complementary IGFETs, e.g. CMOS comprising a P-type well but not an N-type well
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
本発明はＨＣＴ （Ｈｉｇｈ ５ｐｅｅｄ ＣＭＯ３Ｔ
ＴＬ）半導体装置の製造方法に関するもので、特にフィ
ールド領域のキャパシタンスを調節して半導体装置の動
作速度を調節する半導体装置の製造方法に関するもので
ある。[Detailed Description of the Invention] The present invention relates to HCT (High 5peed CMO3T
TL) The present invention relates to a method of manufacturing a semiconductor device, and particularly relates to a method of manufacturing a semiconductor device in which the operating speed of the semiconductor device is adjusted by adjusting the capacitance of a field region.
一般に、ロジック回路に使用される半導体装置の動作速
度を調節しうる要素は回路設計（Ｄｅｓｉｇｎ）と製造
工程（Ｐｒｏｃｅｓｓ）の二つがあり、その中で製造工
程による速度調節はフィールド酸化膜の深さによる寄生
キャパシタンスの量を調節するので可能である。In general, there are two factors that can adjust the operating speed of semiconductor devices used in logic circuits: circuit design and manufacturing process. This is possible because it adjusts the amount of parasitic capacitance due to
寄生キャパシタンスの量を調節すると、抵抗成分と寄生
キャパシタンスによって決定される時間の関数τが変化
するのでフィールド酸化膜の深さを調節して製造工程に
よって調節されることが出来る半導体装置の動作速度は
かなりカバー（Ｃｏｖｅｒ）することが出来る。Adjusting the amount of parasitic capacitance changes the resistance component and the time function τ determined by the parasitic capacitance, so the operating speed of the semiconductor device can be adjusted through the manufacturing process by adjusting the depth of the field oxide film. It can be covered considerably.
第１図はＰ型ＭＯＳ電界効果トランジスターＰＭＯ３と
Ｎ型ＭＯ３電界効果トランジスターＮＭＯ３を具備して
入力データＶｉの反転された出力データＶｏを出力する
通常的なＣＭＯＳインバーターを図示したものである。FIG. 1 shows a conventional CMOS inverter that includes a P-type MOS field effect transistor PMO3 and an N-type MO3 field effect transistor NMO3 and outputs output data Vo which is an inversion of input data Vi.
第２図は第１図の斜線ＮＭＯ３とＰＭＯ３との間のフィ
ールド領域ａの断面図を図示した図面であって、図面を
参照すると、領域１はＮ型半導体基板領域であり、領域
２はＮＭＯ３が形成Ｐ型ウェル（Ｐ −ｔｙｐｅ ｗｅ
ｌｌ ）領域であり、領域３はＰ−ウェ、ル（Ｐ ＋
ｖｅｌｌ）をオームコンタクトする領域であり、領域４
はＮＭＯＳドレインにＮ十領域であり、領域５はＮ＋ス
トップチャネル領域であり、領域６はＰＭＯＳドレイン
になるＰ ＋’６ｉ域であり、領域７はフィールド酸化
膜であり、領域８はＰＭＯ３のドレインとＮＭＯ３のド
レインとを連結する金属ラインである。FIG. 2 is a cross-sectional view of the field region a between the diagonal lines NMO3 and PMO3 in FIG. is formed P-type well (P-type we
ll) region, and region 3 is P−we,ru(P+
This is the region that makes ohmic contact with the
is the N0 region for the NMOS drain, region 5 is the N+ stop channel region, region 6 is the P+'6i region that becomes the PMOS drain, region 7 is the field oxide film, and region 8 is the drain of PMO3. and the drain of NMO3.
上記のようなＣＭＯ３構造においてはフィールド酸化膜
７の下部領域が高濃度Ｐ十領域と低濃度Ｎ−領域に形成
されているのでフィールド領域のキャパシタンスを調節
することが困難であった。In the CMO3 structure as described above, since the lower region of the field oxide film 7 is formed into a high concentration P region and a low concentration N- region, it is difficult to adjust the capacitance of the field region.
其れ故に、従来にはフィールド酸化膜の厚さを高めるＡ
ＨＣＴ工程とフィールド酸化膜の厚さを低めるＨＣＴＬ
ＳＩ程の二つの方法で製造方法を二元化して実施してあ
ったので生産にかなり沢山の難しさがあったのである。Therefore, it is conventional to increase the thickness of the field oxide film A.
HCT process and HCTL to reduce field oxide thickness
There were quite a lot of difficulties in production because SI had two different manufacturing methods.
したがって、本発明の目的はフィールド酸化膜の厚さの
調節が容易し、且つ製造方法を一元化することが出来る
半導体装置の製造方法を提供することにある。SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device that allows easy adjustment of the thickness of a field oxide film and unifies the manufacturing method.
以下、本発明を添付図面を参照して詳細に説明する。Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
第３（Ａ）〜（１）図は本発明による実施例の製造工程
図であって、ＣＭＯＳインバーターを製造する製造工程
の断面図である。FIGS. 3(A) to 3(1) are manufacturing process diagrams of an embodiment of the present invention, and are sectional views of the manufacturing process of manufacturing a CMOS inverter.
図面を参照すると、先ず、Ｎ−シリコン半導体基板１０
上に通常の酸化膜の形成工程で初期酸化膜１１を２００
０〜３０００人程度の厚さで形成する。Referring to the drawings, first, an N-silicon semiconductor substrate 10
An initial oxide film 11 of 200 mm is formed on top using a normal oxide film formation process.
It is formed with a thickness of about 0 to 3,000 people.
その次に、Ｎ型ＭＯ３電界効果トランジスターが形成さ
れるＰ型ウェル領域を形成するために基板１０の上部の
全面にフォトレジストを塗布して通常の写真工程でＰ型
うウェルが形成される領域の上部に窓１２を形成するフ
ォトレジストマスクバタン１３を形成する。Next, in order to form a P-type well region where an N-type MO3 field effect transistor will be formed, a photoresist is applied to the entire upper surface of the substrate 10, and a region where a P-type well will be formed is formed by a normal photo process. A photoresist mask button 13 forming a window 12 is formed on the top of the photoresist mask button 13 .
その次に、上記のフォトレジストマスクパタン１３を蝕
刻マスクにして窓１２の領域の露出された初期酸化膜１
１を蝕刻した後にＰ−ウェルを形成するために２Ｘ１０
１３〜３Ｘ１０”１ｏｎｓ／ｃｍｌの線量でエネルギー
は４０〜５０Ｋｅｖにして硼素イオン注入をしてＰ型イ
オン注入領域１４を第３（Ａ）図のように形成する。Next, using the photoresist mask pattern 13 as an etching mask, the exposed initial oxide film 1 in the area of the window 12 is etched.
2X10 to form P-well after etching 1
Boron ions are implanted at a dose of 13-3.times.10" 1 oz/cml and an energy of 40-50 Kev to form a P-type ion implantation region 14 as shown in FIG. 3(A).
その次に、Ｐ−ウェル領域を形成するためにフォトレジ
ストマスクバタンを除去したのちに通常のドライブイン
（Ｄｒｉｖｅ ＝ｉｎ）工程で上記のＰ型イオン注入領
域１４のＰ型イオンを再分布（又は拡散）させてＰ−ウ
ェル１５を形成する。 この工程時にＰ−ウェルの接合
の深さ（Ｊｕｎｃｔｉｏｎ Ｄｅｐｔｈ ）は５〜６
μｍ程度になるようにし、この時、Ｐ−ウェル１５の領
域の上部には５０００〜５５００人程度の酸化膜が成長
される。Next, after removing the photoresist mask button to form a P-well region, the P-type ions in the P-type ion implantation region 14 are redistributed (or Diffusion) to form a P-well 15. During this process, the junction depth of the P-well is 5 to 6.
At this time, an oxide film of about 5,000 to 5,500 layers is grown on the P-well 15 region.
その次に、上記の基板１０の上部の初期酸化膜１１と図
面には図示されていないが、ドライブイン工程で成長し
た酸化膜を凡て除去する。Next, the initial oxide film 11 on the top of the substrate 10 and the oxide film grown in the drive-in process (not shown in the drawing) are all removed.
その次に、基板上部の全面に１５０〜２００人の厚さの
第１酸化膜１６を成長させ、上記の第１酸化膜１６の全
面に５ｉｚＮ４である窒化膜１７を通常のＣＶＤ方法で
塗布する。Next, a first oxide film 16 with a thickness of 150 to 200 nm is grown on the entire surface of the upper part of the substrate, and a nitride film 17 of 5izN4 is applied on the entire surface of the first oxide film 16 by a normal CVD method. .
その次に、上記の窒化膜１７の上部にフォトレジストを
塗布し、通常の写真工程でＮ型ＭＯ３）ランシスターが
形成されるＰ−ウェル領域１８とＰ型ＭＯ３Ｉ−ランシ
スターが形成される基板上部の領域１９とＰ−ウェル領
域のエツジ部分のＰ＋オーム接触が形成される領域２０
とＮ＋ストップチャネル領域２１の上部がマスキングさ
れたフォトレジストマスクパタン２２を第３図（Ｂ）図
のように形成する。Next, a photoresist is coated on the top of the nitride film 17, and a P-well region 18 where an N-type MO3) run sister is formed and a substrate where a P-type MO3I- run sister is formed are formed using a normal photo process. A region 20 where a P+ ohmic contact is formed between the top region 19 and the edge of the P-well region.
A photoresist mask pattern 22 in which the upper part of the N+ stop channel region 21 is masked is formed as shown in FIG. 3(B).
その次に、上記のフォトレジストマスクパタン２２を蝕
刻マスクにして露出された窒化膜１７を蝕刻し、基板上
部の上記のフォトレジストマスクバタン２２を除したの
ちに通常の熱処理工程でフィールド酸化膜２３を１１０
０人程度０厚さで成長させる。Next, the exposed nitride film 17 is etched using the photoresist mask pattern 22 as an etching mask, and after the photoresist mask pattern 22 on the upper part of the substrate is removed, the field oxide film 23 is removed by a normal heat treatment process. 110
Grow at a thickness of about 0 people.
この工程においては拡散のヒーティングサイクル（Ｄｉ
ｆｏｕｉｏｎ Ｈｅａｔｉｎｇ Ｃｙｃｌｅ）を調節し
てフィールド酸化膜２３の厚さを自由に調節することが
でき、上記においてはインバーターを゛ハイ°°スピー
ド（！ｌｉｇｈ ５ｐｅｅｄ）にするためにフィールド
酸化膜の厚さを１１００人程度０厚たが、゛′ロウパス
ピード（Ｌｏｗ ５ｐｅｅｄ）にする場合、フィールド
酸化膜の厚さを７００人、５００人、３００人等で調節
することも出来るし、且つフィールド酸化膜を成長する
工程をしないことも出来る。In this process, a diffusion heating cycle (Di
The thickness of the field oxide film 23 can be freely adjusted by adjusting the fouion heating cycle. The thickness of the field oxide film was about 1,100 people, but if you set it to low speed, you can adjust the thickness of the field oxide film to 700 people, 500 people, 300 people, etc. It is also possible to skip the growing process.
その次に、Ｎ型ＭＯ３）ランシスターのドレイン及びソ
ースとストップチャネル領域を形成するために上記の基
板１０の上部の全面にフォトレジストを塗布し、通常の
写真工程でＮ型ＭＯ３Ｉ−ランシスターのドレイン及び
ソースが形成される領域２４とストップチャネル領域２
５を除外した領域がマスキングされたフォトレジストマ
スクバタン２６を第３（Ｃ）図のように形成した後、上
記のフォトレジストマスクバタン２６を蝕刻マスクにし
て露出された窒化膜１７を蝕刻する。Next, a photoresist is coated on the entire upper surface of the substrate 10 to form the drain and source of the N-type MO3) run sister and a stop channel region, and the N-type MO3 I- run sister is formed using a normal photo process. Region 24 where drain and source are formed and stop channel region 2
After forming a photoresist mask button 26 in which the area except the area 5 is masked as shown in FIG. 3C, the exposed nitride film 17 is etched using the photoresist mask button 26 as an etching mask.
その次に、上記のフォトレジストマスクパタン２６をイ
オン注入マスクにして線量を１×１０′５〜３Ｘ１０”
１ｏｎｓ／ｃ己にし、エネルギーは５０〜６０Ｋｅｖ程
度である燐イオン注入をしたのちに線量は２Ｘ１０”〜
４Ｘ１０Ｉ５ｉｏｎｓ／ｃｒｉであり、エネルギーは７
０〜８０Ｋｅｖで砒素イオン注入をしてＮ＋イオン注入
領域２７．２８を形成する。Next, using the photoresist mask pattern 26 as an ion implantation mask, the dose is adjusted to 1×10'5 to 3×10''.
After implanting phosphorus ions at 1 ounce/c self and energy at about 50 to 60 Kev, the dose is 2X10”~
4X10I5ions/cri, and the energy is 7
Arsenic ion implantation is performed at 0 to 80 Kev to form N+ ion implantation regions 27 and 28.
上記のように燐と砒素イオンの２次のイオン注入をする
と、Ｎ型ＭＯＳトランジスターの接合ブレーキダウン電
圧（Ｊｕｎｃｔｉｏｎ Ｂｒｅａｋ Ｄｏｗｎ Ｖｏｌ
ｔａｇｅ）が増加されてＮ型ＭＯＳ電界効果トランジス
ターの特性が向上される。When secondary ion implantation of phosphorus and arsenic ions is performed as described above, the junction break down voltage (Junction Break Down Vol.
tage) is increased, thereby improving the characteristics of the N-type MOS field effect transistor.
その次に、基板上部のフォトレジストマスクパタン２６
を除去した後に通常の熱処理工程で上記のＮ＋イオン注
入領域２７．２８を活性化してＮ型ＭＯＳ）ランシスタ
ーのドレイン及びソース２９とストップチャネル領域３
０を形成する。Next, the photoresist mask pattern 26 on the top of the substrate is
After removing the N+ ion implanted regions 27 and 28 in a normal heat treatment process, the drain and source 29 of the N type MOS transistor and the stop channel region 3 are activated.
form 0.
この工程で形成されるＮ ＋ ｍｌ域の接合の深さは０
．５μｍ程度であり、この時Ｎ十領域２９．３０の上部
には１０００人の酸化膜３１が形成される。The depth of the junction in the N + ml region formed in this step is 0.
．． The thickness is about 5 μm, and at this time, an oxide film 31 of 1,000 layers is formed on the upper part of the N1 region 29.30.
その次に、Ｐ型ＭＯ３）ランシスターのドレイン及びソ
ースとＰウェルのオームコンタクトのためのＰ ＋領域
を形成するために上記の基板上部の全面にフォトレジス
トを塗布し、通常の写真工程でＰ型ＭＯ３Ｉ−ランシス
ターのドレイン及びソースが形成される領域３２とＰウ
ェルのオームコンタクトのためのＰ＋が形成される領域
３３を除外した領域がマスキングされたフォトレジスト
マスクパタン３４を第３（Ｄ）図のように形成した後、
上記のフォトレジストマスクパタン３４を蝕刻マスクに
して露出された窒化膜１７を蝕刻する。Next, in order to form P+ regions for ohmic contacts between the drain and source of the P-type MO3) run sister and the P well, a photoresist is coated on the entire upper surface of the above substrate, and a photoresist is applied using a normal photo process. A third (D) photoresist mask pattern 34 is formed in which the regions excluding the region 32 where the drain and source of the type MO3I- run sister are formed and the region 33 where the P+ layer for the ohmic contact of the P well is masked are masked. After forming as shown,
The exposed nitride film 17 is etched using the photoresist mask pattern 34 as an etching mask.
その次に、上記のフォトレジストマスクパタン３４をイ
オン注入マスクにして線量１×１０＋５〜２Ｘ１０”１
ｏｎｓ／ｃ＋１１でエネルギーは３０〜５０Ｋｅｖ硼素
イオン注入をしてＰ＋イオン注入領域３５．３６を形成
する。Next, using the photoresist mask pattern 34 as an ion implantation mask, the dose is 1×10+5 to 2×10”1.
P+ ion implantation regions 35 and 36 are formed by implanting boron ions at an energy of 30 to 50 Kev at ons/c+11.
その次に、基板上部のフォトレジストマスクパタン３４
を除去した後、通常の熱処理工程で上記のＰ＋イオン注
入領域３５．３６を活性化してＰ型ＭＯ３Ｉ−ランジス
クーのドレイン及びソース３７とＰウェルのオームコン
タクトのためのＰ ＋ ｆｉｌ域３８を形成する。Next, a photoresist mask pattern 34 on the top of the substrate is
After removing, the P+ ion implantation regions 35 and 36 are activated by a normal heat treatment process to form a P+ fil region 38 for ohmic contact between the drain and source 37 of the P-type MO3I- transistor and the P well. .
この工程で形成されるＰ ＋ ＴｌＩ域の接合の深さは
０．１ａｍ程度であり、Ｐ＋領域３７．３８の上部には
Ｎ ＋ ８ｆｉ域２９．３０の上部のように１０００人
の厚さの酸化膜３９が形成されるようにする。The depth of the junction in the P + TlI region formed in this process is about 0.1 am, and the upper part of the P + region 37.38 has a thickness of 1000 nm like the upper part of the N + 8fi region 29.30. An oxide film 39 is formed.
その次に、基板の上部に残っている窒化膜１７を除去し
、ＭＯＳ）ランシスターのゲートが形成される領域の第
１酸化膜１６を除去した後、ゲート酸化膜４０を３００
〜４００人の厚さで成長する。Next, the nitride film 17 remaining on the upper part of the substrate is removed, and the first oxide film 16 in the region where the gate of the MOS transistor is formed is removed, and then the gate oxide film 40 is
Grows to ~400 people thick.
その次に、Ｎ型ＭＯ３Ｉ−ランシスターのドレイン及び
ソース領域２９とＰ型ＭＯ３）ランシスターのドレイン
及びソース領域３７の上部にコンタクトｆｉＩ域を形成
するために基板上部の全面にフォトレジストを塗布した
後、通常の写真工程でフォトレジストマスクパタン４３
を第３（Ｅ）図のように形成する。Next, a photoresist was applied to the entire upper surface of the substrate in order to form a contact fiI region on the drain and source region 29 of the N-type MO3I-Ran sister and the drain and source region 37 of the P-type MO3I-Ran sister. After that, a photoresist mask pattern 43 is formed using a normal photo process.
is formed as shown in FIG. 3(E).
その次に、上記のフォトレジストマスクパタン４３を蝕
刻マスクにしてＮ十領域２９とＰ＋領域３７の上部に接
続窓４１．４２を形成した後、基板上部のフォトレジス
トマスクパタン４３を凡て除去する。Next, using the photoresist mask pattern 43 as an etching mask, connection windows 41 and 42 are formed above the N+ region 29 and the P+ region 37, and then the entire photoresist mask pattern 43 on the top of the substrate is removed. .
その次に、ＭＯＳ）ランシスターの各電極を形成するた
めに基板の全面に通常の金属塗布方法で第１金属膜を塗
布し、各電極をパターンニングするために上記の第１金
属膜の上部にフォトレジスト４５を塗布し、通常の写真
蝕刻工程で金属電極４４ａ、４４ｂ、４４ｃ、４４ｄ、
４４ｅを第３（Ｆ）図のように形成した後、基板の上部
に残っているフォトレジストマスクパタン４５を除去す
る。上記の図示した半導体装置はＣＭＯＳインバーター
を図示したもので、電極４４ｃはＮ型ＭＯＳトランジス
ターのドレイン電極とＰ型ＭＯ３）ランシスターの電極
が接続されて形成される。Next, a first metal film is applied to the entire surface of the substrate using a normal metal application method to form each electrode of the MOS (MOS) Runister, and the upper part of the first metal film is patterned to pattern each electrode. A photoresist 45 is applied to the metal electrodes 44a, 44b, 44c, 44d,
After forming 44e as shown in FIG. 3(F), the photoresist mask pattern 45 remaining on the top of the substrate is removed. The semiconductor device illustrated above is a CMOS inverter, and the electrode 44c is formed by connecting the drain electrode of an N-type MOS transistor and the electrode of a P-type MO3) run transistor.
その次に、上記の基板上部に低温酸化膜を形成し、以後
に形成される第２金属膜と上記の第１金属膜を接続する
ために基板上部の全面にフォトレジスト４７を塗布した
後、通常の写真蝕刻の工程で低温酸化膜４６のバタンを
第３（Ｇ）図のように形成し、基板上部のフォトレジス
トマスクパタン４７を除去する。Next, a low-temperature oxide film is formed on the upper part of the substrate, and a photoresist 47 is applied to the entire upper part of the substrate in order to connect the second metal film to be formed later with the first metal film. A pattern of low-temperature oxide film 46 is formed as shown in FIG. 3(G) using an ordinary photolithography process, and the photoresist mask pattern 47 on the upper part of the substrate is removed.
その次に、基板上部の全面に通常の金属塗布方法で第２
金属膜４８を塗布して第１金属膜４４と第２金属膜４８
を連結させ、第２金属膜４８の上部にフォトレジスト４
９を塗布したのち、通常の写真蝕刻工程で第２金属膜４
８のパタンを第３（Ｈ）図のように形成する。Next, a second coating is applied to the entire surface of the upper part of the substrate using the usual metal coating method.
The first metal film 44 and the second metal film 48 are coated with the metal film 48.
A photoresist 4 is placed on the top of the second metal film 48.
After coating 9, a second metal film 4 is formed using a normal photolithographic process.
8 patterns are formed as shown in FIG. 3(H).
その次に、上記の基板上部のフォトレジストマスフパタ
ン４９を凡て除去し、基板上部に半導体装置の表面安定
化（Ｐａｓｓｉνａｔｉｏｎ）のために保護膜層５０を
第３（Ｉ）図のように形成する。Next, all the photoresist mask patterns 49 on the upper part of the substrate are removed, and a protective film layer 50 is formed on the upper part of the substrate for surface stabilization (passivation) of the semiconductor device as shown in FIG. 3(I). Form.
上述したように本発明はフィールド酸化膜の領域のキャ
パシタンスを容易に調節することが出来るので従来二元
化されている製造工程を一元化するとか出来るばかりで
はなく、半導体装置の動作速度を容易に調節することが
出来る利点がある。As mentioned above, since the present invention can easily adjust the capacitance of the field oxide film region, it not only makes it possible to unify the conventionally dual manufacturing process, but also makes it possible to easily adjust the operating speed of the semiconductor device. There is an advantage that it can be done.
又、本発明はロジック回路に使用される凡ての半導体装
置の製造に使用することができる。Further, the present invention can be used for manufacturing all semiconductor devices used in logic circuits.
第１図はＣＭＯＳインバーター回路図、第２図は上記の
第１図のａ領域の断面図、第３（Ａ）〜（１）図は本発
明による製造工程図である。
第
第３図
Δ）
３図
ｑ）
第３図
ｐ）
第３図
口１FIG. 1 is a CMOS inverter circuit diagram, FIG. 2 is a sectional view of region a in FIG. 1, and FIGS. 3(A) to 3(1) are manufacturing process diagrams according to the present invention. Figure 3 Δ) Figure 3 q) Figure 3 p) Figure 3 Port 1
Claims (1)
２導電型のウェル領域１５を形成する第１工程と、 上記の基板１０の上部に第１酸化膜１６と窒化膜を順次
的に形成する第２工程と、 上記のウェル領域上部に第１ＭＯＳトランジスターのド
レイン及びソース２９と基板の所定領域にストップチャ
ネル領域３０を形成する第３工程と、 上記の基板上部のストップチャネル領域３０との間に第
２ＭＯＳトランジスターのドレイン及びソース３７と上
記のウェル１５のエッジ領域にオーム接触領域３８を形
成する第４工程と、 基板上部の窒化膜を除去し、第１及び第２ＭＯＳトラン
ジスターのゲート領域の第１酸化膜１６を除去した後に
ゲート酸化膜を形成するために基板全面に酸化膜４０を
形成する第５工程と、上記の第１及び第２ＭＯＳトラン
ジスターのソース及びドレインの接続のための接続窓４
１、４２を形成する第６工程と、 第１及び第２ＭＯＳトランジスターの各電極を形成する
ために第１金属膜４４ａ、４４ｂ、４４ｃ、４４ｄ、４
４ｅのパタンを形成する第７工程と、 上記の第１金属膜の上部に第１金属膜を所定部位と絶縁
させるために低温酸化膜４６のパタンを形成する第８工
程と、 上記の低温酸化膜によって隔離されて第１金属膜と絶縁
され、接続窓を通じて第１金属膜と接続される第２金属
膜４８のパタンを形成する第９工程と、 上記の第２金属膜４８上に保護膜層５０を形成する第１
０工程を具備して上記の工程の連続からなることを特徴
とする半導体装置の製造方法。 ２、第１項において、 第２工程後に第２導電型のウェルエッジ領域２０と、上
記のウェル１５の上部の第１ＭＯＳトランジスターが形
成される領域１８と、基板上部の第２ＭＯＳトランジス
ターが形成される領域１９と、上記の領域１９の縁に形
成されるストップチャネル領域２１の上部の窒化膜１７
を除去し、熱処理工程によって上記の窒化膜が露出され
たフィールド酸化膜２３を形成することを特徴とする半
導体装置の製造方法。 ３、第１項において、 第２導電型のウェル１５は２×１０＾１＾５〜３×１０
＾１＾５ｉｏｎｓ／ｃｍ＾２の線量（Ｄｏｓｅ）でエネ
ルギーは４０〜５０Ｋｅｖにして第２導電型のイオン注
入をした後に熱処理して接合の深さを５〜６μｍで形成
することを特徴とする半導体製造方法。 ４、第１項において、 第１ＭＯＳトランジスターのドレイン及びソース２９と
ストップチャネル領域３０は燐又は燐と砒素イオンをイ
オン注入し、熱処理して所定の深さで形成することを特
徴とする半導体装置の製造方法。 ５、第１項において、 第２ＭＯＳトランジスターのドレイン及びソース３７と
ウェルエッジ領域のオーム接触領域３８は第１導電型の
イオン注入をし、熱処理して第１ＭＯＳトランジスター
のドレイン及びソース２９の接合の深さより深く形成す
ることを特徴とする半導体装置の製造方法。[Claims] 1. In a method for manufacturing a semiconductor device, a first step of forming a well region 15 of a second conductivity type in a predetermined region on a silicon semiconductor substrate 10 of a first conductivity type; A second step of sequentially forming a first oxide film 16 and a nitride film on the upper part, and a third step of forming a drain and source 29 of the first MOS transistor on the upper part of the well region and a stop channel region 30 in a predetermined region of the substrate. a fourth step of forming an ohmic contact region 38 on the drain and source 37 of the second MOS transistor between the stop channel region 30 on the top of the substrate and the edge region of the well 15; and a nitride film on the top of the substrate. a fifth step of forming an oxide film 40 on the entire surface of the substrate to form a gate oxide film after removing the first oxide film 16 in the gate regions of the first and second MOS transistors; Connection window 4 for connecting the source and drain of the second MOS transistor
1 and 42; and a sixth step of forming first metal films 44a, 44b, 44c, 44d, 4 to form each electrode of the first and second MOS transistors.
a seventh step of forming a pattern 4e; an eighth step of forming a pattern of a low-temperature oxide film 46 on top of the first metal film to insulate the first metal film from a predetermined portion; and the low-temperature oxidation described above. a ninth step of forming a pattern of a second metal film 48 that is isolated from the first metal film by a film and connected to the first metal film through a connection window; and a protective film on the second metal film 48. The first forming layer 50
1. A method for manufacturing a semiconductor device, comprising a series of the above steps, including zero steps. 2. In item 1, after the second step, a well edge region 20 of the second conductivity type, a region 18 above the well 15 where the first MOS transistor is formed, and a second MOS transistor above the substrate are formed. region 19 and the nitride film 17 above the stop channel region 21 formed at the edge of the region 19.
A method for manufacturing a semiconductor device, which comprises removing the nitride film and forming a field oxide film 23 in which the nitride film is exposed through a heat treatment process. 3. In the first term, the well 15 of the second conductivity type is 2×10^1^5 to 3×10
It is characterized by implanting ions of the second conductivity type at a dose of ^1^5 ions/cm^2 and energy of 40 to 50 Kev, followed by heat treatment to form a junction with a depth of 5 to 6 μm. Semiconductor manufacturing method. 4. In the semiconductor device according to item 1, the drain and source 29 and the stop channel region 30 of the first MOS transistor are formed to a predetermined depth by implanting phosphorus or phosphorus and arsenic ions and by heat treatment. Production method. 5. In item 1, the drain and source 37 of the second MOS transistor and the ohmic contact region 38 in the well edge region are implanted with ions of the first conductivity type and heat treated to increase the depth of the junction between the drain and source 29 of the first MOS transistor. A method for manufacturing a semiconductor device, characterized in that the semiconductor device is formed deeper.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR87-15551 | 1987-12-31 | ||
| KR1019870015551A KR900005354B1 (en) | 1987-12-31 | 1987-12-31 | Manufacturing Method of HCT Semiconductor Device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH023270A true JPH023270A (en) | 1990-01-08 |
Family
ID=19267824
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63323827A Pending JPH023270A (en) | 1987-12-31 | 1988-12-23 | HCT semiconductor device manufacturing method |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US4920066A (en) |
| JP (1) | JPH023270A (en) |
| KR (1) | KR900005354B1 (en) |
| DE (1) | DE3843103A1 (en) |
| FR (1) | FR2625609B1 (en) |
| GB (1) | GB2213321B (en) |
| NL (1) | NL8803213A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3924062C2 (en) * | 1989-07-21 | 1993-11-25 | Eurosil Electronic Gmbh | EEPROM semiconductor device with isolation zones for low-voltage logic elements |
| EP0488801B1 (en) * | 1990-11-30 | 1998-02-04 | Sharp Kabushiki Kaisha | Thin-film semiconductor device |
| US5438005A (en) * | 1994-04-13 | 1995-08-01 | Winbond Electronics Corp. | Deep collection guard ring |
| US6017785A (en) * | 1996-08-15 | 2000-01-25 | Integrated Device Technology, Inc. | Method for improving latch-up immunity and interwell isolation in a semiconductor device |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3983620A (en) * | 1975-05-08 | 1976-10-05 | National Semiconductor Corporation | Self-aligned CMOS process for bulk silicon and insulating substrate device |
| US4152823A (en) * | 1975-06-10 | 1979-05-08 | Micro Power Systems | High temperature refractory metal contact assembly and multiple layer interconnect structure |
| JPS5543842A (en) * | 1978-09-25 | 1980-03-27 | Hitachi Ltd | Manufacture of al gate cmos ic |
| JPS5565446A (en) * | 1978-11-10 | 1980-05-16 | Nec Corp | Semiconductor device |
| US4288910A (en) * | 1979-04-16 | 1981-09-15 | Teletype Corporation | Method of manufacturing a semiconductor device |
| DE3133841A1 (en) * | 1981-08-27 | 1983-03-17 | Siemens AG, 1000 Berlin und 8000 München | METHOD FOR PRODUCING HIGHLY INTEGRATED COMPLEMENTARY MOS FIELD EFFECT TRANSISTOR CIRCUITS |
| DE3318213A1 (en) * | 1983-05-19 | 1984-11-22 | Deutsche Itt Industries Gmbh, 7800 Freiburg | METHOD FOR PRODUCING AN INTEGRATED INSULATION LAYER FIELD EFFECT TRANSISTOR WITH CONTACTS FOR THE GATE ELECTRODE SELF-ALIGNED |
-
1987
- 1987-12-31 KR KR1019870015551A patent/KR900005354B1/en not_active IP Right Cessation
-
1988
- 1988-12-21 DE DE3843103A patent/DE3843103A1/en not_active Ceased
- 1988-12-23 JP JP63323827A patent/JPH023270A/en active Pending
- 1988-12-29 FR FR888817423A patent/FR2625609B1/en not_active Expired - Lifetime
- 1988-12-30 US US07/292,106 patent/US4920066A/en not_active Expired - Lifetime
- 1988-12-30 NL NL8803213A patent/NL8803213A/en not_active Application Discontinuation
-
1989
- 1989-01-03 GB GB8900015A patent/GB2213321B/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| GB8900015D0 (en) | 1989-03-01 |
| KR890011084A (en) | 1989-08-12 |
| GB2213321A (en) | 1989-08-09 |
| FR2625609A1 (en) | 1989-07-07 |
| NL8803213A (en) | 1989-07-17 |
| FR2625609B1 (en) | 1992-07-03 |
| KR900005354B1 (en) | 1990-07-27 |
| US4920066A (en) | 1990-04-24 |
| DE3843103A1 (en) | 1989-07-13 |
| GB2213321B (en) | 1991-03-27 |
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