JPH0555484A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable facilitation of the process and shortening of the process time by curtailing the photoresist step during process of a semiconductor device including CMOS elements. CONSTITUTION:The following steps are included: after a semiconductor substrate 1 (P-type silicon) is surfaced with a conductive film 6 (polysilicon) via a gate insulating film 5, a gate electrode 8N of a reverse conductive MOS transistor and its source-drain region 9N are formed in a state that a one-conductivity MOS transistor region with a first photoresist 7, and a gate electrode 8P of one-conductivity MOS transistor and its sour-drain region 9P are formed in a state that the reverse conductive MOS transistor region is coated with a second photoresist 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device including MOS transistors of different conductivity types.

[0002]

2. Description of the Related Art Conventionally, a method shown in FIG. 3 has been proposed as a method for manufacturing a semiconductor device including MOS transistors of different conductivity types such as a CMOS element. 9A to 9D are sectional views showing the manufacturing method in the order of steps.
First, as shown in FIG. 3A, after forming the P well region 2 and the N well region 3 in the P type silicon substrate 1, the field oxide film 4 is formed by the selective oxidation step to perform element isolation, A gate oxide film 5 is grown to a thickness of about 15 nm in the device region. Further, a polysilicon film 6 is formed on the top surface of about 200
nm to grow.

Next, as shown in FIG. 1B, the polysilicon film 6 is dry-etched using the first photoresist 31 as a mask, and a P-channel MOS transistor (hereinafter referred to as a PMOS transistor) and an N-channel MOS transistor (hereinafter referred to as a PMOS transistor) are formed. Hereinafter, each gate electrode 8P, 8N of the NMOS transistor) is formed. Then, as shown in FIG. 7C, PM is formed using the second photoresist 32 as a mask.
The region of the OS transistor is covered, and phosphorus ions are implanted with an energy of 40 KeV and a dose of about 3.0 × 10 ¹³ cm ^-2 ,
A low concentration N ⁻ diffusion layer 9N of the source / drain region 8N of the NMOS transistor is formed.

Next, as shown in FIG. 3D, the region of the NMOS transistor is covered with the third photoresist 33 as a mask, and boron ions are energized by, for example, energy.
Implanted at 30KeV, dose of about 3.0 × 10 ¹³ cm ^-2 , PMOS
Low concentration P ⁻ of the source / drain region 8P of the transistor
The diffusion layer 9P is formed. After that, although illustration is omitted,
After forming sidewalls on both side surfaces of the gate electrode and forming a high-concentration source / drain region diffusion layer, a PSG film is grown as an interlayer insulating film, and then an electrode portion is opened.
A desired semiconductor device can be obtained by performing a wiring process using aluminum.

[0005]

However, according to this method of manufacturing a semiconductor device, one photoresist process is required to form the gate electrode, and one NMOS transistor and one PMOS transistor are required to form the source and drain regions, respectively. However, there is a problem that the manufacturing process is complicated and time-consuming because three photoresist processes are required only by this process. An object of the present invention is to provide a method of manufacturing a semiconductor device, which can reduce the number of photoresist steps, facilitate the manufacturing, and shorten the manufacturing time.

[0006]

According to a method of manufacturing a semiconductor device of the present invention, a step of forming one conductivity type region and an opposite conductivity type region in a semiconductor substrate, and a method of conducting a semiconductor film on a surface of the semiconductor substrate via a gate insulating film. A step of forming a film, and a step of forming a gate electrode of the reverse conductivity type MOS transistor by patterning the first photoresist leaving only the one conductivity type MOS transistor forming area and the gate forming area of the reverse conductivity type MOS transistor. Forming a source / drain region of a reverse conductivity type MOS transistor by implanting a reverse conductivity type impurity using the first photoresist as a mask,
Patterning the second photoresist to leave only the reverse conductivity type MOS transistor formation region and the gate formation region of the one conductivity type MOS transistor to form the gate electrode of the one conductivity type MOS transistor; and the second photoresist. Is used as a mask, and a step of implanting an impurity of one conductivity type to form a source / drain region of the MOS transistor of one conductivity type is included.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. 1A to 1C are sectional views showing a first embodiment of the present invention in the order of steps. First, as shown in FIG. 3A, a P well region 2 and an N well region 3 are formed on a P type silicon substrate 1, and then a field oxide film 4 is formed by a selective oxidation process to perform element isolation. After that, the gate oxide film 5 is grown to a thickness of about 15 nm. Then, a polysilicon film 6 is grown to a thickness of about 200 nm on the entire surface. Subsequently, as shown in FIG. 3B, the first photoresist 7 is patterned to selectively remove the polysilicon film 6 in the NMOS transistor region to form a gate electrode 8N of the NMOS transistor. At this time, the first photoresist 7 covers the PMOS transistor region. Then, using the first photoresist 7 as a mask, phosphorus ions, for example, have an energy of 40 KeV and a dose of about 3.
Implantation is performed under the condition of 0 × 10 ¹³ cm ^-2 to form the low concentration N ⁻ diffusion layer 9N of the source / drain region 8N of the NMOS transistor.

Next, as shown in FIG. 1C, the second photoresist 10 is patterned to selectively remove the polysilicon film 6 left in the PMOS transistor region, and the gate electrode 8P of the PMOS transistor is removed. To form. At this time, the second photoresist 10 is an NMOS
The transistor region is covered. Then, using the second photoresist 10 as a mask, boron ions, for example, have an energy of 30 KeV and a dose of about 3.0 × 10 ¹³ cm ^-2.
Under the conditions described above to form the low-concentration P ⁻ diffusion layer 9P in the source / drain regions of the PMOS transistor.

Thereafter, although not shown, sidewalls are formed on both sides of the gate electrode of each transistor,
After forming the source / drain region high-concentration diffusion layer, a PSG film is grown as an interlayer insulating film, and then an electrode portion is opened, and wiring processing using aluminum is performed to obtain a desired semiconductor device. Therefore, according to this manufacturing method, the PMOS transistor and the NMOS transistor can be manufactured by two photoresist processes using the first photoresist 7 and the second photoresist 10, and the photoresist can be manufactured once more than the conventional process. The resist process can be reduced.

2A to 2C are sectional views showing a method of manufacturing a BiCMOS integrated circuit according to a second embodiment of the present invention in the order of steps. First, as shown in FIG.
Type silicon substrate 21 with P ⁺ buried layer 22 and N ⁺ buried layer 2
3 is formed, an N-type epitaxial layer 24 is formed,
Subsequently, the P well region 2 and the N well region 3 are formed.
Next, after a field oxide film 4 is formed by a selective oxidation process to separate elements, a gate oxide film 5 is grown to a thickness of about 15 nm. At this time, the oxide film is removed only in the collector portion of the NPN bipolar transistor. Then, a polysilicon film 6 is grown to a thickness of about 200 nm on this, and then phosphorus is diffused in a POCl ₃ atmosphere to form an N ⁺ diffusion layer 25 which becomes a collector region of the NPN bipolar transistor.

Next, as shown in FIG. 3B, the first photoresist 7 is patterned to selectively remove the polysilicon film 6 in the NMOS transistor region, and the NMOS is then removed.
The gate electrode 8N of the transistor is formed. At this time, the first photoresist 7 and the PMOS transistor region N
It covers the PN bipolar transistor region. Then, using the first photoresist 7 as a mask, phosphorus ions are implanted under the conditions of energy of 40 KeV and dose amount of 3.0 × 10 ¹³ cm ^-2 to form a low concentration N ⁻ diffusion layer 9N of the source / drain region 8N of the NMOS transistor. To do.

Next, as shown in FIG. 1C, the second photoresist 10 is patterned to selectively remove the polysilicon film 6 in the PMOS transistor region, and the PMO is removed.
The gate electrode 8P of the S transistor and the collector electrode 8B of the NPN bipolar transistor are formed. At this time, the second photoresist 10 covers the NMOS transistor region. Then, using the second photoresist 10 as a mask, boron ions, for example, with an energy of 30 Ke
^{Implanted under} the conditions of V and dose of about 3.0 × 10 ¹³ cm ^-2 , PMO
A low concentration P ⁻ diffusion layer 9P in the source / drain region of the S transistor is formed. At the same time, the base region 26 of the NPN bipolar transistor is formed.

After that, although not shown, in the MOS transistor portion, sidewalls are formed on both side surfaces of the gate electrode, high-concentration diffusion layers in the source / drain regions are formed, and then a high-concentration base region in the bipolar transistor portion is formed. Diffusion layer and emitter diffusion layer regions are formed. Then
After growing a PSG film as an interlayer insulating film, an electrode portion is opened and a wiring process using aluminum is performed to obtain a desired semiconductor device. According to this manufacturing method,
Since the formation of the gate electrode of the MOS transistor and the formation of the source / drain diffusion layer regions can be performed in the same photoresist process, and at the same time the base region of the bipolar transistor can be formed, it is possible to compare with the conventional method. Therefore, it is possible to reduce the number of the two photoresist processes, facilitate the manufacturing, and shorten the manufacturing time.

[0014]

As described above, according to the present invention, the gate electrode and the source / drain region of the reverse conductivity type MOS transistor are formed with the formation region of the one conductivity type MOS transistor covered with the first photoresist. Then, the gate electrode and the source / drain regions of the one conductivity type MOS transistor are formed in a state where the formation region of the opposite conductivity type MOS transistor is covered with the second photoresist.
When manufacturing a semiconductor device having an OS structure, M
The formation of the gate electrode of the OS transistor and the formation of the source / drain regions can be performed in the same photoresist process, and one photoresist process can be omitted as compared with the conventional manufacturing method, and the manufacturing is easy. There is an effect that it is possible to reduce the production time and the manufacturing time.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a first embodiment of a method of manufacturing a semiconductor device of the present invention in the order of manufacturing steps.

FIG. 2 is a sectional view showing a second embodiment of the present invention in the order of manufacturing steps.

FIG. 3 is a cross-sectional view showing a method of manufacturing a conventional semiconductor device in the order of steps.

[Explanation of symbols]

 1, 21 P-type silicon substrate 2 P well 3 N well 6 polysilicon film 7 first photoresist 8N, 8P gate electrode 9N, 9P source / drain region 10 second photoresist

Claims (1)

[Claims] 1. A step of forming one conductivity type region and an opposite conductivity type region on a semiconductor substrate, a step of forming a conductive film on the surface of the semiconductor substrate via a gate insulating film, and a first photoresist. Patterning is performed by leaving only the conductive type MOS transistor forming region and the reverse conductive type MOS transistor gate forming region to form a gate electrode of the reverse conductive type MOS transistor; and using the first photoresist as a mask, the reverse conductive type is formed. Reverse conductivity type MO by implanting impurities
The step of forming the source / drain regions of the S-transistor and the patterning of the second photoresist by leaving the second photoresist only in the reverse-conductivity type MOS transistor forming region and the gate-forming region of the one-conducting type MOS transistor are performed.
Forming a gate electrode of a transistor;
And a step of forming a source / drain region of a one-conductivity type MOS transistor by using the photoresist as a mask and implanting one-conductivity type impurities.