KR0167667B1 - Semiconductor manufacturing method - Google Patents
Semiconductor manufacturing method Download PDFInfo
- Publication number
- KR0167667B1 KR0167667B1 KR1019950037736A KR19950037736A KR0167667B1 KR 0167667 B1 KR0167667 B1 KR 0167667B1 KR 1019950037736 A KR1019950037736 A KR 1019950037736A KR 19950037736 A KR19950037736 A KR 19950037736A KR 0167667 B1 KR0167667 B1 KR 0167667B1
- Authority
- KR
- South Korea
- Prior art keywords
- silicon film
- film
- semiconductor manufacturing
- transistor
- mos
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 22
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 22
- 239000010703 silicon Substances 0.000 claims abstract description 22
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 20
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 20
- 230000008021 deposition Effects 0.000 claims abstract description 6
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 16
- 229910008484 TiSi Inorganic materials 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 7
- 150000002500 ions Chemical class 0.000 claims description 6
- 238000005245 sintering Methods 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 3
- 230000009036 growth inhibition Effects 0.000 abstract description 3
- 230000010354 integration Effects 0.000 abstract description 3
- 238000005468 ion implantation Methods 0.000 description 5
- 239000012535 impurity Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 238000005280 amorphization Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/0172—Manufacturing their gate conductors
- H10D84/0174—Manufacturing their gate conductors the gate conductors being silicided
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
- H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
- H10D84/85—Complementary IGFETs, e.g. CMOS
- H10D84/859—Complementary IGFETs, e.g. CMOS comprising both N-type and P-type wells, e.g. twin-tub
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
본 발명은 적어도 하나의 트렌지스터를 구비하는 반도체소자에서, 상기 트렌지스터의 게이트 전극 상부 표면 및 소오스/드레인 상부 표면에 실리사이드막을 형성하기 위한 반도체 제조 방법에 있어서; 기형성된 트렌지스터의 게이트 전극 및 소오스/드레인 상부 표면에 선택적 증착으로 실리콘막을 형성하는 단계; 상기 실리콘막을 비정질화하는 단계; 상기 비정질화된 실리콘막 상에 실리사이드막을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 제조 방법에 관한 것으로, 본 발명은 N-MOS 지역의 As에 의한 실리사이드 성장 억제를 배제하여 낮은 면저항을 가지며, 소자의 고집적화가 가능하고, N-MOS 지역과 P-MOS 지역의 실리사이드막을 균일한 두께로 형성하여 제조 공정이 용이함을 가져오는 효과가 있다.A semiconductor manufacturing method for forming a silicide film on a gate electrode upper surface and a source / drain upper surface of a transistor in a semiconductor device having at least one transistor; Forming a silicon film by selective deposition on the gate electrode and the source / drain top surface of the preformed transistor; Amorphizing the silicon film; The present invention relates to a semiconductor manufacturing method comprising forming a silicide film on the amorphous silicon film, the present invention has a low sheet resistance by excluding silicide growth inhibition by As in the N-MOS region, High integration can be achieved, and the silicide films in the N-MOS region and the P-MOS region are formed to have a uniform thickness, thereby facilitating the manufacturing process.
Description
제1a도 내지 1d도는 본 발명의 일실시예에 따른 CMOS 제조 공정도.1a to 1d is a CMOS manufacturing process diagram according to an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 실리콘 기판 2 : 필드산화막1 silicon substrate 2 field oxide film
3 : P웰 4 : N웰3: P well 4: N well
5 : 게이트 산화막 6 : 게이트 전극5 gate oxide film 6 gate electrode
7 ; 스페이서 8 : N-MOS의 소오스/드레인 접합7; Spacer 8: Source / drain junction of N-MOS
9 : P-MOS의 소오스/드레인 접합 10 : 비도핑된 실리콘막9 source / drain junction of P-MOS 10 undoped silicon film
11 : 비정질화된 실리콘막 12 : TiSi2 11: amorphous silicon film 12: TiSi 2
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 모스펫(이하, MOSFET라 칭한다)이 고집적화되어 감에 따라 게이트 전극과 소오스/드레인 지역에서 좀더 낮은 면 저항(Sheet Resistance, 전체적으로 직렬 저항이라고 함)을 얻기 위한 반도체 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and in particular, as MOSFETs (hereinafter referred to as MOSFETs) become highly integrated, lower surface resistance (Sheet Resistance, generally referred to as series resistance) in the gate electrode and source / drain regions is increased. It relates to a semiconductor manufacturing method for obtaining.
종래에는 반도체 소자를 구성하는 MOSFET의 게이트 및 소오스/드레인 지역 상에 실리사이드(Silicide)막을 형성하여 낮은 면저항을 얻고 있으며, 그 제조공정을 CMOS 제조 방법을 통해 간단히 살펴보면 다음과 같다.Conventionally, a silicide film is formed on gate and source / drain regions of a MOSFET constituting a semiconductor device to obtain a low sheet resistance. The manufacturing process thereof is briefly described through a CMOS manufacturing method.
먼저, 통상적인 방법으로 소자분리가 이루어진 기판 상에 N-MOS를 위한 P웰 및 P-MNO를 위한 N웰을 각각 형성하고, 각각의 웰 지역에 게이트 전극을 형성한다.First, a P well for an N-MOS and an N well for a P-MNO are formed on a substrate having device isolation in a conventional manner, and a gate electrode is formed in each well region.
그 다음, N-MOS 지역의 소오스/드레인 접합 형성을 위한 As 이온 주입, P-MOS 지역의 소오스/드레인 접합 형성을 위한 BF2이온주입을 각각 실시한 상태에서, 전체구조 상부에 실리사이드막 형성을 위한 Ti막 증착 및 제1신터링(Sintering)과 선택작인 Ti 식각 및 제2신터링을 각각 차례로 실시하여,N-MOS와 P-MOS의 게이트 및 소오스/드레인 상에 실리사이드막인 TiSi2를 형성하고 있다.Next, with the As ion implantation for forming the source / drain junction in the N-MOS region and the BF 2 ion implantation for forming the source / drain junction in the P-MOS region, the silicide layer was formed on the entire structure. Ti film deposition, first sintering, and optional Ti etching and second sintering are sequentially performed to form TiSi 2 , a silicide film, on gates and sources / drains of N-MOS and P-MOS, respectively. have.
그러나, 소자가 점차 고집착화 되어감에 따라, 원하는 낮은 저항을 얻기에는 한계가 있었다.However, as the device became increasingly highly integrated, there was a limit to obtaining the desired low resistance.
즉, 반도체 소자 제조시, N-MOS 지역의 소오스/드레인 영역의 불순물인 As은 실리사이드막(통상적으로 TiSi2) 형성을 억제하여 낮은 면저항을 얻기 힘들고, CMOS와 같이 N-MOS와 P-MOS가 동시에 형성되는 경우, P-MOS 지역의 소오스/드레인 영역의 불순물인 BF2는 TiSi2의 형성을 억제하지 않으므로, N-MOS 지역과 P-MOS 지역의 실리사이드막의 두께가 제조 공정상 균일화될 수 없기 때문에 제조 공정상 어려움이 있게 된다.That is, in the fabrication of semiconductor devices, As, which is an impurity in the source / drain regions of the N-MOS region, suppresses the formation of the silicide film (typically TiSi 2 ), so that it is difficult to obtain low sheet resistance. When formed simultaneously, BF 2 , an impurity in the source / drain regions of the P-MOS region, does not inhibit the formation of TiSi 2 , so that the thicknesses of the silicide films in the N-MOS region and the P-MOS region cannot be uniformized in the manufacturing process. This causes difficulties in the manufacturing process.
그리고, 좁은 실리콘 라인에는 As의 반응(reaction)에 기인하는 TiSi2성장 억제 때문에 고집적화 되는데는 한계점이 있다.In addition, narrow silicon lines have a limitation in that they are highly integrated due to TiSi 2 growth inhibition due to the reaction of As.
본 발명은 상기 제반 문제점을 해결하기 위하여 안출된 것으로, 낮은 면저항을 가져와 고집적화가 가능한 반도체 소자 방법을 제공함을 그 목적으로 한다.Disclosure of Invention The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device method capable of high integration by bringing low sheet resistance.
또한, 본 발명의 다른 목적은 N-MOS 지역과 P-MOS 지역의 실리사이드막을 균일한 두께로 형성하여 제조 공정이 용이함을 가져오는 반도체 소자 제조 방법을 제공하는데 있다.In addition, another object of the present invention is to provide a method for manufacturing a semiconductor device that makes the manufacturing process easy by forming silicide films in the N-MOS region and the P-MOS region with a uniform thickness.
상기 목적을 달성하기 위하여 본 발명은 적어도 하나의 트렌지스터를 구비하는 반도체 소자에서, 상기 트렌지스터의 게이트 전극 상부 표면 및 소오스/드레인 상부 표면에 실리사이드막을 형성하기 위한 반도체 제조 방법 에 있어서;기형성된 트렌지스터의 게이트 전극 및 소오스/드레인 상부표면에 선택적 증착으로 실리콘막을 형성하는 단계; 상기 실리콘막을 비정질화하는 단계; 및 상기 비정질화된 실리콘막 상의 실리사이드막을 형성하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object, the present invention provides a semiconductor manufacturing method for forming a silicide film on a gate electrode upper surface and a source / drain upper surface of a transistor in a semiconductor device having at least one transistor; a gate of a pre-formed transistor; Forming a silicon film on the electrode and the source / drain top surface by selective deposition; Amorphizing the silicon film; And forming a silicide film on the amorphous silicon film.
상기한 바와 같이 본 발명은 N-MOS 지역의 As에 의한 실리사이드 성장 억제를 배제하기 위하여 게이트 전극과 소오스/드레인에 선택적으로 비도핑된 실리콘막을 증착하는 방법과 예비-비정질화(Pro-amorphization) 방법을 사용하는 것이다.As described above, the present invention provides a method of depositing a selectively undoped silicon film on a gate electrode and a source / drain and a pre-amorphization method to exclude silicide growth inhibition by As in the N-MOS region. Is to use
이하, 첨부된 도면을 참조하여 본발명을 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제1a도 내지 제1d도는 본 발명의 일실시예에 따른 CMOS 제조 공정이다.1A to 1D illustrate a CMOS fabrication process according to an embodiment of the present invention.
먼저, 제1a도는 필드산화막(2)이 형성된 실리콘 기판(1) 상에 N-MOS를 위한 P웰(3) 및 P-MOS를 위한 N웰(4)을 각각 형성하고, 각각의 웰 지역의 소정부위에 게이트 산화막(5) 및 게이트 전극(6)을 형성한 다음, 게이트 전극(6) 측벽에 스페이서(7)를 형성한 상태이다.First, FIG. 1A shows a P well 3 for an N-MOS and an N well 4 for a P-MOS, respectively, on a silicon substrate 1 having a field oxide film 2 formed thereon. After the gate oxide film 5 and the gate electrode 6 are formed at predetermined portions, the spacer 7 is formed on the sidewalls of the gate electrode 6.
이어서, 제1b도와 같이 N-MOS 지역에 As 이온주입을 실시하여 N+영역인 N-MOS의 소오스/드레인 접합(8)을 형성하고, P-MOS 지역의 BF2이온주입을 실시하여 P-MOS의 소오스/드레인 접합(9)을 형성한 다음, 불순물이 주입되지 않은 실리콘막, 즉 비도핑된 실리콘막(10)을 게이트 전극(6) 상부와 N-MOS 및 P-MOS의 소오스/드레인 접합(8,9) 상부에 선택적으로 형성한다.Subsequently, As ion implantation is performed in the N-MOS region as shown in FIG. 1b to form a source / drain junction 8 of N-MOS which is an N + region, and BF 2 ion implantation in the P-MOS region is performed to form P-. After the source / drain junction 9 of MOS is formed, a silicon film that is not implanted with impurities, that is, an undoped silicon film 10, is placed over the gate electrode 6 and the source / drain of N-MOS and P-MOS. It is formed selectively on the junction (8, 9).
이때, 비도핑된 실리콘막(10)의 선택적 증착법은 화학기상증착(CVD) 시스템을 이용하여 600℃ 내지 700℃ 정도의 낮은 온도에서 Si2H6가스의 플로우율(Flow Rate)을 조정하여 형성하며, 두께는 200Å 내지 300Å으로 형성한다.At this time, the selective deposition of the undoped silicon film 10 is formed by adjusting the flow rate of Si 2 H 6 gas at a low temperature of 600 ℃ to 700 ℃ using a chemical vapor deposition (CVD) system And, the thickness is formed to 200 ~ 300Å.
이어서, 제1c도와 같이 상기 비도핑된 실리콘막(10)에 이온주입(11)을 실시하여 비도핑된 실리콘막을 비정질화(10a) 한다.Subsequently, as illustrated in FIG. 1C, ion implantation 11 is performed on the undoped silicon film 10 to amorphousize the undoped silicon film 10a.
이때, 주입되는 이온은 As 이온으로 농도는 3×1014cm-2정도이다.At this time, the implanted ions are As ions, the concentration is about 3 × 10 14 cm -2 .
제1d도와 같이 실리사이드막 형성을 위해, 전체구조 상부에 Ti막을 3500Å 정도 증착하고 690℃의 온도에서 30초 정도 제1신터링을 실시하고, 선택적인 Ti식각을 실시한 후, 840℃의 온도에서 10초 정도 제2신터링을 실시하여, N-MOS와 P-MOS의 게이트 전극(6) 및 소오스/드레인 접합(8,9) 상에 실리사이드막인 TiSi2(12)를 형성한다.In order to form the silicide film as shown in FIG. 1D, a Ti film is deposited on the entire structure at about 3500Å and subjected to first sintering at a temperature of 690 ° C. for about 30 seconds, followed by selective Ti etching, and then at 10 ° C. Second sintering is performed for about a second to form TiSi 2 (12) as a silicide film on the gate electrodes 6 and the source / drain junctions 8 and 9 of the N-MOS and P-MOS.
본 발명은 상기 일실시예와 같이 N-MOS 및 P-MOS로 이루어지는 CMOS 및 그 밖의 다른 반도체 소자에 적용될 수 있으며, As 이온에 의해 소오스/드레인 접합층이 형성되는 N-MOS만에만 적용될 수 있다.The present invention can be applied to CMOS and other semiconductor devices composed of N-MOS and P-MOS as in the above embodiment, and can be applied only to N-MOS in which a source / drain junction layer is formed by As ions. .
이상, 상기 설명한 바와 같이 이루어지느 본 발명은 N-MOS 지역의 As에 의한 실리사이드 성정억제를 배제하여 낮은 면저항을 가지며, 소자의 고집적화가 가능하고, N-MOS 지역과 P-MOS 지역의 실리사이드막을 균일한 두께로 형성하여 제조 공정의 용이함을 가져오는 효과가 있다.As described above, the present invention has a low sheet resistance by suppressing silicide stabilities due to As in the N-MOS region, enables high integration of the device, and makes the silicide films in the N-MOS region and the P-MOS region uniform. Forming to a thickness has the effect of bringing the ease of the manufacturing process.
Claims (11)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950037736A KR0167667B1 (en) | 1995-10-27 | 1995-10-27 | Semiconductor manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950037736A KR0167667B1 (en) | 1995-10-27 | 1995-10-27 | Semiconductor manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR970023878A KR970023878A (en) | 1997-05-30 |
| KR0167667B1 true KR0167667B1 (en) | 1999-02-01 |
Family
ID=19431684
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950037736A KR0167667B1 (en) | 1995-10-27 | 1995-10-27 | Semiconductor manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR0167667B1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20000066155A (en) * | 1999-04-13 | 2000-11-15 | 황인길 | Shallow junction &silicide forming method of semiconductor devices |
-
1995
- 1995-10-27 KR KR1019950037736A patent/KR0167667B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR970023878A (en) | 1997-05-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2978736B2 (en) | Method for manufacturing semiconductor device | |
| US6365472B1 (en) | Semiconductor device and method of manufacturing the same | |
| US6087234A (en) | Method of forming a self-aligned silicide MOSFET with an extended ultra-shallow S/D junction | |
| JPH04225529A (en) | Improved method of fabricating integrated circuit structures with lightly doped drains (LDDs) | |
| JP2509518B2 (en) | Titanium silicide contact manufacturing method | |
| EP0459398B1 (en) | Manufacturing method of a channel in MOS semiconductor devices | |
| JP3014030B2 (en) | Method for manufacturing semiconductor device | |
| JPH04305978A (en) | Manufacturing method of power MOS semiconductor device | |
| KR0167667B1 (en) | Semiconductor manufacturing method | |
| JPH03227516A (en) | Manufacture of semiconductor device | |
| US6780700B2 (en) | Method of fabricating deep sub-micron CMOS source/drain with MDD and selective CVD silicide | |
| JPH10125919A (en) | Method for forming electrode of semiconductor element | |
| JPH0738113A (en) | Manufacture of thin film transistor | |
| JP3211340B2 (en) | Method for manufacturing thin film transistor | |
| JP2711187B2 (en) | Method for manufacturing semiconductor device | |
| JP3371631B2 (en) | Semiconductor device and manufacturing method thereof | |
| JPS6074663A (en) | Manufacture of complementary type semiconductor device | |
| KR100214460B1 (en) | Method of manufacturing thin film transistor | |
| KR100196521B1 (en) | Method of manufacturing thin film transistor | |
| JP2973479B2 (en) | Thin film transistor device | |
| JPH0555577A (en) | Manufacture of thin film transistor | |
| KR940000988B1 (en) | Semiconductor Device Double Gate Manufacturing Method | |
| JPS6097662A (en) | Manufacture of semiconductor device | |
| JPH06204418A (en) | Semiconductor device and manufacture thereof | |
| KR100256803B1 (en) | Method for forming shallow junction in semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| PA0109 | Patent application |
Patent event code: PA01091R01D Comment text: Patent Application Patent event date: 19951027 |
|
| PA0201 | Request for examination |
Patent event code: PA02012R01D Patent event date: 19951027 Comment text: Request for Examination of Application |
|
| PG1501 | Laying open of application | ||
| E701 | Decision to grant or registration of patent right | ||
| PE0701 | Decision of registration |
Patent event code: PE07011S01D Comment text: Decision to Grant Registration Patent event date: 19980629 |
|
| GRNT | Written decision to grant | ||
| PR0701 | Registration of establishment |
Comment text: Registration of Establishment Patent event date: 19980929 Patent event code: PR07011E01D |
|
| PR1002 | Payment of registration fee |
Payment date: 19980929 End annual number: 3 Start annual number: 1 |
|
| PG1601 | Publication of registration | ||
| PR1001 | Payment of annual fee |
Payment date: 20010817 Start annual number: 4 End annual number: 4 |
|
| PR1001 | Payment of annual fee |
Payment date: 20020820 Start annual number: 5 End annual number: 5 |
|
| PR1001 | Payment of annual fee |
Payment date: 20030814 Start annual number: 6 End annual number: 6 |
|
| PR1001 | Payment of annual fee |
Payment date: 20040820 Start annual number: 7 End annual number: 7 |
|
| PR1001 | Payment of annual fee |
Payment date: 20050822 Start annual number: 8 End annual number: 8 |
|
| PR1001 | Payment of annual fee |
Payment date: 20060818 Start annual number: 9 End annual number: 9 |
|
| PR1001 | Payment of annual fee |
Payment date: 20070827 Start annual number: 10 End annual number: 10 |
|
| PR1001 | Payment of annual fee |
Payment date: 20080820 Start annual number: 11 End annual number: 11 |
|
| PR1001 | Payment of annual fee |
Payment date: 20090828 Start annual number: 12 End annual number: 12 |
|
| FPAY | Annual fee payment |
Payment date: 20100825 Year of fee payment: 13 |
|
| PR1001 | Payment of annual fee |
Payment date: 20100825 Start annual number: 13 End annual number: 13 |
|
| LAPS | Lapse due to unpaid annual fee | ||
| PC1903 | Unpaid annual fee |
Termination category: Default of registration fee Termination date: 20120809 |