[go: up one dir, main page]

JPH03268351A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPH03268351A
JPH03268351A JP2066683A JP6668390A JPH03268351A JP H03268351 A JPH03268351 A JP H03268351A JP 2066683 A JP2066683 A JP 2066683A JP 6668390 A JP6668390 A JP 6668390A JP H03268351 A JPH03268351 A JP H03268351A
Authority
JP
Japan
Prior art keywords
semiconductor device
chip
bed
chips
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2066683A
Other languages
English (en)
Other versions
JPH0777258B2 (ja
Inventor
Yoichi Hiruta
陽一 蛭田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2066683A priority Critical patent/JPH0777258B2/ja
Priority to US07/670,270 priority patent/US5138433A/en
Publication of JPH03268351A publication Critical patent/JPH03268351A/ja
Publication of JPH0777258B2 publication Critical patent/JPH0777258B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5387—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0655—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/2401—Structure
    • H01L2224/24011—Deposited, e.g. MCM-D type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/2401—Structure
    • H01L2224/2402—Laminated, e.g. MCM-L type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01042—Molybdenum [Mo]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 ［発明の目的］ （産業上の利用分野） 本発明は、複数の半導体チップを同一のパッケージに実
装した半導体装置（マルチチップパッケージ）に関する
。
（従来の技術） 従来のマルチチップパッケージを第８図、第９図に示す
。即ち第８図の場合、チップ１１は、Ｆ　ｅ−４２ｖｔ
％Ｎｉアロイ等のベッド１２上にアルミナフィルム１３
．Ａｉ）フィルム１４を介して実装され、チップ間等の
配線は、アルミナ１３上のＡｐ配線１４により、ボンデ
ィングワイヤ１５を用いてなされていた。１６はベッド
１２と同材質のリード、１７はモールド用プラスチック
である。
また第９図では、バンブ２１によりチップ（例えばＬＳ
Ｉメモリ用）２２を配線基板（ベッド）２３１．２３２
に実装していた。この場合、チ・ンブ２２のＳｔ基板は
パッケージを構成する部材とは、直接接していないこと
になる。第９図中２４はＡｉ＋フィン、２５は高熱伝導
接着剤、２６はリード、２７はムライトフランジ、２８
はアルミナキャップ、２９は封止用接着剤、３０は封止
用接着剤である。
（発明が解決しようとする課８） 第８図に示した従来例にあっては、チップ１１をＡＩ！
フィルム１４及びアルミナフィルム１３を介してベッド
１２上に実装しているが、プラスチック１７でモールド
され、ベッド１２は、アルミナ１３があるため、直接外
へ引き出されていないので、放熱特性が悪い。
第９図に示した従来例にあっては、べ・ンド２３１．２
３２からＡｇフィン２４までの熱伝達特性は向上してい
るものの、ＬＳＩチップ２２とベッド２３１がバンブに
より接続されているため、チップ２２からの放熱特性は
改善されていない。
この様に従来例では、同一パッケージに複数のチップを
搭載した場合に、増加する発熱量に対する対策が不充分
であり、チップ温度の上昇をまねき、回路動作に不良を
引き起こす。
本発明は、同一パッケージに複数のチップを搭載した場
合、問題となる放熱特性を改善することが目的である。
［発明の構成］ （課題を解決するための手段と作用） 本発明は、複数の半導体チップを同一のパッケージに実
装した半導体装置において、前記チップがベッドまたは
パッケージ基板に直接接着されていることを特徴とする
半導体装置である。
即ち本発明では、チップ裏面をベッド又は基板に直接接
着することにより、放熱特性を向上させたものである。
（実施例） 第１図に本発明の第１実施例を示す。この実施例では、
半導体チップ４１の裏面を直接ベッド４２に接着してい
る。チップ間等の配線は、絶縁性の高い例えばポリイミ
ド４３上に形成したＣｕ配線４４を介してボンディング
ワイヤー４５により行なっている。ベッド４２の材質と
しては、４２７０イ（鉄、ニッケル系合金）、Ｃｕ等で
よい。チップ４１とベッド４２との接着は、ポリイミド
等の絶縁性接着剤とか導電性接着剤等で行なってもよい
。第１図の構成は、その後例えば有機性樹脂で封止され
る。
第１図のようにすれば、チップ４１とベッド４２との間
に、第８図のアルミナフィルム１３等が介在されないた
め、両者間の放熱性が良くなる。
第２図は実装方法をセラミックパッケージ５１に適用し
た場合の第２の実施例の断面図である。
チップ４１とセラミックパッケージ５１との間には、ベ
ッド４２があっても、なくてもよい。第２図中５２は放
熱フィン、５３は配線、５４はビン（配線端子）、５５
はリッドである。なお、上記実装方法をセラミックパッ
ケージによらず、プラスチックパッケージに封止する場
合は、樹脂剥離を防止するため、ベッドにアンカーホー
ルを設けるとよい。
第３実施例を第３図に示す。この実施例では、チップ間
等の接続をＴ　Ａ　Ｂ　（Ｔａｐｅ　Ａｕｔｏｍａｔｅ
ｄＢｏｎｄｉｎｇ）により行なっている。即ちベッド４
２にポリイミド４３を塗布し、Ｃｕの配線パターン４４
及び電極６１を形成した後（第３図（ａ））、チップ４
１をベッド４２に直接接着しく第３図（ｂ））、テープ
ボンディングによりテープ６２上の配線パターン６３を
用いて、チップ４１上の電極６４、ポリイミド上の配線
パターン電極４５間とか、チップと外部導出リード間等
の配線を行なう（第３図（Ｃ））。
第４図に示す第４の実施例では、第１．第３の実施例と
は異なり、ポリイミド４３上にはＣｕ配線を形成せず、
絶縁性テープ７１の下面に配線パターン７２を形成して
いる。本実施例ではチップ４１をベッド４２に直接接着
後、ポリイミド４３を平坦に４００〜５００ρはど塗布
しく第４図（ａ））、チップ上パッド部のバンブ部６４
のみポリイミド４３を除去しく第４図（ｂ））　、Ｃｕ
配線７２が形成されたボンディング用テープ７１の圧着
により、チップ間接続を行なう（第４図（Ｃ））。
第５の実施例を第５図に示す。本実施例では、チップ４
１付近はプラスチック８１で封止される。
即ちチップ４１をアルミナ基板８２に直接接着し、これ
とリードのインナーリード部８３が接してモールドされ
ている。プラスチック８１の封止の場合、樹脂剥離を防
止するため、基板８２にアンカーホールを設けるとよい
。
第６の実施例を第６図に示す。この実施例では、基板９
１には、熱伝導性の良い例えばＡＪＮを用い、基板９１
の両面にチップ４１が実装されており、インナーリード
８３で基板９１をはさみ込んでいる。
上述した各実施例では、ベッド４２またはこれと同等の
役目をするアルミナ基板９１、パッケージ基板５１等に
チップ４１を直接接着したため、チップ−ベッド又は基
板間の熱抵抗の減少と放熱面積の拡大により、半導体チ
ップからパッケージ表面までの熱抵抗を大幅に減らすこ
とができた。
また、第５，６図に示す構造を採った場合、チップから
ベッドまたは基板を経てリードへ熱が伝わる経過が形成
されるため、熱抵抗の低減にさらに効果がある。
第７図に、従来の熱抵抗と本発明を適用したパッケージ
の熱抵抗を示す。パッケージには放熱フィンはつけてお
らず、無風状態で測定を行った。
図から明らかな様に、本発明により、熱抵抗は従来より
３０〜５０％改善されている。
またＴＡＢによりチップ間配線を行った場合、特に第４
の実施例では、チップ間隔を従来の半分程度に減らすこ
とができ、実装密度の向上の点がらも効果がある。
なお、本発明は上記実施例に限られず、種々の応用が可
能である。例えば、本発明はベッド、パッケージ等の材
質を実施例で述べたものに限定するものではない。また
例えばＴＡＢ配線を用いた場合、全部をＴＡＢとしなく
ても、一部のみでもよい。
〔発明の効果］ 以上説明した如く本発明によれば、放熱効果に優れたマ
ルチチップパッケージ型半導体装置が提供できるもので
ある。
【図面の簡単な説明】
第１図は本発明の第１実施例の要部断面図、第２図は本
発明の第２実施例の断面図、第３図。 第４図は本発明の第３．第４実施例の製造工程図、第５
図は本発明の第５実施例の断面図、第６図は本発明の第
６実施例の要部の斜視図、第７図は上記実施例の効果を
示す特性図、第８図、第９図は従来装置の断面図である
。 ４１・・・チップ、４２・・・ベッド、４３・・・ポリ
イミド、４４・・・配線パターン、４５・・・ボンディ
ングワイヤ、５１・・・セラミックパッケージ、５２・
・・放熱ファン、６１．６４・・・電極、６２・・・Ｔ
ＡＢ用テープ、７１・・・テープ、７２・・・配線パタ
ーン、８１・・・封止用プラスチック、８２・・・アル
ミナ基板、８３・・・インナーリード、９１・・・基板
。

Claims (12)

    【特許請求の範囲】
  1. （１）複数の半導体チップを同一のパッケージに実装し
    た半導体装置において、前記チップがベッドまたはパッ
    ケージ基板に直接接着されていることを特徴とする半導
    体装置。
  2. （２）前記複数の半導体チップ間に電気絶縁性の高い樹
    脂が充填されていることを特徴とする請求項１に記載の
    半導体装置。
  3. （３）前記チップが接着された基板がリード端子のイン
    ナーリード部と接していることを特徴とする請求項１ま
    たは２に記載の半導体装置。
  4. （４）前記充填樹脂上に形成された配線パターンを介し
    て、配線がなされていることを特徴とする請求項２に記
    載の半導体装置。
  5. （５）前記配線パターンとチップ間の配線の一部または
    全部がボンディングワイヤーでなされていることを特徴
    とする請求項４に記載の半導体装置。
  6. （６）前記配線パターンとチップ間の配線の一部または
    全部がＴＡＢ（ＴａｐｅＡｕｔｏｍａｔｅｄＢｏｎｄｉ
    ｎｇ）でなされていることを特徴とする請求項４に記載
    の半導体装置。
  7. （７）前記チップ間、及びチッとプ外部リードとの接続
    がＴＡＢによりなされていることを特徴とする請求項４
    に記載の半導体装置。
  8. （８）前記半導体チップがベッドまたは基板両面に実装
    されていることを特徴とする請求項１ないし７のいずれ
    か１項に記載の半導体装置。
  9. （９）前記半導体チップが実装されているベッドまたは
    パッケージ基板が絶縁性で、これがインナーリードの一
    部によりはさみ込まれていることを特徴とする請求項８
    に記載の半導体装置。
  10. （１０）前記半導体チップが有機性樹脂により封止され
    ていることを特徴とする請求項１ないし９のいずれか１
    項に記載の半導体装置。
  11. （１１）前記半導体チップがセラミックパッケージ中に
    封止されていることを特徴とする請求項１ないし９のい
    ずれか１項に記載の半導体装置。
  12. （１２）前記パッケージ表面に放熱用フィンが取り付け
    られていることを特徴とする請求項１１に記載の半導体
    装置。
JP2066683A 1990-03-16 1990-03-16 半導体装置 Expired - Lifetime JPH0777258B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2066683A JPH0777258B2 (ja) 1990-03-16 1990-03-16 半導体装置
US07/670,270 US5138433A (en) 1990-03-16 1991-03-15 Multi-chip package type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2066683A JPH0777258B2 (ja) 1990-03-16 1990-03-16 半導体装置

Publications (2)

Publication Number Publication Date
JPH03268351A true JPH03268351A (ja) 1991-11-29
JPH0777258B2 JPH0777258B2 (ja) 1995-08-16

Family

ID=13322976

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2066683A Expired - Lifetime JPH0777258B2 (ja) 1990-03-16 1990-03-16 半導体装置

Country Status (2)

Country Link
US (1) US5138433A (ja)
JP (1) JPH0777258B2 (ja)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5438216A (en) * 1992-08-31 1995-08-01 Motorola, Inc. Light erasable multichip module
US5422514A (en) * 1993-05-11 1995-06-06 Micromodule Systems, Inc. Packaging and interconnect system for integrated circuits
US5380956A (en) * 1993-07-06 1995-01-10 Sun Microsystems, Inc. Multi-chip cooling module and method
US5688716A (en) 1994-07-07 1997-11-18 Tessera, Inc. Fan-out semiconductor chip assembly
US6848173B2 (en) * 1994-07-07 2005-02-01 Tessera, Inc. Microelectric packages having deformed bonded leads and methods therefor
JP3123638B2 (ja) * 1995-09-25 2001-01-15 株式会社三井ハイテック 半導体装置
US6468638B2 (en) 1999-03-16 2002-10-22 Alien Technology Corporation Web process interconnect in electronic assemblies
US6982478B2 (en) * 1999-03-26 2006-01-03 Oki Electric Industry Co., Ltd. Semiconductor device and method of fabricating the same
US6636334B2 (en) * 1999-03-26 2003-10-21 Oki Electric Industry Co., Ltd. Semiconductor device having high-density packaging thereof
JP3576030B2 (ja) * 1999-03-26 2004-10-13 沖電気工業株式会社 半導体装置及びその製造方法
US6606247B2 (en) 2001-05-31 2003-08-12 Alien Technology Corporation Multi-feature-size electronic structures
US7218527B1 (en) * 2001-08-17 2007-05-15 Alien Technology Corporation Apparatuses and methods for forming smart labels
US7214569B2 (en) 2002-01-23 2007-05-08 Alien Technology Corporation Apparatus incorporating small-feature-size and large-feature-size components and method for making same
US7253735B2 (en) * 2003-03-24 2007-08-07 Alien Technology Corporation RFID tags and processes for producing RFID tags
DE102004025684B4 (de) 2004-04-29 2024-08-22 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Verfahren zum Ausbilden einer Kontaktstruktur zur elektrischen Kontaktierung eines optoelektronischen Halbleiterchips
US7688206B2 (en) 2004-11-22 2010-03-30 Alien Technology Corporation Radio frequency identification (RFID) tag for an item having a conductive layer included or attached
US7690096B1 (en) * 2008-09-19 2010-04-06 Dreamwell, Ltd. Method of manufacturing an aged mattress assembly

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6292653U (ja) * 1985-11-29 1987-06-13
JPS63131561A (ja) * 1986-11-18 1988-06-03 インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン 電子パツケージ

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4330790A (en) * 1980-03-24 1982-05-18 National Semiconductor Corporation Tape operated semiconductor device packaging
US4729010A (en) * 1985-08-05 1988-03-01 Hitachi, Ltd. Integrated circuit package with low-thermal expansion lead pieces
JPS6230367U (ja) * 1985-08-07 1987-02-24
JPS63107149A (ja) * 1986-10-24 1988-05-12 Hitachi Ltd マルチチツプモジユ−ル
JPS63149191A (ja) * 1986-12-15 1988-06-21 日立マクセル株式会社 Ｉｃカ−ド
JP2585006B2 (ja) * 1987-07-22 1997-02-26 東レ・ダウコーニング・シリコーン株式会社 樹脂封止型半導体装置およびその製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6292653U (ja) * 1985-11-29 1987-06-13
JPS63131561A (ja) * 1986-11-18 1988-06-03 インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン 電子パツケージ

Also Published As

Publication number Publication date
US5138433A (en) 1992-08-11
JPH0777258B2 (ja) 1995-08-16

Similar Documents

Publication Publication Date Title
US6630373B2 (en) Ground plane for exposed package
US6956741B2 (en) Semiconductor package with heat sink
TWI419243B (zh) 一種積體電路封裝體及其製造方法
JPH03268351A (ja) 半導体装置
JPH06236946A (ja) ヒートスプレッダ及びリードとプラスチックパッケージとの間の強化接着を有する半導体デバイス
JPH07254668A (ja) 高熱放出用の半導体パッケージ
JPH0613502A (ja) 半導体集積回路チップ
JPH0774282A (ja) 半導体装置
CN103915405B (zh) 半导体器件和制造半导体器件的方法
JPS6042620B2 (ja) 半導体装置の封止体
JPH02307251A (ja) 樹脂封止型半導体装置
TW201308548A (zh) 小基板多晶片記憶體封裝構造
JP2908330B2 (ja) リードフレーム，半導体装置及び半導体装置の製造方法
US6846697B2 (en) Integrated circuit packages and the method for making the same
JPH0338057A (ja) フラグレス・リードフレーム、それを用いたパッケージおよび製法
CN201307589Y (zh) 多平行槽孔的球栅阵列封装构造
JPH05211257A (ja) 半導体集積回路の実装方法
JP3894749B2 (ja) 半導体装置
JPS6329960A (ja) 樹脂封止型半導体装置用リ−ドフレ−ム
JPS6089945A (ja) 封止半導体装置
JP2551349B2 (ja) 樹脂封止型半導体装置
CN100403532C (zh) 散热型球格阵列封装结构
JPH0870087A (ja) リードフレーム
JPH05243326A (ja) 半導体装置
JPH08172142A (ja) 半導体パッケージ及びその製造方法並びに半導体装置

Legal Events

Date Code Title Description
FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20070816

Year of fee payment: 12

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080816

Year of fee payment: 13

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090816

Year of fee payment: 14

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090816

Year of fee payment: 14

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100816

Year of fee payment: 15

EXPY Cancellation because of completion of term
FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100816

Year of fee payment: 15