JPH03102819A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH03102819A JPH03102819A JP24005789A JP24005789A JPH03102819A JP H03102819 A JPH03102819 A JP H03102819A JP 24005789 A JP24005789 A JP 24005789A JP 24005789 A JP24005789 A JP 24005789A JP H03102819 A JPH03102819 A JP H03102819A
- Authority
- JP
- Japan
- Prior art keywords
- tungsten
- silicon substrate
- film
- source electrode
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000004065 semiconductor Substances 0.000 title claims description 4
- 239000000758 substrate Substances 0.000 claims abstract description 29
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 26
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 26
- 239000010703 silicon Substances 0.000 claims abstract description 26
- 229910052751 metal Inorganic materials 0.000 claims abstract description 17
- 239000002184 metal Substances 0.000 claims abstract description 17
- 235000014113 dietary fatty acids Nutrition 0.000 claims abstract description 16
- 229930195729 fatty acid Natural products 0.000 claims abstract description 16
- 239000000194 fatty acid Substances 0.000 claims abstract description 16
- 150000004665 fatty acids Chemical class 0.000 claims abstract description 16
- 238000005245 sintering Methods 0.000 claims abstract description 5
- 239000003960 organic solvent Substances 0.000 claims abstract description 3
- 239000011248 coating agent Substances 0.000 claims abstract 2
- 238000000576 coating method Methods 0.000 claims abstract 2
- 238000000034 method Methods 0.000 claims description 15
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 239000010408 film Substances 0.000 abstract description 34
- 229910052721 tungsten Inorganic materials 0.000 abstract description 26
- 239000010937 tungsten Substances 0.000 abstract description 26
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 abstract description 25
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 14
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 14
- 239000000243 solution Substances 0.000 abstract description 9
- 230000004888 barrier function Effects 0.000 abstract description 7
- WWZKQHOCKIZLMA-UHFFFAOYSA-N octanoic acid Chemical compound CCCCCCCC(O)=O WWZKQHOCKIZLMA-UHFFFAOYSA-N 0.000 abstract description 7
- 239000005380 borophosphosilicate glass Substances 0.000 abstract description 5
- 239000006104 solid solution Substances 0.000 abstract description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 abstract description 3
- CTQNGGLPUBDAKN-UHFFFAOYSA-N O-Xylene Chemical compound CC1=CC=CC=C1C CTQNGGLPUBDAKN-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052799 carbon Inorganic materials 0.000 abstract description 3
- 239000007788 liquid Substances 0.000 abstract description 3
- 239000010409 thin film Substances 0.000 abstract description 3
- 239000008096 xylene Substances 0.000 abstract description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical group [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 229910000676 Si alloy Inorganic materials 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- CSDREXVUYHZDNP-UHFFFAOYSA-N alumanylidynesilicon Chemical compound [Al].[Si] CSDREXVUYHZDNP-UHFFFAOYSA-N 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229910021645 metal ion Inorganic materials 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- YPIFGDQKSSMYHQ-UHFFFAOYSA-N 7,7-dimethyloctanoic acid Chemical compound CC(C)(C)CCCCCC(O)=O YPIFGDQKSSMYHQ-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 description 1
- MEOSMFUUJVIIKB-UHFFFAOYSA-N [W].[C] Chemical compound [W].[C] MEOSMFUUJVIIKB-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000012895 dilution Substances 0.000 description 1
- 238000010790 dilution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 125000002347 octyl group Chemical group [H]C([*])([H])C([H])([H])C([H])([H])C([H])([H])C([H])([H])C([H])([H])C([H])([H])C([H])([H])[H] 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- -1 tungsten octylate Chemical class 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の目的〕
(産業上の利用分野)
本発明は、半導体装置の製造方法に係り、特にショット
キーソース型MOSトランジスタのソース電極の形成に
関する。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, and particularly to the formation of a source electrode of a Schottky source type MOS transistor.
(従来の技術)
従来用いられているショットキーソース型MOSトラン
ジスタとしては、例えば第2図に示すようなものがある
。このタイプのトランジスタでは、通常のMOS型トラ
ンジスタのようにソース・ドレインを形成する拡散層は
なく、ゲート電極1はこれを囲むように形成された酸化
シリコン膜2によって、ソース電極3とシリコン基板5
に対して分離されているのみである。そしてソース電極
3とシリコン基板5とはショットキー障壁を形成し、ゲ
ート電極1に電極が印加されると酸化シリコンs2を介
してシリコン基板表面に反転層が形成されるように構成
されている。(Prior Art) As a conventionally used Schottky source type MOS transistor, there is one shown in FIG. 2, for example. In this type of transistor, there is no diffusion layer that forms the source and drain as in a normal MOS transistor, and the gate electrode 1 is surrounded by a silicon oxide film 2 formed to surround the source electrode 3 and the silicon substrate.
They are only separated from each other. The source electrode 3 and the silicon substrate 5 form a Schottky barrier, and when an electrode is applied to the gate electrode 1, an inversion layer is formed on the surface of the silicon substrate via the silicon oxide s2.
ところが、ゲート電極1の側壁はソース電極3との分離
のために酸化シリコン膜2で覆われている。このため、
この側壁の酸化シリコン膜の厚さの分のすきまbを越え
て反転層が形成されなければソース電極3からドレイン
電極4へ電流を流すことはできない。However, the side walls of the gate electrode 1 are covered with a silicon oxide film 2 for isolation from the source electrode 3. For this reason,
Current cannot flow from the source electrode 3 to the drain electrode 4 unless the inversion layer is formed across the gap b corresponding to the thickness of the silicon oxide film on the sidewall.
つまりこのトランジスタにおいてはすきまbの分、閾値
電圧が大きくなってしまう。In other words, in this transistor, the threshold voltage increases by the gap b.
これを防止する手段として、第3図に示すように、ゲー
ト電極1に隣接するのソース電極形成部のシリコン基板
表面をゲート電極1端縁の下部にまで至るように掘り、
凹部を形成し、この凹部に選択CVD法あるいはCVD
法によりタングステン膜7を埋め込み、このタングステ
ン膜7に対してアルミニウムーシリコン合金等で配線を
行い、ソース電極3とする方法が提案されている。As a means to prevent this, as shown in FIG. 3, the surface of the silicon substrate in the source electrode formation area adjacent to the gate electrode 1 is dug down to the bottom of the edge of the gate electrode 1.
A recess is formed, and selective CVD or CVD is applied to this recess.
A method has been proposed in which a tungsten film 7 is buried by a method, and wiring is formed using an aluminum-silicon alloy or the like on the tungsten film 7 to form the source electrode 3.
しかしながら、このようなCVD法を用いてタングステ
ン膜7をシリコン上に選択的に埋め込む力法では、WF
6とH2を用いた場合、タングステンの成長速度が毎分
数10A程度と非常に遅くまた、タングステン成長時に
タングテンが酸化シリコン膜2とシリコン基板5との界
面に食い込む現象が生じるということが知られている。However, in the force method of selectively embedding the tungsten film 7 on silicon using such a CVD method, the WF
It is known that when 6 and H2 are used, the growth rate of tungsten is very slow, about several tens of amperes per minute, and a phenomenon occurs where tungsten bites into the interface between the silicon oxide film 2 and the silicon substrate 5 during tungsten growth. There is.
一方、上記現象を抑制することが可能なWF8とSiH
4を用いた場合では、選択性のくずれが生じ、シリコン
上にタングステンが形成されない部分がところどころ存
在し、十分な特性を得ることができないという問題があ
った。On the other hand, WF8 and SiH, which can suppress the above phenomenon,
When No. 4 was used, there was a problem that the selectivity deteriorated and there were some parts on the silicon where tungsten was not formed, making it impossible to obtain sufficient characteristics.
(発明が解決しようとする課題)
このように、第2図に示した前者の構造では閾値電圧の
変動をもたらし、第3図に示した後者の改良構造ではゲ
ート電極1の下の空洞が残留して閾値電圧が高くなる他
、配線自体は不良配線となるという問題があった。(Problem to be Solved by the Invention) As described above, the former structure shown in FIG. 2 causes fluctuations in the threshold voltage, and the latter improved structure shown in FIG. 3 leaves a cavity under the gate electrode 1. In addition to increasing the threshold voltage, there is a problem that the wiring itself becomes defective.
また、この空洞の部分では、タングステンがないために
、シリコン基板との間で接合を形成するのはタングステ
ンではなくアルミニウムであり、アルミニウムによるシ
ョットキーコンタクトを形成することになってしまう。Furthermore, since there is no tungsten in this cavity, it is aluminum rather than tungsten that forms the bond with the silicon substrate, resulting in a Schottky contact made of aluminum.
本発明は、前記実情に鑑みてなされたもので、閾値電圧
が低く、信頼性の高いショットキー障壁型MOS}ラン
ジスタを提供することを目的とする。The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a Schottky barrier type MOS transistor having a low threshold voltage and high reliability.
(課題を解決するための手段)
そこで本発明では、ソース電極形成部のシリコン基板表
面をゲート電極端縁の下部まで掘り、四部を形成したの
ち、脂肪酸と金属イオンの化合物である脂肪酸金属を有
機溶剤に溶かした液をシリコン基板表面に塗布し、シリ
コン基板表面に脂肪酸金属を付着させたのち、これを分
解焼結してこの凹部内に金属膜を形成するようにしてい
る。(Means for Solving the Problem) Therefore, in the present invention, the surface of the silicon substrate in the source electrode formation area is dug down to the bottom of the edge of the gate electrode, and after forming four parts, a fatty acid metal, which is a compound of a fatty acid and a metal ion, is A liquid dissolved in a solvent is applied to the surface of the silicon substrate to adhere the fatty acid metal to the surface of the silicon substrate, and then this is decomposed and sintered to form a metal film within the recess.
(作用)
すなわち、この方法は従来の選択CVD法あるいはCV
D法によりタングステン膜を形成することにより凹部を
埋め込む方法に替わり、脂肪酸と金属イオンの化合物で
ある脂肪酸金属を含む溶液を塗布し焼結させることによ
りこの凹部内に金属膜を形成するものである。(Operation) In other words, this method is different from the conventional selective CVD method or CVD method.
Instead of filling the recess by forming a tungsten film using method D, this method forms a metal film in the recess by applying and sintering a solution containing a fatty acid metal, which is a compound of a fatty acid and a metal ion. .
上記方法によれば、脂肪酸金属を含む溶液を塗布するこ
とにより四部にはくまなくこの溶液が充填される。そし
てこの状態で焼結させるため、空洞を生じたりすること
なく完全に凹部を埋め込むことができる上、シリコン基
板と酸化シリコン膜との界面にタングステンが入り込む
のを防止し、信頼性の向上をはかることができる。According to the above method, by applying a solution containing a fatty acid metal, all four parts are filled with the solution. Since it is sintered in this state, it is possible to completely fill the recess without creating a cavity, and it also prevents tungsten from entering the interface between the silicon substrate and silicon oxide film, improving reliability. be able to.
(実施例)
以下、本発明の第1の実施例について、図面を参照しつ
つ詳細に説明する。(Example) Hereinafter, a first example of the present invention will be described in detail with reference to the drawings.
まず、第1図(a)に示すように、シリコン基板5の表
面にゲート酸化膜8として酸化シリコン膜を形成し、さ
らにリンをドープしながら膜厚40000Aのポリシリ
コン膜を堆積し、フォトリソグラフィおよびエッチング
工程によりゲート電極をバターニングし、酸素雰囲気中
で膜厚1000Aの酸化シリコン膜9を形成する。First, as shown in FIG. 1(a), a silicon oxide film is formed as a gate oxide film 8 on the surface of a silicon substrate 5, and then a polysilicon film with a thickness of 40,000 Å is deposited while doping with phosphorus. Then, the gate electrode is patterned by an etching process, and a silicon oxide film 9 having a thickness of 1000 Å is formed in an oxygen atmosphere.
次いで、第1図(b)に示すように、膜厚6000Aの
BPSG膜10を堆積し、窒素雰囲気中で900℃20
分のアニールを行いBPSG膜の平坦化を行う。Next, as shown in FIG. 1(b), a BPSG film 10 with a thickness of 6000 Å was deposited and heated at 900°C for 20 minutes in a nitrogen atmosphere.
The BPSG film is planarized by annealing for 30 minutes.
さらに、フォトリソグラフイおよび反応性イオンエッチ
ング工程により、ゲート電極1の間のソース電極形成領
域のBPSG膜10および酸化シリコン膜9をエッチン
グし、ソース電極形成領域に開口部11を形成した後、
等方性エッチングにより基板をエッチングし、第1図(
e)に示すように、開口部13を形成する。Further, the BPSG film 10 and the silicon oxide film 9 in the source electrode formation region between the gate electrodes 1 are etched by photolithography and reactive ion etching processes to form an opening 11 in the source electrode formation region.
The substrate was etched by isotropic etching, and as shown in Figure 1 (
As shown in e), an opening 13 is formed.
この後、第1図(d)に示すように、脂肪酸金属の一種
である、オクチル酸タングステン液をキシレンで希釈し
、これをこのシリコン基板表面に塗布し、減圧下で50
0℃に加熱して焼結する。こにより、オクチル酸タング
ステンは分解して、タングステンと炭素の混合固溶体薄
膜12が形成される。このときオクチル酸タングステン
液は、液体であるため、原理的にゲート電極1下の開口
部13に完全にゆきわたる。Thereafter, as shown in FIG. 1(d), a tungsten octylate solution, which is a type of fatty acid metal, was diluted with xylene, and this was applied to the surface of the silicon substrate, and was heated for 50 minutes under reduced pressure.
Sinter by heating to 0°C. As a result, tungsten octylate is decomposed and a mixed solid solution thin film 12 of tungsten and carbon is formed. At this time, since the tungsten octylate solution is a liquid, in principle it completely spreads to the opening 13 under the gate electrode 1.
このオクチル酸タングステン液の一回の塗布と焼結によ
り得られる膜厚は、希釈濃度によって変化するため必要
に応じて複数回の塗布焼結を繰り返すようにする。The film thickness obtained by one application and sintering of this tungsten octylate solution varies depending on the dilution concentration, so the application and sintering are repeated multiple times as necessary.
このようにして所望の膜厚のタングステン炭素混合固溶
体薄膜12を得た後、全面に膜厚10000Aのアルミ
ニウムーシリコン合金膜14をスバッタ法により第1図
(e)に示すように形成する。After obtaining the tungsten-carbon mixed solid solution thin film 12 with a desired thickness in this manner, an aluminum-silicon alloy film 14 with a thickness of 10,000 Å is formed on the entire surface by a sputtering method as shown in FIG. 1(e).
これは、ソース全体としての抵抗の低減のためである。This is to reduce the resistance of the source as a whole.
最後に、シリコン基板裏面に、チタン15、ニッケル1
6、銀17を順にそれぞれ膜厚2000A.6000A
,3000Aの厚さに蒸着して、第3図(『)に示すよ
うにドレイン電極4を形成し、さらに膜厚1200OA
のPSG保護IIi18を形成する。Finally, place 15 titanium and 1 nickel on the back side of the silicon substrate.
6 and silver 17 with a film thickness of 2000A. 6000A
, 3000A to form the drain electrode 4 as shown in FIG.
form the PSG protection IIi18.
このようにして、開口部13内に空洞を生じたりするこ
となく完全に開口部13を埋め込むことができる上、シ
リコン基板と酸化シリコン膜との界面にタングステンが
入り込むのを防止し、極めて容易に信頼性の高いショッ
トキー障壁型MOSトランジスタを形成することができ
る。In this way, the opening 13 can be completely filled without creating a cavity in the opening 13, and tungsten can be prevented from entering the interface between the silicon substrate and the silicon oxide film, making it extremely easy to fill the opening 13. A highly reliable Schottky barrier type MOS transistor can be formed.
また、この方法は、工程が単純でかつ安定であり、また
高価なCVD装置も不要であるため、コストの低減をも
はかることができる。Furthermore, this method has simple and stable steps, and does not require an expensive CVD device, so it can also reduce costs.
さらに、オクチル酸タングステンのキシレン希釈液を塗
布するに際し、その表面張力により、ゲート電極下の開
口部13のような部分は特にオクチル酸タングステンが
多量に付着し易く、優先的に埋め込まれていくため、埋
め込み特性のみならず、段差形状の改善の上でも有利な
方法である。Furthermore, when applying a xylene diluted solution of tungsten octylate, due to its surface tension, a large amount of tungsten octylate tends to adhere to areas such as the opening 13 under the gate electrode, and is preferentially buried. This is an advantageous method not only for improving the embedding characteristics but also for improving the shape of the step.
また、高級脂肪酸としてはオクチル酸を限定するもので
はなくネオデカン酸他の脂肪酸でもよい。Further, the higher fatty acid is not limited to octyl acid, but may be neodecanoic acid or other fatty acids.
さらに、この高級脂肪酸と結合させる金属としてはタン
グステンの他、アルミニウム、チタン、コバルト、銅、
ジルコニウム、モリブデン等から適宜選択可能である。Furthermore, in addition to tungsten, the metals that can be combined with this higher fatty acid include aluminum, titanium, cobalt, copper,
It can be appropriately selected from zirconium, molybdenum, etc.
以上説明してきたように、本発明の半導体装置の製造方
法によれば、ショットキー障壁型MOSトランジスタの
ソース電極の形成に際し、基板表面にゲート電極下にま
で至る四部を形成し、この凹部内に脂肪酸金属を有機溶
剤に溶かした液をシリコン基板表面に塗布し、シリコン
基板表面に脂肪酸金属を付着させたのち、これを分解焼
結して金属膜を形成し、必要に応じてこの金属膜に対し
てソース配線を行うようにしているため、閾値電圧が低
く信頼性の高いトランジスタを得ることが可能となる。As described above, according to the method for manufacturing a semiconductor device of the present invention, when forming the source electrode of a Schottky barrier type MOS transistor, four portions extending below the gate electrode are formed on the substrate surface, and the four portions are filled in the recessed portion. A solution of fatty acid metal dissolved in an organic solvent is applied to the surface of the silicon substrate to adhere the fatty acid metal to the surface of the silicon substrate, which is then decomposed and sintered to form a metal film. On the other hand, since the source wiring is provided, it is possible to obtain a transistor with a low threshold voltage and high reliability.
第1図は(a)乃至第1図(『)は本発明の第1の実施
例のショットキー障壁型MOSトランジスタの製造工程
を示す図、第2図および第3図はそれぞれ従来例のショ
ットキー障壁型MOSトランジスタを示す図である。
1・・・ゲート電極、2・・・酸化シリコン膜、3・・
・ソース電極、4・・・ドレイン電極、5・・・シリコ
ン基板、6・・・すきま、7・・・タングステン膜、8
・・・ゲート絶縁膜、9・・・酸化シリコン膜、10・
・・BPSG膜、11・・・ソース電極形成領域の開口
部、12・・・タングステンと炭素の固溶体(ソース電
t!!ii)、13・・・開口部、14・・・AI−S
i合金膜、15・・・チタン、16・・・ニッケル、1
7・・・銀。
第1 図
41(a) to 1(') are diagrams showing the manufacturing process of the Schottky barrier type MOS transistor of the first embodiment of the present invention, and FIGS. 2 and 3 are shots of the conventional example, respectively. FIG. 2 is a diagram showing a key barrier type MOS transistor. 1... Gate electrode, 2... Silicon oxide film, 3...
・Source electrode, 4...Drain electrode, 5...Silicon substrate, 6...Gap, 7...Tungsten film, 8
...Gate insulating film, 9...Silicon oxide film, 10.
... BPSG film, 11... Opening of source electrode formation region, 12... Solid solution of tungsten and carbon (source electrode t!!ii), 13... Opening, 14... AI-S
i alloy film, 15... titanium, 16... nickel, 1
7...Silver. 1st figure 4
Claims (1)
コン基板との間でショットキー接合を形成するように構
成されたショツトキーソース型MOSトランジスタの製
造方法において、シリコン基板上にゲート絶縁膜を介し
てゲート電極を形成するゲート電極形成工程と、前記ゲ
ート電極の上層に絶縁膜を形成する絶縁膜形成工程と、
ソース電極形成部のシリコン基板表面をゲート電極端縁
の下部まで到達するような凹部を形成する凹部形成工程
と、脂肪酸金属を有機溶剤に溶かした溶液をシリコン基
板表面に塗布する塗布工程とシリコン基板表面に塗布せ
しめられた脂肪酸金属を加熱分解し、前記凹部内に金属
膜を形成する焼結工程とからなるソース電極形成工程と
、ドレイン電極形成工程とを含むことを特徴とする半導
体装置の製造方法。(1) In a method for manufacturing a Schottky source type MOS transistor configured to form a Schottky junction between a source electrode formed on the surface of a silicon substrate and the silicon substrate, a gate electrode forming step of forming a gate electrode; an insulating film forming step of forming an insulating film on the upper layer of the gate electrode;
A recess formation step in which a recess is formed on the silicon substrate surface of the source electrode forming part to reach the lower part of the edge of the gate electrode, a coating step in which a solution of a fatty acid metal dissolved in an organic solvent is applied to the silicon substrate surface, and the silicon substrate Manufacturing a semiconductor device comprising: a source electrode forming step consisting of a sintering step of thermally decomposing a fatty acid metal coated on the surface and forming a metal film in the recess; and a drain electrode forming step. Method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24005789A JPH03102819A (en) | 1989-09-18 | 1989-09-18 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24005789A JPH03102819A (en) | 1989-09-18 | 1989-09-18 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03102819A true JPH03102819A (en) | 1991-04-30 |
Family
ID=17053845
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP24005789A Pending JPH03102819A (en) | 1989-09-18 | 1989-09-18 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03102819A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6271594B1 (en) | 1997-05-29 | 2001-08-07 | Nec Corporation | Semiconductor device and method of manufacturing the same |
WO2010113715A1 (en) * | 2009-03-31 | 2010-10-07 | 日鉱金属株式会社 | Method of producing semiconductor device, and semiconductor device |
JP2011155273A (en) * | 2011-03-03 | 2011-08-11 | Fujitsu Semiconductor Ltd | Semiconductor wafer and method for manufacturing the same |
CN102163623A (en) * | 2010-02-23 | 2011-08-24 | 富士电机系统株式会社 | Semiconductor device and fabrication method of semiconductor device |
US8592951B2 (en) | 2005-12-19 | 2013-11-26 | Fujitsu Semiconductor Limited | Semiconductor wafer having W-shaped dummy metal filling section within monitor region |
-
1989
- 1989-09-18 JP JP24005789A patent/JPH03102819A/en active Pending
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6271594B1 (en) | 1997-05-29 | 2001-08-07 | Nec Corporation | Semiconductor device and method of manufacturing the same |
US6274417B1 (en) | 1997-05-29 | 2001-08-14 | Nec Corporation | Method of forming a semiconductor device |
KR100298915B1 (en) * | 1997-05-29 | 2001-10-19 | 가네꼬 히사시 | Semiconductor device and method of manufacturing the same |
US8592951B2 (en) | 2005-12-19 | 2013-11-26 | Fujitsu Semiconductor Limited | Semiconductor wafer having W-shaped dummy metal filling section within monitor region |
WO2010113715A1 (en) * | 2009-03-31 | 2010-10-07 | 日鉱金属株式会社 | Method of producing semiconductor device, and semiconductor device |
CN102163623A (en) * | 2010-02-23 | 2011-08-24 | 富士电机系统株式会社 | Semiconductor device and fabrication method of semiconductor device |
JP2011176027A (en) * | 2010-02-23 | 2011-09-08 | Fuji Electric Co Ltd | Semiconductor element and method of manufacturing the same |
US8691635B2 (en) | 2010-02-23 | 2014-04-08 | Fuji Electric Co., Ltd. | Fabrication method of semiconductor device |
JP2011155273A (en) * | 2011-03-03 | 2011-08-11 | Fujitsu Semiconductor Ltd | Semiconductor wafer and method for manufacturing the same |
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