JPS63291437A - Semiconductor device - Google Patents

Abstract

PURPOSE:To avoid the deterioration of contact characteristics and improve the reliability and life of a wiring by a method wherein a high melting point metal film is deposited over a layer insulating film and the inner surface of an aperture drilled in the layer insulating film so as to reach the surface of a diffused layer as a barrier metal film. CONSTITUTION:A contact hole 13 which reaches the surface of a diffused layer 11 is drilled by a photolithography technology. A titanium film and a titanium nitride film are successively built up over the whole surface including the inner surface of the contact hole 13 to form a barrier metal layer 14 composed of a double-layer film. Then a polycrystalline silicon layer 15 is deposited. By etching the polycrystalline silicon layer 15 to the vertical direction to the extent of its thickness, the polycrystalline silicon layer 15 is left on the side wall of the contact hole 13 only. Then a silicon layer 16 doped with a high concentration impurity whose conductivity type is the same as that of the diffused layer 11 is formed in the contact hole 13 to fill the contact hole 13 with the silicon layer, 16. Then wiring material composed of Al-Si alloy is deposited over the whole surface and patterned to form a wiring 17.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Field of Application) The present invention relates to a semiconductor device in which internal wiring, particularly wiring of fine contact portions, is improved.

(Prior Art) Conventionally, when forming a contact to an active region of a semiconductor device, first a diffusion layer is formed as an active region, an interlayer insulating film is deposited on it, and then a contact hole is formed in this interlayer insulating film. A hole is opened, and then a wiring material is deposited by sputtering or the like, and this is patterned to form a contact. In addition, An-8i, which is generally made of aluminum containing silicon, is used as the wiring material.
Alloys are used. By forming the contact with the -8i alloy using A, penetration of the aluminum into the diffusion layer is prevented.

By the way, in order to obtain good electrical conduction with the diffusion layer in the above-mentioned contact, sintering treatment is performed after Al2-8i deposition, but at that time, the silicon substrate and the Al-8i
The reaction causes silicon to precipitate at the interface, resulting in the inconvenience of deterioration of contact characteristics.

Furthermore, in the case of a multilayer wiring structure, after the first layer of Al2-Si is deposited and patterned, an interlayer insulating film is deposited on top of it as a planarization process. Void) occurs, which causes a decrease in the reliability of the wiring at the contact portion.

Furthermore, when depositing Al2-5+ alloy by sputtering, the step coverage of the Affi-3i alloy in the contact portion becomes increasingly worse as the contact size becomes finer. Therefore, the reliability of the A1-5+ wiring is significantly reduced.

Furthermore, due to the scaling of the wiring width, the life of the wiring deteriorates when only the β-8i wiring is used.

(Problems to be Solved by the Invention) In this way, in the past, the silicon substrate and the wiring made of Affi-3i alloy were brought into direct contact, resulting in deterioration of contact characteristics and reliability of the Ap-s + wiring. Problems such as deterioration of wiring and deterioration of wiring life are occurring. Therefore, an object of the present invention is to provide a semiconductor device that can eliminate all of these drawbacks.

[Configuration of the Invention (Means for Solving Problems)] A semiconductor device of the present invention includes a diffusion layer formed in a silicon semiconductor substrate, an interlayer insulating film deposited on the diffusion layer, and the diffusion layer. an opening formed in the interlayer insulating film to reach the surface of the interlayer insulating film; a high melting point metal film deposited over the inner peripheral surface of the opening and the interlayer insulating film; and filling the opening. The semiconductor device is composed of a silicon layer formed in such a manner that the silicon layer is formed in a manner similar to the above, and a metal wiring formed over the silicon layer and the high melting point metal film.

(Function) In the semiconductor device of the present invention, a high melting point metal film as a barrier metal is deposited over the inner peripheral surface of the opening formed in the interlayer insulating film and on the glabella insulating film so as to reach the surface of the diffusion layer. This prevents direct contact between the metal wiring and the diffusion layer.

Moreover, by filling the opening with the silicon layer, it is possible to prevent the formation of cavities in the interlayer film near the opening.

(Example) Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a cross-sectional view sequentially showing steps in manufacturing a semiconductor device of the present invention.

First, as shown in FIG. 1(a), a silicon semiconductor substrate 1
0 by a normal silicon gate MOS process.
Form an S transistor. At this time, a diffusion 1111 having a conductivity type opposite to that of the substrate is formed on the substrate 10. After this, the diffusion layer 11 is formed by CVD (chemical vapor deposition).
After depositing silicon oxide 1112 on the entire surface including the surface, the surface of the silicon oxide film 12 is planarized by annealing at 900° C. for 30 minutes, for example. After that, the silicon oxide film 12 is etched by photolithography.
A contact hole 13 reaching the surface of the diffusion layer 11 is opened.

Next, as shown in FIG. 1(b), the contact hole 13
A titanium film (Ti) and titanium nitride (TiN) are successively deposited on the entire surface including the inner circumferential surface of the barrier metal layer 14 by sputtering to a thickness of 500 and 1000, respectively, to form a barrier metal layer 14 consisting of a two-layer film. do. Subsequently, a polycrystalline silicon layer 15 is deposited to a thickness of 500 nm over the entire surface by LP-CVD (low pressure chemical vapor deposition).

Next, as shown in FIG. 1C, the polycrystalline silicon layer 15 is vertically etched by the thickness thereof using an anisotropic etching technique. Leave only on the side walls. At this time, by using an etching gas having a high selectivity between the barrier metal layer 14 and the polycrystalline silicon 1i115, the barrier metal layer 14 can be left as is.

Next, as shown in FIG. 1(d), the contact hole 13
Silicon W 116 into which impurities of the same conductivity type as the diffusion layer 11 are introduced at a high concentration is formed inside the silicon layer 11 , and the contact hole 13 is filled with this silicon layer 16 .

This step is performed using selective silicon growth techniques.

That is, during selective silicon growth, the contact hole 13
Since the silicon layer grows in a short time only from the polycrystalline silicon layer 15 left on the sidewall of the contact hole 13, the inside of the contact hole 13 can be filled with the silicon layer 16. Next, a wiring material made of Affi-8i alloy is deposited on the entire surface and patterned to form wiring 17. After this, an interlayer insulating film 18 is deposited on the entire surface as shown in FIG. 1(e).

According to such a structure, the barrier gold 114 is interposed between the wiring 17 made of Afi-8i alloy and the diffusion layer 11, so that the two do not come into direct contact with each other, so that unlike the conventional method, silicon is removed during sintering. Deterioration of contact characteristics due to precipitation of is suppressed. Further, by filling the contact hole 13 with the silicon layer 16, the level difference is alleviated, and it is possible to prevent the formation of cavities in the interlayer insulating film when a multilayer wiring structure is formed. And Aff- at the contact part
The step coverage of the wiring 17 due to the 8i alloy also becomes good. Furthermore, since the wiring 17 made of β-3i alloy has a laminated structure with the barrier metal layer 14, the life of the wiring itself is greatly improved.

FIG. 2 is a sectional view showing the structure of a semiconductor device according to another embodiment of the invention. In the device of this embodiment, the barrier metal layer 14 is formed only on the II wall of the contact hole 13. In such a semiconductor device, an etching gas having the same etching rate as that of the barrier metal layer 14 is used during anisotropic etching of the polycrystalline silicon layer 15. In this case, during the selective growth of the silicon layer 15, the silicon layer 16 also grows from the bottom of the contact hole 13, making it possible to fill the contact hole 13 more quickly.

[Effects of the Invention] As explained above, according to the present invention, problems such as deterioration of contact characteristics, deterioration of wiring reliability, deterioration of wiring life, etc.
It is possible to provide a semiconductor device that can eliminate all the drawbacks of conventional devices.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing the steps of manufacturing a semiconductor device according to the present invention, and FIG. 2 is a cross-sectional view showing the structure of a semiconductor device according to another embodiment of the present invention. 10... Silicon semiconductor substrate, 11... Diffusion layer, 1
2... Silicon oxide film, 13... Contact hole, 1
4... Barrier metal layer, 15... Polycrystalline silicon layer,
16... Silicon layer, 17... Wiring, 18... Interlayer insulating film. Applicant's agent Patent attorney Takehiko Suzue (a) (b) (c) Figure 1

Claims (2)

[Claims] (1) A diffusion layer formed in a silicon semiconductor substrate, an interlayer insulation film formed on the diffusion layer, and an opening formed in the interlayer insulation film to reach the surface of the diffusion layer. , a high melting point metal film formed over the inner peripheral surface of the opening and the interlayer insulating film, a silicon layer formed to fill the opening, and a high melting point metal film over the silicon layer and the high melting point metal. A semiconductor device comprising a metal wiring formed over a film. (2) The semiconductor device according to claim 1, wherein an impurity of the same conductivity type as that contained in the diffusion layer is introduced into the silicon layer.