JPH0214575A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent characteristic deterioration called channel leakage by fluctuation of the threshold value voltage by a method wherein a MOS field effect transistor includes a gate region having a plurality of threshold value voltages and thereby the threshold value voltage of a channel region liable to receive stress is in advance adjusted and changed. CONSTITUTION:A MOS field effect transistor includes a gate region having a plurality of threshold value voltages shown by A and B. For instance, suppose that great stress is put on the region A. In this case, the threshold value voltage lowers caused by increased interface charge or the like the MOS field effect transistor. In this case, however, when the p-type substrate impurity density in this region A is if advance raised higher than the region B (possible by an ordinary channel doping method or the like) to raise the threshold value voltage, the portion of the lowered threshold value voltage due to stress can be compensated for.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention relates to a semiconductor device, and in particular to a MO
The present invention relates to a semiconductor device including an S field effect transistor.

[Prior Art] FIG. 2 shows a conventional NMOS, that is, an n-channel MO
This is a cross-sectional structure of a three-structure field effect transistor. There are 3 electrodes for the source, gate, and drain from the left in the figure.
Individuals exist. Further, as the name MOS indicates, the gate portion has a stacked structure of a gate electrode 5, a gate oxide film 4, and a p-type silicon substrate 1.

The gate electrode 5 and the lead wire 7 are insulated by an interlayer insulating film 6. In the figure, reference numeral 3 represents a field oxide film for isolation between elements.

Although this device is equipped with a surface protective film layer, its illustration is omitted to simplify the drawing.

In a conventional MO6% field effect transistor, the threshold voltage (VTH) of the channel region is only one heel. Here, the threshold voltage refers to the gate voltage that causes an inversion layer to be formed on the silicon surface of a MOS capacitor (Koyama ed., Ultra High Speed MOS Devices (published by Baifukan in 1988), 11.9
(see page). The impurity concentration, gate oxide film thickness, interface charge, etc. that determine this threshold voltage are kept constant, and the MO3 field effect transistor exhibits normal characteristics.

[Problem to be solved by the invention] Conventional MO5? Since the Li field effect transistor is configured as described above and has only one type of channel region, the following problems have arisen. That is, referring to FIG. 3, when chip 8 of the N-channel MOS field effect transistor as described above is connected to external leads 10 and packaged in resin 9, compressive stress is applied to chip 8 from resin 9. When the chip 8 is subjected to non-uniform strain due to this compressive stress, there is a problem in that the threshold voltage of the channel region receiving the maximum stress changes, resulting in characteristic deterioration called channel leakage.

This invention was made to solve the above-mentioned problems, and an object thereof is to provide a semiconductor device including a MOS field effect transistor that does not cause characteristic deterioration even when subjected to internal or external stress. shall be.

[Means for Solving the Problems] The present invention relates to a semiconductor device including a MOS field effect transistor. In order to solve the above problem, the MOS Ri field effect transistor includes a gate region having a plurality of threshold voltages, whereby the threshold voltage of the stress-prone channel region is adjusted in advance. There is.

[Operation] Since the MO3'J field effect transistor includes a gate region with multiple threshold voltages, the threshold voltage of the stress-sensitive channel region is pre-adjusted, so that even if the stress-induced interface There is an increase in charge,
Even if the threshold voltage decreases, channel leakage can be prevented from occurring.

[Example] Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram for explaining one embodiment of the present invention. Referring to FIG. 1, the portion designated by reference numeral 2 is n
The ten-shaped diffusion region, designated by reference numeral 5, is the gate electrode. MO3 required for the example? The IS field effect transistor includes a gate region, labeled A and B in the figure, with multiple threshold voltages.

Referring to FIG. 1, for example, assume that a large stress is applied to region A. In this case, in a MOS field effect transistor, the threshold voltage decreases due to factors such as an increase in interfacial charge. In this case, if the p-type substrate impurity concentration in the A region is made higher than that in the B region in advance (this can be done by a normal channel doping method, etc.) and the threshold voltage is increased, the threshold voltage due to stress can be reduced. It is possible to compensate for the drop in value voltage.

Further, referring to FIG. 3, it is known that when a chip 8 of a 5 ftt N-channel field effect transistor is packaged with resin, the stress at the outer periphery of the chip 8 is higher than at other parts. In such a case, the stress causes the threshold voltage of the N-channel MOS field effect transistor to decrease in the channel region near the outer periphery of the chip. However, according to the present invention, the substrate impurity concentration is increased in the portion where the threshold voltage is expected to decrease;
By raising the threshold voltage of that portion in advance, it is possible to compensate for the drop in threshold voltage due to stress.

In the above embodiment, the case where the field effect transistor is an N-channel MOS field effect transistor has been described, but the present invention is not limited to this, and even if it is a P-channel MO3 field effect transistor, the same method as in the embodiment can be applied. Realize the effect.

Further, in the above embodiment, a method of creating a gate region having a plurality of threshold voltages is explained by exemplifying a method of changing the substrate impurity concentration, but the present invention is not limited to this. Even by changing the thickness of the oxide film, the same effects as in the embodiment can be achieved.

Although the semiconductor device of the present invention has been described above with reference to specific embodiments, the present invention can be implemented in various other forms without departing from its spirit or main characteristics. Therefore, the embodiments described above are in all respects I
This is only an example and should not be interpreted in a limited manner. The scope of the present invention is indicated by the claims, and is not restricted in any way by the main text of the specification. Furthermore, all modifications and changes that come within the scope of equivalents of the claims are intended to be within the scope of the present invention.

[Effects of the Invention] As explained above, according to the present invention, an MO8 field effect transistor includes a gate region having a plurality of threshold voltages, whereby the threshold voltage of a channel region susceptible to stress is set in advance. Since the adjustment is changed, even if an increase in interfacial charge due to stress causes a decrease in threshold voltage, the decrease in threshold voltage due to stress can be compensated for. Therefore, it is possible to prevent characteristic deterioration called channel leakage caused by fluctuations in threshold voltage. As a result, it is possible to obtain a semiconductor device that can operate stably and with high reliability over a long period of time.

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining one embodiment of the present invention. FIG. 2 is a diagram of a cross-sectional structure of a field effect transistor having an 8MO8 structure. FIG. 3 is a diagram of a NMO3m field effect transistor chip packaged in resin. In the figure, 5 is a gate electrode, A is a portion with a raised threshold voltage, and B is a portion with a normal threshold voltage. In each figure, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] A semiconductor device including a MOS field effect transistor, wherein the MOS field effect transistor includes a gate region having a plurality of threshold voltages, whereby the threshold voltage of a channel region susceptible to stress is adjusted. A semiconductor device that has been adjusted in advance.