JPH06177339A - Semiconductor integrated circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] Even when the drain area of the output transistor is reduced along with the miniaturization of IC elements, it is possible to prevent a decrease in electrostatic breakdown withstand against surge input from the output pad. In an output circuit section of an IC, a CMOS type output circuit 11, an output pad 12 connected to an output node of this output circuit, a gate and a source are connected to an output node of the output circuit, and a substrate region is a power source. A MOS transistor for electrostatic breakdown protection, which is connected to a potential node or a ground potential node, has a drain connected to a semiconductor substrate and a well region, and has a gate insulating film 35 formed to have a threshold voltage higher than an IC power supply voltage. N2 or P2
And is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a semiconductor integrated circuit (I
Regarding C), especially the MOS for protection against electrostatic damage of the output circuit
Regarding transistors.

[0002]

2. Description of the Related Art FIG. 6 shows an example of an output circuit section in a conventional CMOS IC.

In this output circuit section, data from the internal circuit 10 is output to an output terminal (pad) 12 through a CMOS type output buffer circuit 11. Output buffer circuit 1
1, a P-channel MOS (PMOS) transistor P1 for output and an NMOS transistor N1 are connected in series between a power supply potential (VCC) node and a ground potential (VSS) node, and these output transistors P1, N
Each drain of 1 is connected to the output pad 12.

In the output circuit section, the output pad 1
When a surge such as static electricity is input from 2, the PMOS
Parasitic diode due to junction between drain region (P type diffusion layer) of transistor P1 and substrate region (N well) or parasitic due to junction between drain region (N type diffusion layer) of NMOS transistor N1 and substrate region (P type) By absorbing by the diode, the output transistor P
1 and N1 are protected from electrostatic breakdown.

By the way, with the miniaturization of the elements in the IC, the drain areas of the output transistors P1 and N1 are also reduced, and the PN junction area of the parasitic diode is also reduced. As a result, the capacitance of the PN junction becomes small, and the rounding of the surge input waveform determined by the time constant of this capacitance and the resistance of the output wiring becomes small, and the electrostatic breakdown withstand capability of the output transistor decreases.

As a measure for preventing the decrease in electrostatic breakdown resistance, it is conceivable to increase the drain area of the output transistor to increase the capacitance of the diffusion layer, but with this, the chip size increases. However, the chip cost will be high.

As another measure, it is possible to insert a resistor in the output wiring, but this causes a decrease in the operating speed of the output transistor and a decrease in the driving capability.

When the output transistor has a double diffused drain structure, as a measure for increasing the electrostatic breakdown resistance,
It is possible to increase the gate length of the output transistor and increase the concentration by adding impurities to the low concentration layer of the drain, but increasing the gate length lowers the operating speed and increases the cost due to the addition of processes. .

[0009]

As described above, the conventional IC has a problem that when the drain area of the output transistor is reduced with the miniaturization of the element, the electrostatic breakdown resistance of the output transistor is reduced.

The present invention has been made to solve the above problems. Even if the drain area of the output transistor becomes smaller due to the miniaturization of the element, the electrostatic breakdown of the output transistor against the surge input from the output pad. An object of the present invention is to provide a semiconductor integrated circuit capable of preventing a decrease in withstand voltage.

[0011]

In a semiconductor integrated circuit of the present invention, a CMOS type output circuit, an output pad connected to an output node of the output circuit, and a gate and a source connected to the output node of the output circuit. The substrate region is connected to the power supply potential node or the ground potential node, the drain is connected to the semiconductor substrate and the well region, and the gate insulating film is formed to have a threshold voltage higher than the integrated circuit power supply voltage. A MOS transistor for destruction protection is provided.

[0012]

When a surge is input from the output pad, the surge is received by the drain region of the output transistor of the output circuit and the transistor for electrostatic breakdown protection. In this case, the electrostatic breakdown protection transistor is turned on, and the surge input is released to the semiconductor substrate or the well region.

As a result, even if the drain area of the output transistor becomes smaller due to the miniaturization of the element, it is possible to prevent the electrostatic breakdown withstand capability of the output transistor from being lowered with respect to the surge input from the output pad.

Therefore, even if the element is miniaturized, the electrostatic breakdown withstand capability can be improved without increasing the chip size, the chip cost, the operating speed of the output transistor, and the driving capability. It will be possible.

[0015]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a CMO according to a first embodiment of the present invention.
It is a circuit diagram which shows the output circuit part of S type IC.

This output circuit section outputs the data from the internal circuit 10 to the output pad 12 via the CMOS type output buffer circuit 11. The output buffer circuit 11 has V
An output PMOS transistor P1 and an NMOS transistor N1 are connected in series between the CC node and the VSS node, and these output transistors P1 and N1 are connected.
Each drain (the output node of the output circuit) is output pad 1
Connected to 2.

Further, the output node of the output buffer circuit 11 is connected to a MOS transistor for electrostatic breakdown protection (in this example, a PMOS transistor P2 and an NMOS transistor N2).

That is, in the NMOS transistor N2 for electrostatic breakdown protection, the gate and source (N type diffusion layer) are connected to the output pad 12, the drain (N type diffusion layer) is connected to the VCC node, and the substrate region thereof is provided. (P-type semiconductor substrate) is V
Connected to SS node.

Also, in the electrostatic breakdown protection PMOS transistor P2, the gate and source (P-type diffusion layer) are connected to the output pad 12, the drain (P-type diffusion layer) is connected to the VSS node, and its substrate region is formed. VCC is applied to (N well region in the P type substrate).

In the electrostatic breakdown protection NMOS transistor N2 and PMOS transistor P2, the gate insulating film is formed thick so that the threshold voltage thereof becomes higher than the power supply voltage Vcc of the IC. FIG. 2 is a cross-sectional view showing the element structure of the output NMOS transistor N1 and the electrostatic breakdown prevention NMOS transistor N2 in FIG.

Here, 31 is a P-type semiconductor substrate and 32 is P
An N well selectively formed on the surface layer portion of the mold substrate, 35 is a field oxide film for element isolation selectively formed on the substrate surface, and 33a and 33b are output electrodes formed on a part of the substrate surface layer portion. Source region (N-type diffusion layer) and drain region (N-type diffusion layer) of the NMOS transistor N1 of
Reference numeral 4 is a gate insulating film of the output NMOS transistor formed on the surface of the substrate, and 36a is a gate electrode (for example, polysilicon is used) of the output NMOS transistor formed on the gate insulating film 34. is there.

The drain region 33b of the output NMOS transistor N1 also serves as the source region (N-type diffusion layer) of the electrostatic breakdown preventing NMOS transistor N2, and the field oxide film 35 adjacent to the source region 33b. NMOS transistor N for electrostatic discharge prevention with a pin in between
The second drain region (N-type diffusion layer) 33c is formed so as to be continuous with a part of the surface layer portion of the substrate 31 and a part of the surface layer portion of the N well 32.

The source region 33b and the drain region 33
The field oxide film 35 between c and c is a gate insulating film of the NMOS transistor for electrostatic breakdown prevention, and the gate electrode 36b of the NMOS transistor for electrostatic breakdown prevention (the output NMOS transistor (The same wiring layer as the gate electrode 36a is used) is formed. That is, the gate insulating film 35 of the NMOS transistor for electrostatic breakdown protection has a film thickness larger than that of the gate insulating film 34 of other MOS transistors (such as the output NMOS transistor N1) whose threshold voltage is lower than the integrated circuit power supply voltage. It is formed thick.

Further, each of the gate electrodes 36a and 36b is provided.
An interlayer insulating film 37 is formed on the above. Then, the source wiring 38b and the output wiring 38a of the output NMOS transistor are formed on the interlayer insulating film 37 by metal wiring. The source wiring 38b is in contact with the source region 33a of the output NMOS transistor through a contact hole formed in the interlayer insulating film 37.

In addition, the output wiring 38a has a gate electrode 36b of the NMOS transistor for preventing electrostatic breakdown and a drain region 33 of the NMOS transistor for output through a contact hole formed in the interlayer insulating film 37.
b are each contacted. Further, a protective film 39 is formed on each of the wirings 38a and 38b, and a pad opening (not shown) is formed in the protective film 39.

In the output circuit portion having the structure shown in FIG. 2, when a positive charge surge is input from the output pad, it is applied to the gate electrode 36b of the NMOS transistor for preventing electrostatic breakdown through the output wiring 38a and output. For NM
It is applied to the drain region 33b of the OS transistor.
As a result, the NMOS transistor N for electrostatic breakdown protection is
2 is turned on, and positive charges are released to the N well region 32. FIG. 3 is a cross-sectional view showing the element structures of the output PMOS transistor P1 and the electrostatic breakdown prevention PMOS transistor P2 in FIG.

Here, 41 is a P-type semiconductor substrate and 42 is a P-type semiconductor substrate.
An N well selectively formed on the surface layer of the mold substrate, 45 is a field oxide film for element isolation selectively formed on the substrate surface, and 43a and 43b are outputs formed on a part of the N well surface layer. Source region (P type diffusion layer) and drain region (P type diffusion layer) of the PMOS transistor for
4 is a gate insulating film of the output PMOS transistor formed on the surface of the N well, and 46a is the gate insulating film 44.
It is a gate electrode of an output PMOS transistor formed on the above.

The drain region 43b of the output PMOS transistor also serves as the source region (P-type diffusion layer) of the NMOS transistor for electrostatic breakdown prevention, and the field oxide film 45 adjacent to the source region 43b is sandwiched therebetween. A drain region (P-type diffusion layer) 43c of the PMOS transistor for preventing electrostatic breakdown is formed in the drain region 43c, and the drain region 43c is part of the surface layer of the N well 42 and the substrate 4.
1 is formed so as to be continuous with a part of the surface layer portion.

The source region 43b and the drain region 43
The field oxide film 45 between c and c is a gate insulating film of the PMOS transistor for preventing electrostatic breakdown, and the gate electrode 46b of the PMOS transistor for preventing electrostatic breakdown is formed thereon. That is, the gate insulating film 45 of the PMOS transistor for electrostatic breakdown protection is thicker than the gate insulating films of other MOS transistors whose threshold voltage is lower than the integrated circuit power supply voltage (such as the output PMOS transistor P1). Has been formed.

Further, each of the gate electrodes 46a, 46b described above
An interlayer insulating film 47 is formed on the above. A source wiring 48b and an output wiring 48a of the output PMOS transistor are formed on the interlayer insulating film 47 by metal wiring. The source wiring 48b is in contact with the source region 43a of the output PMOS transistor through a contact hole opened in the interlayer insulating film 47.

In addition, the output wiring 48b is provided with a gate electrode 46b of the PMOS transistor for preventing electrostatic breakdown and a drain region 43 of the output PMOS transistor through a contact hole formed in the interlayer insulating film 47.
b are each contacted. Further, a protective film 49 is formed on each of the wirings 48a and 48b, and a pad opening (not shown) is formed in the protective film 49.

In the output circuit section having the structure shown in FIG. 3, when a negative charge surge is input from the output pad 42,
It is applied to the gate electrode 46b of the PMOS transistor for preventing electrostatic breakdown through the output wiring 48a and to the drain region 43b of the output PMOS transistor P1. As a result, the electrostatic breakdown protection PMOS transistor P2 is turned on, and negative charges are released to the P-type substrate 41.

That is, in the IC of the first embodiment,
When a surge is input from the output pad 12, the surge is received not only by the drain regions of the output transistors P1 and N1 of the output buffer circuit 11 but also by the electrostatic breakdown protection transistors P2 and N2. In this case, the electrostatic breakdown protection transistor is turned on, and the surge input is released to the semiconductor substrate or the well region.

As a result, even if the drain areas of the output transistors P1 and N1 are reduced with the miniaturization of the element, the electrostatic breakdown withstand capability of the output transistors P1 and N1 against the surge input from the output pad 12 is prevented from decreasing. It will be possible.

Therefore, even if the element is miniaturized, the electrostatic breakdown withstand capability can be improved without increasing the chip size, the chip cost, the operating speed of the output transistor, and the driving capability. It will be possible.

The present invention is not limited to the above embodiment, but the NMO shown in FIG. 2 can be used as a transistor for electrostatic breakdown protection.
Only the S transistor N2 or the PM shown in FIG.
It also includes the case where only the OS transistor P2 is provided. Figure 4
FIG. 6 is a cross-sectional view showing a modified example of the NMOS transistor for preventing electrostatic breakdown in FIG. 2.

In comparison with the NMOS transistor N2 for preventing electrostatic breakdown shown in FIG. 2, the NMOS transistor for preventing electrostatic breakdown in FIG. 4 has its gate electrode replaced by an output wiring (metal wiring) 58a. Is different. Others are the same as in the case of FIG. 2, and reference numerals 51, 52 and 5 in FIG.
3a, 53b, 54 to 57 and 58b are designated by reference numeral 3 in FIG.
1, 32, 33a, 33b, 34 to 37, 38b respectively. The NMOS transistor for preventing electrostatic breakdown of FIG. 4 is also the NM for preventing electrostatic breakdown of FIG.
The same effect as the OS transistor can be obtained. Note that FIG.
As for the internal PMOS transistor for preventing electrostatic breakdown, it is possible to substitute the metal wiring for the gate electrode as in the above.

FIG. 5 shows an NMO according to the second embodiment of the present invention.
A MOS transistor for output and an MO for preventing electrostatic breakdown in the output circuit section of an S-type or PMOS-type IC
It is sectional drawing which shows an example of an S transistor.

Here, 61 is a P-type or N-type semiconductor substrate, 65 is a field oxide film for element isolation selectively formed on the substrate surface, and 63a and 63b are formed on a part of the substrate surface layer. Source region and drain region of the output MOS transistor, 64 is a gate insulating film of the output MOS transistor formed on the substrate surface, 66b
Is an output MO formed on the gate insulating film 64.
This is the gate electrode of the S transistor.

The drain region 63b of the output MOS transistor also serves as the source region of the electrostatic breakdown preventing MOS transistor, and the electrostatic breakdown prevention is provided with the field oxide film 65 adjacent to the source region 63b interposed therebetween. A drain region 63b of the MOS transistor is formed,
A diffusion layer region 63c of a different conductivity type (same conductivity type as the substrate) is formed so as to be continuous with the drain region 63b.

The source region 63b and the drain region 63
The field oxide film 65 between c and c is a gate insulating film of the MOS transistor for preventing electrostatic breakdown, and the gate electrode 66b of the MOS transistor for preventing electrostatic breakdown is formed on this. In other words, P for electrostatic damage protection
The gate insulating film 65 of the MOS transistor is formed to be thicker than the gate insulating film of another MOS transistor whose threshold voltage is lower than the integrated circuit power supply voltage (such as an output MOS transistor).

Furthermore, each of the gate electrodes 66a and 66b described above.
An interlayer insulating film 67 is formed on the above. The source wiring 68b, the output wiring 68a and the connection wiring 68 of the output MOS transistor are formed on the interlayer insulating film 67.
c is formed by metal wiring. Source wiring 6
8b is a source region 63 of the output MOS transistor through a contact hole formed in the interlayer insulating film 67.
Contact a.

The output wiring 68a is in contact with the gate electrode 66b of the MOS transistor for preventing electrostatic breakdown and the drain region 63b of the MOS transistor for output through a contact hole formed in the interlayer insulating film 67. .

The connection wiring 68c contacts the drain region 63c of the PMOS transistor for preventing electrostatic breakdown and the diffusion layer region 62 of different conductivity type connected thereto at the bottom of the contact hole opened in the interlayer insulating film 67. Has been done.

In the structure shown in FIG. 5, the structure shown in FIG.
Compared to the IC shown in FIG. 3, the well region does not exist, and the output MOS transistor and the electrostatic breakdown preventing MOS transistor are formed on the surface layer of the P-type or N-type semiconductor substrate.

That is, in the IC of the second embodiment,
When a surge is input from the output pad 12, the surge is received not only by the drain region of the output transistor of the output circuit but also by the transistor for protection against electrostatic breakdown. In this case, the electrostatic breakdown protection transistor is turned on, and the surge input is released to the semiconductor substrate 61 through the electrostatic breakdown protection transistor, the connection wiring 68c, and the diffusion layer region 62. As a result, the same effect as that of the first embodiment can be obtained.

Although the drain region 63b of the MOS transistor for preventing electrostatic breakdown and the diffusion layer region 63c of different conductivity type are formed adjacent to each other in the second embodiment, they are formed separately. , May be formed so as to be connected by wiring.

As for the MOS transistor for preventing electrostatic breakdown in FIG. 5, it is possible to omit the gate electrode 66b and substitute the metal wiring 68a as shown in FIG.

[0049]

As described above, according to the IC of the present invention,
Even if the drain area of the output transistor becomes smaller due to the miniaturization of the element, it is possible to prevent the electrostatic breakdown withstand capability of the output transistor from being reduced by the surge input from the output pad.

Therefore, even if the element is miniaturized, the electrostatic breakdown withstand amount can be improved without increasing the chip size, the chip cost, the operating speed of the output transistor, and the driving capability. it can.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an output circuit section of a CMOS type IC according to a first embodiment of the present invention.

2 is a cross-sectional view showing an output NMOS transistor and an electrostatic breakdown prevention NMOS transistor in FIG.

FIG. 3 is a cross-sectional view showing an output PMOS transistor and an electrostatic breakdown prevention PMOS transistor in FIG.

FIG. 4 is a cross-sectional view showing a modification of the NMOS transistor for preventing electrostatic breakdown in FIG.

FIG. 5 is an output MOS in an output circuit section of an NMOS type or PMOS type IC according to a second embodiment of the present invention.
FIG. 4 is a cross-sectional view showing an example of a transistor and a MOS transistor for preventing electrostatic breakdown.

FIG. 6 is a circuit diagram showing an example of an output circuit section of a conventional semiconductor integrated circuit.

[Explanation of symbols]

10 ... Internal circuit, 11 ... Output buffer circuit, 12 ... Output pad, P1, N1 ... Output MOS transistor, P
2, N2 ... MOS transistor for electrostatic breakdown protection, 3
1, 41, 51, 61 ... Semiconductor substrate, 32, 42 ... N well, 33a, 43a, 63a ... Source region of output MOS transistor, 33b, 43b, 63b ... Output M
OS transistor drain regions 33c, 43c, 5
3c, 63c ... Drain region of electrostatic breakdown preventing MOS transistor, 34, 44, 54, 64 ... Gate insulating film,
35, 45, 55, 65 ... Field oxide film, 36a,
46a, 66a ... Gate electrodes of output MOS transistors, 36b, 46b, 66b ... Gate electrodes of electrostatic breakdown prevention MOS transistors, 37, 47, 57, 67 ... Interlayer insulating films, 38a, 48a, 68a ... Output wiring, 38
b, 48b, 68b ... Source wiring of output MOS transistor, 39, 49, 69 ... Protective film, 62 ... Diffusion layer region of different conductivity type.

Claims (5)

[Claims] 1. A CMOS type output circuit, an output pad connected to an output node of the output circuit, a gate and a source connected to the output node of the output circuit, and a substrate region having a power supply potential node or a ground potential node. And a drain connected to the semiconductor substrate and the well region, and a MOS transistor for electrostatic breakdown protection having a gate insulating film formed to have a threshold voltage higher than an integrated circuit power supply voltage. A characteristic semiconductor integrated circuit. 2. A MOS type output circuit, an output pad connected to an output node of the output circuit, a gate and a source connected to the output node of the output circuit, and a substrate region having a power supply potential node or a ground potential node. MOS transistor for electrostatic breakdown protection having a gate insulating film formed so that the drain voltage is connected to the semiconductor substrate through a diffusion layer of different conductivity type and the threshold voltage is higher than the integrated circuit power supply voltage. And a semiconductor integrated circuit. 3. The semiconductor integrated circuit according to claim 1, wherein the gate insulating film of the electrostatic breakdown protection MOS transistor has a threshold voltage lower than an integrated circuit power supply voltage.
A semiconductor integrated circuit, which is thicker than a gate insulating film of an S transistor. 4. The semiconductor integrated circuit according to claim 1, wherein a gate insulating film of the MOS transistor for electrostatic breakdown protection is a field oxide film. 5. The semiconductor integrated circuit according to claim 1, wherein the gate electrode of the MOS transistor for electrostatic breakdown protection is formed of a metal wiring, and the gate insulating film of this MOS transistor is a field oxide film and its A semiconductor integrated circuit characterized in that an interlayer insulating film formed above the metal wiring is used.