JPH02125342U

JPH02125342U -

Info

Publication number: JPH02125342U
Application number: JP3415789U
Authority: JP
Priority date: 1989-03-23
Filing date: 1989-03-23
Publication date: 1990-10-16

Description

[Brief explanation of drawings]

第１図ａは本考案の第一実施例の入力回路ブロ
ツクを示す平面図。第１図ｂはそのＸ−Ｘ′断面
図。第２図はその回路図。第３図は本考案の第一
実施例を示す平面図。第４図ａ，ｂ，ｃおよびｄ
は本考案の第一実施例と従来例の入力回路ブロツ
クの入出力信号を示すパルス波形図。第５図ａは
本考案の第二実施例の入力回路の要部を示す平面
図。第５図ｂはそのＹ−Ｙ′断面図。第６図は従
来例を示す平面図。第７図はその基本セルの一例
を示す平面図。第８図はその基本セルの回路図。
第９図は従来例の入力回路ブロツクを示す平面図
。第１０図はその回路図。１……半導体基板、２ａ，２ａ_１……入力回路
ブロツク、２ｂ……出力回路ブロツク、３……基
本セル、４……電源パツド、５……接地パツド、
６……入力信号パツド、７，９，１５，１８……
接続孔、８……抵抗体層、１０……入力保護回路
、１１，１３，１４，１７，２２……引出し線、
１２……入力バツフア、１６……電源線、１９…
…接地線、２０……誘電体層、２１……下層導体
層、３０……入力端子、３１……抵抗、３２，３
３……ダイオード、３４……電源（ＶＤＤ）、３
５，３６……Ｐｃｈトランジスタ、３７，３８…
…Ｎｃｈトランジスタ、３９……コンデンサ、４
１……Ｐ^＋型拡散層、４２……第一Ｐｃｈゲート
電極層、４３……第二Ｐｃｈ電極層、４４……Ｐ
型島拡散層、４５……Ｎ^＋型拡散層、４６……第
一Ｎｃｈゲート電極層、４７……第二Ｎｃｈゲー
ト電極層。 FIG. 1a is a plan view showing an input circuit block according to a first embodiment of the present invention. FIG. 1b is a sectional view taken along the line X-X'. Figure 2 is its circuit diagram. FIG. 3 is a plan view showing the first embodiment of the present invention. Figure 4 a, b, c and d
1 is a pulse waveform diagram showing input and output signals of input circuit blocks of the first embodiment of the present invention and a conventional example; FIG. FIG. 5a is a plan view showing the main parts of an input circuit according to a second embodiment of the present invention. FIG. 5b is a sectional view taken along the Y-Y' line. FIG. 6 is a plan view showing a conventional example. FIG. 7 is a plan view showing an example of the basic cell. FIG. 8 is a circuit diagram of the basic cell.
FIG. 9 is a plan view showing a conventional input circuit block. Figure 10 is its circuit diagram. 1... Semiconductor substrate, 2a, 2a ₁ ... Input circuit block, 2b... Output circuit block, 3... Basic cell, 4... Power pad, 5... Ground pad,
6...Input signal pad, 7, 9, 15, 18...
Connection hole, 8...Resistor layer, 10...Input protection circuit, 11, 13, 14, 17, 22...Leader line,
12...Input buffer, 16...Power line, 19...
...Grounding wire, 20...Dielectric layer, 21...Lower conductor layer, 30...Input terminal, 31...Resistance, 32,3
3...Diode, 34...Power supply (VDD), 3
5, 36...Pch transistor, 37, 38...
...Nch transistor, 39...Capacitor, 4
1... P ⁺ type diffusion layer, 42... First Pch gate electrode layer, 43... Second Pch electrode layer, 44... P
Type island diffusion layer, 45...N ⁺ type diffusion layer, 46... First Nch gate electrode layer, 47... Second Nch gate electrode layer.

Claims

[Claims for Utility Model Registration] A semiconductor substrate comprising a plurality of input circuit blocks and an output circuit block disposed around the outer periphery of a semiconductor substrate, and a plurality of basic cells regularly disposed in an inner region, the input In a standard cell type semiconductor integrated circuit, the circuit block includes an input signal pad into which an input signal is input, and a resistor layer whose one end is connected to the input signal pad via a connection hole. A dielectric layer provided below the input signal pad, a lower conductor layer provided opposite the input signal pad with this dielectric layer in between, and the other end of the lower conductor layer and the resistor layer. A semiconductor integrated circuit characterized by comprising: a leader line that connects the semiconductor integrated circuit;