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JPH01130534U - - Google Patents

Info

Publication number
JPH01130534U
JPH01130534U JP1988027678U JP2767888U JPH01130534U JP H01130534 U JPH01130534 U JP H01130534U JP 1988027678 U JP1988027678 U JP 1988027678U JP 2767888 U JP2767888 U JP 2767888U JP H01130534 U JPH01130534 U JP H01130534U
Authority
JP
Japan
Prior art keywords
pad electrode
thin film
metal thin
wiring
circuit group
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1988027678U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1988027678U priority Critical patent/JPH01130534U/ja
Publication of JPH01130534U publication Critical patent/JPH01130534U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案に係る半導体装置の第１の実施
例を示す平面図、第２図は第１図の―線断面
図、第３図は第１図の―線断面図、第４図は
パツド電極およびダミーパツド電極上にそれぞれ
プローブを立てた場合の等価回路図、第５図は第
２の実施例装置の平面図、第６図は第５図の―
線断面図、第７図は第５図の―線断面図、
第８図は第２の実施例装置においてパツド電極お
よびダミーパツド電極上にプローブを立てた場合
の等価回路図、第９図および第１０図は本考案に
係わる半導体装置の他の実施例を示す模式図、第
１１図は従来例における半導体装置を示す平面図
、第１２図は第１１図の―線断面図であ
る。 １……Ｓｉ基板、２……フイールド酸化膜、３
……モート部、４……ゲート酸化膜、５……ゲー
ト電極、６……層間絶縁膜、７……コンタクトホ
ール、８……パツド電極、９……パツド配線、２
０……ダミーパツド電極、２１……ダミーパツド
配線、２２……第２層間絶縁膜、２３……第２の
金属配線。 1 is a plan view showing a first embodiment of a semiconductor device according to the present invention, FIG. 2 is a cross-sectional view taken along the line -- in FIG. 1, FIG. 3 is a cross-sectional view taken along the line -- in FIG. 1, and FIG. is an equivalent circuit diagram when probes are set up on the pad electrode and the dummy pad electrode, respectively, FIG. 5 is a plan view of the device of the second embodiment, and FIG.
Line sectional view, Figure 7 is a - line sectional view of Figure 5,
FIG. 8 is an equivalent circuit diagram when a probe is set up on a pad electrode and a dummy pad electrode in the device of the second embodiment, and FIGS. 9 and 10 are schematic diagrams showing other embodiments of the semiconductor device according to the present invention. 11 is a plan view showing a conventional semiconductor device, and FIG. 12 is a sectional view taken along the line -- in FIG. 1...Si substrate, 2...Field oxide film, 3
...Moat part, 4...Gate oxide film, 5...Gate electrode, 6...Interlayer insulating film, 7...Contact hole, 8...Padded electrode, 9...Padded wiring, 2
0...Dummy pad electrode, 21...Dummy pad wiring, 22...Second interlayer insulating film, 23...Second metal wiring.

Claims (1)

【実用新案登録請求の範囲】 半導体基板上に、少なくとも１つの素子を有す
る回路群と、 上記回路群と外部回路との接点となるパツド電
極と、 上記回路群とパツド電極とを接続する金属薄膜
配線と、 を備えてなる半導体装置において、 上記パツド電極および金属薄膜配線と同一の平
面形状および断面形状を有するダミーパツド電極
およびダミー金属薄膜配線を、少なくとも１組付
設したことを特徴とする半導体装置。[Claims for Utility Model Registration] A circuit group having at least one element on a semiconductor substrate, a pad electrode that serves as a contact point between the circuit group and an external circuit, and a metal thin film that connects the circuit group and the pad electrode. Wiring; A semiconductor device comprising at least one set of a dummy pad electrode and a dummy metal thin film wiring having the same planar shape and cross-sectional shape as the pad electrode and the metal thin film wiring.
JP1988027678U 1988-03-02 1988-03-02 Pending JPH01130534U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1988027678U JPH01130534U (en) 1988-03-02 1988-03-02

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1988027678U JPH01130534U (en) 1988-03-02 1988-03-02

Publications (1)

Publication Number Publication Date
JPH01130534U true JPH01130534U (en) 1989-09-05

Family

ID=31250375

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1988027678U Pending JPH01130534U (en) 1988-03-02 1988-03-02

Country Status (1)

Country Link
JP (1) JPH01130534U (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03125430A (en) * 1989-10-11 1991-05-28 Mitsubishi Electric Corp Integrated circuit device and manufacture thereof
JPH06310560A (en) * 1993-04-23 1994-11-04 Toko Inc Semiconductor device and manufacture thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03125430A (en) * 1989-10-11 1991-05-28 Mitsubishi Electric Corp Integrated circuit device and manufacture thereof
JPH06310560A (en) * 1993-04-23 1994-11-04 Toko Inc Semiconductor device and manufacture thereof

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