JPH02102727U - - Google Patents
Info
- Publication number
- JPH02102727U JPH02102727U JP1090189U JP1090189U JPH02102727U JP H02102727 U JPH02102727 U JP H02102727U JP 1090189 U JP1090189 U JP 1090189U JP 1090189 U JP1090189 U JP 1090189U JP H02102727 U JPH02102727 U JP H02102727U
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- wiring layer
- metal wiring
- semiconductor device
- impurities
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000002184 metal Substances 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 2
- 239000012535 impurity Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Weting (AREA)
Description
第１図〜第３図は本考案に係る半導体装置の実
施例を示す図で、第１図は要部断面図、第２図は
金属配線層を形成した状態の要部断面図、第３図
は金属配線層をエツチング処理した状態の要部断
面図、第４図〜第６図は従来の半導体装置を示す
図で、第４図は要部断面図、第５図は金属配線層
を形成した状態の要部断面図、第６図は金属配線
層をエツチング処理した状態の要部断面図である
。
１，１１……半導体基板、２，１２……ベース
領域、３，１３……エミツタ領域、４，７，１４
……酸化膜、１５，１９……絶縁膜、５，６，８
，１６，１７，２０……金属配線層。
1 to 3 are views showing an embodiment of a semiconductor device according to the present invention, in which FIG. 1 is a cross-sectional view of the main part, FIG. 2 is a cross-sectional view of the main part with a metal wiring layer formed, and FIG. The figure is a cross-sectional view of the main part after the metal wiring layer has been etched, and Figures 4 to 6 are diagrams showing a conventional semiconductor device. FIG. 6 is a cross-sectional view of the main part after the metal wiring layer has been etched. 1, 11... Semiconductor substrate, 2, 12... Base region, 3, 13... Emitter region, 4, 7, 14
... Oxide film, 15, 19 ... Insulating film, 5, 6, 8
, 16, 17, 20...metal wiring layer.
Claims (1)
が形成され、該酸化膜上に金属配線層が形成され
てなる半導体装置において、該酸化膜と該金属配
線層間に絶縁膜が介在されてなる構成の半導体装
置。 In a semiconductor device in which an oxide film containing a high concentration of impurities is formed on a semiconductor substrate and a metal wiring layer is formed on the oxide film, an insulating film is interposed between the oxide film and the metal wiring layer. Configuration of semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1090189U JPH02102727U (en) | 1989-01-31 | 1989-01-31 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1090189U JPH02102727U (en) | 1989-01-31 | 1989-01-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02102727U true JPH02102727U (en) | 1990-08-15 |
Family
ID=31218973
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1090189U Pending JPH02102727U (en) | 1989-01-31 | 1989-01-31 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02102727U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015070100A (en) * | 2013-09-27 | 2015-04-13 | 富士電機株式会社 | Silicon carbide semiconductor device manufacturing method |
-
1989
- 1989-01-31 JP JP1090189U patent/JPH02102727U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015070100A (en) * | 2013-09-27 | 2015-04-13 | 富士電機株式会社 | Silicon carbide semiconductor device manufacturing method |