JPH01255252A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device having a bump to be effectively manufactured with high yield reliability by forming an intermediate metal layer on an interconnection layer exposed in the first window of a protective layer, forming an etching mask layer having a second window for exposing the metal layer thereon, and placing the bump on the second window. CONSTITUTION:A semiconductor chip 1, an interconnection layer 2 formed on the chip 1, a protective layer 3 formed on the layer 2 and having a first window 7 for exposing the layer 2 at a predetermined place, an intermediate metal layer 4 covering the layer 2 in the window 7 and extending on the layer 3, an etching mask layer 6 formed on the layer 4 and having a second window 8 for exposing the layer 4, and a bump 5 to be placed on the layer 4 in the window 8 are provided. For example, the layer 2 is formed of aluminium alloy such as aluminium, Al-Si, etc., and the layer 4 is preferably formed of a multilayer of a metal layer preferably operating as a barrier for diffusion and a metal layer for improving the bonding strength of the bump to be placed on the metal layer.

Description

[Detailed Description of the Invention] , [Summary] Regarding a semiconductor device in which metal bumps (protrusions) are formed on a semiconductor chip for mounting, and a method for manufacturing the same, the bumps can be reliably manufactured with high yield and reliability. Semiconductor device 111
1, a semiconductor chip; a wiring layer formed on the semiconductor chip; a protective layer formed on the wiring layer and having a first window exposing the wiring layer at a predetermined location; v! an etching mask layer that is formed on the intermediate metal layer and has a second window that exposes the intermediate metal layer; bumps placed on the intermediate metal layer; and nitric acid.

[Industrial application field]

The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device in which metal bumps (protrusions) are formed on a semiconductor chip for mounting, and a method for manufacturing the same.

[Conventional technology]

In semiconductor devices such as semiconductor integrated circuits, in order to make the circuit formed on the semiconductor chip connectable to the outside, 51
1! equipment is required.

Wire bonding, in which wires are used to connect a dangling pad f of a wiring layer provided on the periphery of a semiconductor chip, a lead frame, etc., is widely used as a mounting technique. A wire, usually made of gold or the like, is passed through the capillary and thermocompressed to the bonding pad and the end of the lead frame. As the degree of integration of semiconductor devices increases and the number of wires increases, problems arise in wire bonding. One wire bonding
Therefore, as the number of bonds increases, the time required for the bonding process becomes longer and the throughput deteriorates. Furthermore, the maximum number of bonding pads that can be formed on the periphery of a semiconductor chip is limited by the outer periphery of the chip, the outer diameter of the capillary used for bonding, and other factors. There is also a limit to the minimum width that can be achieved at the leading end of the lead frame. As the number of terminals increases, the distance from the semiconductor chip must be increased in order to maintain a constant spacing between the leads of the lead frame.

This makes it easier for the bonding wire to flow during transfer molding.

Tough (T) is a mounting technology that replaces wire bonding.
A B tape automated bond
There is ingl technology. Inner lead wiring is formed on the tape, aligned on the semiconductor chip, and pressed down from above to perform multiple bonding simultaneously. Therefore, even if the number of terminals increases, the time required for bonding does not essentially increase. Also, compared to lead frames, it is easier to deal with an increase in the number of terminals because it does not use a capillary 4 and the inner lead width on the tape can be made thinner.

Another technique is the 7.Ace down bonding technique in which a semiconductor chip is directly bonded onto a wiring board. In this case, the boding pads can be formed not only in the periphery of the semiconductor chip but also in a wide area, making it easier to cope with an increase in the number of terminals.

In these bonding techniques that do not use boding wire gold, gold, steel,
Metal bumps such as solder are used.

FIG. 4A shows a structure in which bumps are formed on bonding pads of a wiring layer of a semiconductor chip.

A bonding pad is formed on a semiconductor chip 1 at the end of a wiring layer 2 made of aluminum or aluminum alloy, and a window 7 is opened in a protective layer 3 above the bonding pad. Ponting pad wiring layer 2
An intermediate metal layer 4 is formed thereon which acts as a barrier against metal interdiffusion, and metal bumps 5 are formed thereon.

The bumps 5 are formed by forming the intermediate metal layer 4 over the entire surface of the semiconductor chip, forming a plating mask such as photoresist, and performing selective plating. After the bumps 5 are formed, the plating mask is removed, and the intermediate metal layer 4 is etched using the bumps 5 as a mask. In this etching, the intermediate metal layer 4 may be etched to the inside of the bump 5 due to side etching. If the etching progresses too much, the aluminum wiring '42 will be etched as shown in FIG. 4(B). Such overetching causes wire breakage and the like, lowering the yield and reliability of semiconductor devices. Assuming that the bump 5 is approximately the same size as the bonding pad portion of the underlying wiring layer 2, by making the window 7 of the protective layer 3 small, it is possible to prevent the wiring layer 2 from being affected by the etching of the intermediate metal layer 4. . However, since the bumps 5 have an unnecessary size, material is wasted and the adhesion strength is also reduced.

In addition, during bonding, the pressure applied from above prevents the 11Ml around the window 7 as shown in No. 41ffi (C).
13 may cause a crack. If the cracks reach the wiring layer 2 or the semiconductor surface, the performance and reliability of the semiconductor device will deteriorate due to the intrusion of moisture and the like.

[The problem that the invention attempts to solve]

Semiconductor devices in which bumps are formed on semiconductor chips have tremendous potential, so it is certain that the yield and reliability will be high.
It has been desired to realize a technology that can manufacture semiconductor devices having bumps.

An object of the present invention is to provide a semiconductor device having bumps that can be manufactured reliably with high yield and reliability.

Another object of the present invention is to provide a method for reliably manufacturing a semiconductor device having bumps with high yield and reliability.

[Means to solve the problem]

forming an intermediate metal layer on the bonding pad of the wiring layer on the semiconductor chip exposed by the first window of the protective layer;
An etching mask layer is formed thereon, which is made of a material that serves as a mask for etching the intermediate metal layer, and has a second window that exposes the intermediate metal layer, and a metal bang is formed on the second window.

[For production]

The etching mask layer on the intermediate metal layer acts as a mask during etching of the intermediate metal layer, resulting in an over-etching effect. can be prevented.

The etching mask layer on the intermediate metal layer can act as a mechanical buffer against the pressure during bonding, and can prevent cracks in the protective layer on the semiconductor chip.

〔Example〕

FIG. 1 shows the manufacturing process of a semiconductor device having bumps.

Referring to FIG. 1(A), a wiring layer 2 is formed on a semiconductor chip 1 on which a circuit is formed, and the ends of the wiring layer 2 form bonding pads. The protective layer 3 covers the wiring layer 2,
The first window 7 exposes the bonding pad of wiring)-2. An intermediate metal layer 4 is formed on the exposed wiring layer 2 and protective layer 3, which acts as a barrier against metal interdiffusion and improves bump adhesion. An etching mask layer 6 is formed on the intermediate metal layer 4, which can act as a mask against etching when the intermediate metal layer 4 is etched.

The etching mask layer 6 has a second window 8 and has a portion extending outward from the bumps to be placed thereon.

Similar to the configuration of FIG. 4(A) according to the prior art, in this embodiment, when the distance between the outer edge of the bump 5 and the edge of the window 7 of the protective layer 3 is 5 to 10 μm, the distance between the window 7 and the bump 5 is Furthermore, by setting the distance from the window 7 to the outer edge of the etching stopper layer 6 to about 15-20/1 m, damage to the wiring layer 2 due to overetching can be prevented.

The wiring layer 2 can be made of aluminum or an aluminum alloy such as Al/Si, and the intermediate metal layer 4 preferably has a bonding strength (adhesion) between the metal layer that acts as a barrier against diffusion and the bumps placed thereon. It is composed of multiple layers with layers of metal that improve the quality. For example each layer 2000-30
Make the thickness 0OA.

When the bump is made of gold or the like, metals that act as a barrier include titanium, tungsten, titanium alloys, tungsten alloys, and the like. Metals for promoting adhesion include paladium, platinum, copper, and the like. If the bumps are solder, the intermediate metal layer 4 is made of, for example, dikel or titanium-copper-nickel. The protective layer 3 is a material that can stabilize the semiconductor surface and the wiring layer 2, and is made of, for example, phosphosilicate glass (PSG).
It is a membrane with J-hydrogenated Noricon. The etching stopper layer 6 is made of oxides such as duric oxide, phosphoric acid glass, etc.
It can be made of an insulator such as nitride/recon, a nitride such as aluminum nitride, an oxynitride such as silicon oxynitride, a resin such as polyimide, or a conductor such as indium tin oxide (ITO) or titanium nitride. It is preferable to use one that can be prepared at low temperatures. For example, it is made of a silicon nitride CVD film with a thickness of 2000 to 300 OA.

Next, referring to FIG. 1(B), a plating mask layer 9 is formed to cover the surface other than the portion where the bump 5 is to be formed. The bonding pad portion of the wiring layer 2 is exposed. Intermediate metal layer 4 is plated with gold. Bumps 5 are created by plating as electrodes. The plating mask layer 9 can be made of photoresist or the like. For example, it is made of photoresist with a thickness of 30 μm. The bumps 5 can be made of gold, copper, solder, or the like. In the case of gold bumps, the thickness is, for example, 20-30 μm, and in the case of solder, the thickness is, for example, several hundred μm. Next, referring to the first example (C), after the bump 5 is plated, a mask layer is formed. Remove 9. During plating, the intermediate metal layer 4, which also served as a plating electrode, is etched using the etching mask layer 6 as a mask. For example, the intermediate metal layer 4 made of titanium-palladium is etched using hydrochloric acid.
Wet etching is performed using a mixture of nitric acid and hydrofluoric acid. Of course, not only wet etching but also dry etching may be performed.

The dimensions of the etching mask layer 6 can be freely determined separately from the dimensions of the bumps 5. Therefore, the dimensions are designed so that this etching process sufficiently acts as a mask and the intermediate metal layer 4 is not over-etched.

Since overetching of the intermediate metal layer 4 can be effectively prevented, the underlying wiring layer 2 can be prevented from being damaged in the etching process.

If excessive force is applied from above during bonding, the etching mask layer 6 is the first to be affected. However, even if a crack occurs in the etching mask layer 6 that reaches the surface of the intermediate metal layer 4, the wiring layer 2 is sufficiently protected and will not be affected by moisture in the outside air.

FIG. 2 shows a configuration that is even more resistant to pressure. The bonding pad part of wiring layer 2! ! The first window 7 is formed thick, and the bump 5t is formed so as to fit inside the first window 7. Preferably, the dimensions of the bump 5 are selected so that the bump 5 is located inside the edge of the window 7 to the extent that the influence of the chip portion of the protective layer 3 is eliminated. Shows paulownia gold forming 5. A wiring y#2 is formed on the semiconductor chip 1, a 143 ft-thick wiring is formed on it, and a first window 7
The process up to the point where it is fully opened is the same as in the case of FIGS. 1 and 2. The intermediate metal layer 4 extends from the first window 7 to the a-retention layer 3.
It extends over the top of the bump 5 to the part where the bump 5 is to be formed. The bump 5 is formed completely outside the window 7, preferably where the intermediate metal layer 4 extends flat. An etching mask layer 6 is formed on the intermediate gold W4 layer 4, and a second window 8t is formed in a portion away from the first window 7. Since the bump 5 can be created by completely removing the stepped portion of the wiring layer 2, it is possible to prevent cracks from occurring that reach the wiring r*2 due to stress during bonding.

〔Effect of the invention〕

The etching mask layer, which can be freely designed separately from the bump, can effectively prevent over-etching of the intermediate metal layer and prevent damage to the wiring layer.

A buffer against the application of pressure can be constructed, and accidents caused by cracks during bonding can be effectively prevented.

[Brief explanation of the drawing]

Fig. 1 is a partial cross-sectional view of a semiconductor device showing the manufacturing process of a semiconductor device having bumps, Fig. 2 is a partial cross-sectional view of a semiconductor device in which bumps are formed smaller than the windows in the protective layer, and Fig. 3 is a partial cross-sectional view of a semiconductor device in which bumps are formed smaller than the windows in the protective layer. FIG. 4 is a cross-sectional view of a semiconductor device having bumps formed outside the window. FIG. 4 is a cross-sectional view of a semiconductor device having bumps according to the prior art. Explanation of symbols 1 Semiconductor chip 2 Wiring layer 3 Protective layer 4 Intermediate metal layer 5 Bump 6 Etching mask layer 7 First window of protective layer 8 Second window of etching mask layer 9 Plating mask layer 1,000'2 container 8 CC) Etching hammer and a chihiro body device a required number 1 Figure nit J smaller brochure.堠 2 Tsugi DX et al. Jaw view 5 Figure (A) α product (8) Membrane shape 11 scratches (
C) A pot shaving cook sub-method ml knee Juru hamf. prison 4 diagram

Claims (2)

[Claims] (1) A semiconductor chip (1), a wiring layer (2) formed on the semiconductor chip, and a first wiring layer formed on the wiring layer and exposing the wiring layer at a predetermined location.
a protective layer (3) having a window (7), and an intermediate metal layer (4) covering the wiring layer in the first window and extending on the protective layer.
), an etching mask layer (6) formed on the intermediate metal layer and having a second window (8) exposing the intermediate metal layer; (2) a bump (
5) A semiconductor device comprising: Forming a wiring layer (2) on a semiconductor chip (1), and forming a protective layer (3) that covers the wiring layer and has a first window (7) that exposes the wiring layer at a predetermined location. forming the intermediate metal layer (4) on the first window and the protective layer; and forming a material on the intermediate metal layer that serves as a mask against etching of the intermediate metal layer. , a second layer exposing the intermediate metal layer
forming an etching mask layer (6) having a window (8) and having a larger outer shape than a bump to be formed later; and a bump (5) placed on the intermediate metal layer with the second window. ) and etching the intermediate metal layer using the etching mask layer as a mask.