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JP4740536B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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JP4740536B2
JP4740536B2 JP2003395150A JP2003395150A JP4740536B2 JP 4740536 B2 JP4740536 B2 JP 4740536B2 JP 2003395150 A JP2003395150 A JP 2003395150A JP 2003395150 A JP2003395150 A JP 2003395150A JP 4740536 B2 JP4740536 B2 JP 4740536B2
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semiconductor device
intermediate layer
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bonding pad
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JP2004128513A (en
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仲谷吾郎
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Rohm Co Ltd
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Description

本発明は、半導体装置およびその製造方法に関し、特に、ボンディングパッド周辺のパッシベーションに関する。   The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to passivation around a bonding pad.

ＶＬＳＩ（超大規模集積回路）等の半導体装置を製造する際に、ボンディングパッド周辺および電極パッド上に形成されるバンプ周辺のパッシベーション構造は極めて重要であり、信頼性を維持しつつ生産性の向上を図るために種々の努力がなされている。   When manufacturing a semiconductor device such as a VLSI (very large scale integrated circuit), the passivation structure around the bonding pad and the bump formed on the electrode pad is extremely important, and it is possible to improve productivity while maintaining reliability. Various efforts have been made to achieve this.

近年、ポリイミド樹脂をパッシベーション膜に用いた構造が、種々提案されている。その一例として、図２１に示すように、半導体基板１表面、あるいは前記半導体基板表面に形成された配線層にコンタクトするように形成されたアルミニウム層からなる電極パッド２と、この上層を覆う窒化シリコン膜３に形成されたコンタクトホールＨ内に中間層４としてのＴｉＷ層を介して金のボンディングパッド５を形成したものがある。この金のボンディングパッド５の周りには、パッシベーション膜としてのポリイミド樹脂膜７が形成されている。   In recent years, various structures using a polyimide resin as a passivation film have been proposed. As an example thereof, as shown in FIG. 21, an electrode pad 2 made of an aluminum layer formed so as to contact the surface of the semiconductor substrate 1 or a wiring layer formed on the surface of the semiconductor substrate, and silicon nitride covering the upper layer In some cases, a gold bonding pad 5 is formed in a contact hole H formed in the film 3 through a TiW layer as an intermediate layer 4. A polyimide resin film 7 as a passivation film is formed around the gold bonding pad 5.

ところで、この構造は以下に示すような製造工程を経て形成される。   By the way, this structure is formed through the following manufacturing process.

まず、素子領域の形成されたシリコン基板１表面に配線層（図示せず）および層間絶縁膜（図示せず）を形成し、フォトリソグラフィにより、スルーホール（図示せず）を形成する。この後、アルミニウム層を蒸着し、フォトリソグラフィにより、配線（図示せず）および電極パッド２をパターニングする。そしてこの上層に窒化シリコン膜３を形成し、フォトリソグラフィにより、パターニングし、電極パッド２の周縁は窒化シリコン膜で覆われるように電極パッド２の中央部にコンタクトホールを形成する。（図２２）   First, a wiring layer (not shown) and an interlayer insulating film (not shown) are formed on the surface of the silicon substrate 1 where the element region is formed, and a through hole (not shown) is formed by photolithography. Thereafter, an aluminum layer is deposited, and wiring (not shown) and the electrode pad 2 are patterned by photolithography. Then, a silicon nitride film 3 is formed as an upper layer and patterned by photolithography, and a contact hole is formed at the center of the electrode pad 2 so that the periphery of the electrode pad 2 is covered with the silicon nitride film. (Fig. 22)

この後、図２３に示すように、パッシベーション膜としてのポリイミド樹脂膜７を形成し、これをパターニングすることにより、図２４に示すように、電極パッド２を露呈せしめる。   Thereafter, as shown in FIG. 23, a polyimide resin film 7 as a passivation film is formed and patterned to expose the electrode pad 2 as shown in FIG.

そしてアルミニウム層が表面に露呈していると腐蝕しやすいため、図２５に示すように、この上層にスパッタリング法によりバリア層となるチタンタングステンＴｉＷ膜を中間層４として形成した後、ボンディングパッドとなる金層５を形成する。   Since the aluminum layer is easily corroded when exposed on the surface, a titanium tungsten TiW film serving as a barrier layer is formed as an intermediate layer 4 on the upper layer by sputtering as shown in FIG. A gold layer 5 is formed.

この後、図２６に示すように、フォトリソグラフィにより、この金層５および中間層４をパターニングする。
従って、パッド層５の端縁とポリイミド樹脂膜７の端縁とが一致するのが望ましいが、マスク精度を考慮すると、一致させるのは難しいという問題がある。一方、パッシベーション膜７上に金層５および中間層４がのりあげるとショートなどの問題が生じ易いという問題がある。このため、フォトリソグラフィの精度を考慮して、パターニングがなされる。 Thereafter, as shown in FIG. 26, the gold layer 5 and the intermediate layer 4 are patterned by photolithography.
Therefore, it is desirable that the edge of the pad layer 5 and the edge of the polyimide resin film 7 coincide with each other. On the other hand, when the gold layer 5 and the intermediate layer 4 are lifted on the passivation film 7, there is a problem that a problem such as a short circuit easily occurs. For this reason, patterning is performed in consideration of the accuracy of photolithography.

このため、パッシベーション膜を構成するポリイミド樹脂膜とパッド層５との間に隙間が生じることになり、酸化され易いＴｉＷが露呈することになり、腐蝕が生じ易く、パッシベーション効果を良好に発揮し得ず、信頼性が低下するという問題がある。   For this reason, a gap is generated between the polyimide resin film constituting the passivation film and the pad layer 5, and TiW that is easily oxidized is exposed, and corrosion is likely to occur. However, there is a problem that reliability is lowered.

このように、従来のパッド構造では、パッシベーション膜とボンディングパッド層との間の隙間から、水分などが侵入し、アルミニウムなどの電極パッドに腐蝕が生じ易く、信頼性を維持するのが困難であるという問題があった。   As described above, in the conventional pad structure, moisture or the like enters from the gap between the passivation film and the bonding pad layer, and the electrode pad such as aluminum is easily corroded, and it is difficult to maintain the reliability. There was a problem.

この発明は、前記実情に鑑みてなされたもので、水分に対する耐性が高く信頼性の高いパッシベーション構造をもつボンディングパッドを有する半導体装置を提供することを目的とする。   The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor device having a bonding pad having a highly reliable passivation structure that is highly resistant to moisture.

本発明の第１では、所望の素子領域の形成された半導体基板と、前記半導体基板表面、あるいは前記半導体基板表面に形成された配線層にコンタクトするように形成された電極パッドと、前記電極パッドの端縁を覆う窒化シリコン膜と、前記電極パッド表面に中間層を介して形成された金層からなるボンディングパッドとを含み、前記ボンディングパッドと前記中間層との界面が側壁に露呈しないように、前記ボンディングパッドの周縁を覆い、前記窒化シリコン膜上に形成された樹脂絶縁膜とを含むことを特徴とする。 In the first aspect of the present invention, a semiconductor substrate on which a desired element region is formed, an electrode pad formed so as to contact the surface of the semiconductor substrate or a wiring layer formed on the surface of the semiconductor substrate, and the electrode pad And a bonding pad made of a gold layer formed on the surface of the electrode pad via an intermediate layer so that the interface between the bonding pad and the intermediate layer is not exposed to the side wall. the not covering the peripheral edge of the bonding pad, characterized in that it comprises a resin insulating film formed on the silicon nitride film.

かかる構成によれば、樹脂絶縁膜が、前記ボンディングパッドの周縁を覆うように、形成されているため、下地の電極パッドや中間層が露呈することなく、樹脂絶縁膜で被覆されており信頼性の向上を図ることが可能となる。
なおここで中間層とはＴｉＷのようなバリアメタル層あるいは密着性層あるいは、めっきの下地を構成する下地層等を含むものとする。そしてこれらが腐食性あるいは酸化され易い材料である場合に特に本発明は有効である。 According to such a configuration, since the resin insulating film is formed so as to cover the periphery of the bonding pad, the underlying electrode pad and the intermediate layer are covered with the resin insulating film without exposing, and the reliability is improved. Can be improved.
Here, the intermediate layer includes a barrier metal layer such as TiW or an adhesive layer, or a base layer constituting a base of plating. The present invention is particularly effective when these are corrosive or easily oxidized materials.

望ましくは、前記樹脂絶縁膜はポリイミド樹脂膜であることを特徴とする。   Preferably, the resin insulating film is a polyimide resin film.

かかる構成によれば、ポリイミド樹脂膜を用いることにより、ボンディングパッド周縁の表面の絶縁とパッシベーション効果を備えた信頼性の高いパッド構造を得ることが可能となる。また形成が容易である。   According to this configuration, by using the polyimide resin film, it is possible to obtain a highly reliable pad structure having insulation and a passivation effect on the peripheral surface of the bonding pad. Moreover, formation is easy.

望ましくは、前記樹脂絶縁膜は、前記ボンディングパッドおよび前記中間層の端縁を覆うように形成されていることを特徴とする。   Preferably, the resin insulating film is formed so as to cover an edge of the bonding pad and the intermediate layer.

かかる構成によれば、信頼性の高いボンディングパッド構造を得ることが可能となる。   According to such a configuration, a highly reliable bonding pad structure can be obtained.

望ましくは、前記中間層はチタンタングステン（ＴｉＷ）層を含むことを特徴とする。   Preferably, the intermediate layer includes a titanium tungsten (TiW) layer.

かかる構成によれば、チタンタングステン（ＴｉＷ）層は特に酸化され易く界面が露呈していると劣化を招き易いという欠点があるが、本発明によれば、容易に信頼性の高いバンプ構造を得ることが可能となる。   According to such a configuration, the titanium tungsten (TiW) layer has a drawback that it is easily oxidized and easily deteriorates when the interface is exposed. According to the present invention, a highly reliable bump structure is easily obtained. It becomes possible.

望ましくは、前記電極パッドは、アルミニウムを含む金属膜からなることを特徴とする。   Preferably, the electrode pad is made of a metal film containing aluminum.

アルミニウム層は特に酸化され易く界面が露呈していると劣化を招き易いという欠点があるが、かかる構成によれば、容易に信頼性の高いパッド構造を得ることが可能となる。   The aluminum layer has a drawback that it is particularly easily oxidized and easily deteriorates if the interface is exposed. According to such a configuration, a highly reliable pad structure can be easily obtained.

望ましくは、前記電極パッドは、銅薄膜であることを特徴とする。   Preferably, the electrode pad is a copper thin film.

銅層は特に酸化され易く界面が露呈していると劣化を招き易いという欠点があるが、かかる構成によれば、容易に信頼性の高いパッド構造を得ることが可能となる。   The copper layer is particularly susceptible to oxidation and has the drawback of easily deteriorating when the interface is exposed. According to such a configuration, it is possible to easily obtain a highly reliable pad structure.

望ましくは、所望の素子領域の形成された半導体基板と、前記半導体基板表面、あるいは前記半導体基板表面に形成された配線層にコンタクトするように形成された第１及び第２の電極パッドと、前記第１及び第２の電極パッドの端縁の周縁を覆う窒化シリコン層と、前記第１の電極パッド表面に中間層を介して形成された金層からなるボンディングパッドと、前記半導体基板上に形成された第２の電極パッド表面に中間層を介して形成されたバンプとを含み、前記ボンディングパッドと前記中間層との界面が側壁に露呈しないように、前記ボンディングパッドの周縁を覆うとともに、前記バンプの側面とともに露呈する、前記バンプと前記中間層との界面を覆うように、少なくとも前記バンプの周辺部および前記ボンディングパッドの周辺部で前記窒化シリコン膜上に形成された樹脂絶縁膜とを含むことを特徴とする。 Preferably, the semiconductor substrate in which a desired element region is formed, the first and second electrode pads formed so as to contact the surface of the semiconductor substrate or a wiring layer formed on the surface of the semiconductor substrate, Formed on the semiconductor substrate, a silicon nitride layer covering the periphery of the edge of the first and second electrode pads, a bonding pad made of a gold layer formed on the surface of the first electrode pad via an intermediate layer, and And a bump formed on the surface of the second electrode pad through an intermediate layer , covering the periphery of the bonding pad so that the interface between the bonding pad and the intermediate layer is not exposed to the side wall, and exposed on the side surface together with the bumps, the said bumps so as to cover the interface with the intermediate layer, at least the peripheral portion and the peripheral of the bonding pads of the bump In characterized in that it comprises a resin insulating film formed on the silicon nitride film.

また本発明の半導体装置は、、複数のバンプを具備しており、これら複数のバンプのうち第１のバンプを介して、他の半導体チップがフェースダウンで接続されており、第２のバンプを介して、ボンディングワイヤの一端が接続されこのボンディングワイヤの他端を介して電気的接続が実現される。   In addition, the semiconductor device of the present invention includes a plurality of bumps, and other semiconductor chips are connected face down through the first bump among the plurality of bumps. Thus, one end of the bonding wire is connected, and electrical connection is realized through the other end of the bonding wire.

かかる構成によれば、ワイヤボンディングと、バンプを用いたダイレクトボンディングとが混在するような半導体装置においても、信頼性の高いパッド構造を提供することが可能となる。   According to this configuration, it is possible to provide a highly reliable pad structure even in a semiconductor device in which wire bonding and direct bonding using bumps are mixed.

本発明の方法は、所望の素子領域の形成された半導体基板表面、あるいは前記半導体基板表面に形成された配線層にコンタクトするように電極パッドを形成する工程と、前記電極パッド表面に窒化シリコン膜を形成する工程と、前記電極パッド表面の一部が露呈するように、前記窒化シリコン膜を開口する工程と、前記電極パッド表面に中間層を形成する工程と、前記中間層表面にボンディングパッドとなるパッド層を金層で形成し、これらをパターニングする工程と、前記ボンディングパッドと前記中間層との界面の側壁が露呈しないように、前記ボンディングパッドと前記中間層のパターンの端縁を覆うように、前記窒化シリコン膜上に、樹脂絶縁膜を形成する工程とを含むことを特徴とする。 The method of the present invention includes a step of forming an electrode pad so as to contact a semiconductor substrate surface on which a desired element region is formed or a wiring layer formed on the semiconductor substrate surface, and a silicon nitride film on the electrode pad surface. forming a, as a part of the electrode pad surface is exposed, a step of opening the mouth of the silicon nitride film, forming an intermediate layer on the electrode pad surface, the bonding pads on the surface of the intermediate layer Forming a pad layer to be a gold layer, patterning these, and covering an edge of a pattern of the bonding pad and the intermediate layer so that a side wall of an interface between the bonding pad and the intermediate layer is not exposed A step of forming a resin insulating film on the silicon nitride film .

かかる構成によれば、パッド層を形成しパターニングしたのち、ポリイミド樹脂膜を形成しているため、パッド周縁を良好に覆うことが可能となる。   According to this configuration, since the polyimide resin film is formed after the pad layer is formed and patterned, the pad periphery can be satisfactorily covered.

望ましくは、前記樹脂絶縁膜を形成する工程は、ポリイミド樹脂膜を塗布する工程を含むことを特徴とする。   Preferably, the step of forming the resin insulating film includes a step of applying a polyimide resin film.

かかる構成によれば、樹脂絶縁膜がポリイミド樹脂膜であるため、形成が容易でかつパッシベーション効果も高い表面構造を得ることが可能となる。   According to this configuration, since the resin insulating film is a polyimide resin film, it is possible to obtain a surface structure that is easy to form and has a high passivation effect.

望ましくは、前記中間層の形成工程は、スパッタリング法によりチタンタングステン（ＴｉＷ）層を形成する工程を含むことを特徴とする。   Preferably, the intermediate layer forming step includes a step of forming a titanium tungsten (TiW) layer by a sputtering method.

チタンタングステン（ＴｉＷ）層は特に酸化され易く界面が露呈していると劣化を招き易いという欠点があるが、かかる構成によれば、容易に信頼性の高いバンプ構造を得ることが可能となる。   The titanium tungsten (TiW) layer has a disadvantage that it is particularly easily oxidized and easily deteriorates when the interface is exposed. With such a configuration, it is possible to easily obtain a highly reliable bump structure.

望ましくは、前記パッド層を形成する工程は金層をスパッタリングにより形成する工程を含むことを特徴とする。   Preferably, the step of forming the pad layer includes a step of forming a gold layer by sputtering.

かかる構成によれば、より効率よく金のボンディングパッドを形成することが可能となる。   According to this configuration, a gold bonding pad can be formed more efficiently.

以上説明してきたように、本発明によれば、樹脂絶縁膜が、前記金層からなるボンディングパッドの周縁を覆うように、形成されているため、下地の電極パッドや中間層が露呈することなく、樹脂絶縁膜で被覆されており、半導体装置の長寿命化および信頼性の向上を図ることが可能となる。   As described above, according to the present invention, since the resin insulating film is formed so as to cover the peripheral edge of the bonding pad made of the gold layer, the underlying electrode pad and the intermediate layer are not exposed. Since it is covered with a resin insulating film, it is possible to extend the life and improve the reliability of the semiconductor device.

また、本発明の方法によれば、パッド層を形成しパターニングしたのち、ポリイミド樹脂膜を形成しているため、パッド周縁を良好に覆うことが可能となり、半導体装置の長寿命化および信頼性の向上を図ることが可能となる。   In addition, according to the method of the present invention, since the polyimide resin film is formed after the pad layer is formed and patterned, the pad periphery can be satisfactorily covered, and the lifetime and reliability of the semiconductor device can be increased. It is possible to improve.

図１は、本発明の第１の実施形態のパッド構造をもつ半導体装置を示す説明図であり、図２乃至図９は、本発明の第１の実施形態による半導体装置の製造工程を示す説明図である。
この構造では、所望の素子領域の形成されたシリコン基板１表面の電極パッド２と、前記電極パッド表面に中間層４としてのチタンタングステン層を介して形成されたボンディングパッド５とを含み、前記ボンディングパッドおよび前記中間層４の周縁から、前記ボンディングパッド端縁に這い上がるように、ポリイミド樹脂膜７からなる樹脂絶縁膜を形成してなることを特徴とする。 FIG. 1 is an explanatory view showing a semiconductor device having a pad structure according to the first embodiment of the present invention, and FIGS. 2 to 9 are explanatory views showing manufacturing steps of the semiconductor device according to the first embodiment of the present invention. FIG.
This structure includes an electrode pad 2 on the surface of the silicon substrate 1 on which a desired element region is formed, and a bonding pad 5 formed on the surface of the electrode pad via a titanium tungsten layer as an intermediate layer 4. A resin insulating film made of a polyimide resin film 7 is formed so as to rise from the peripheral edge of the pad and the intermediate layer 4 to the edge of the bonding pad.

次に本発明の第１の実施形態の半導体装置の製造工程について説明する。
まず、図１に示すように、半導体基板１上にフィールド酸化膜（図示せず）を形成したものを用意し、フィールド酸化膜や半導体基板の上に、ポリシリコンゲートを備えたＭＯＳＦＥＴなどの素子領域を形成する。 Next, the manufacturing process of the semiconductor device according to the first embodiment of the present invention will be described.
First, as shown in FIG. 1, a device in which a field oxide film (not shown) is formed on a semiconductor substrate 1 is prepared, and an element such as a MOSFET having a polysilicon gate on the field oxide film or the semiconductor substrate is prepared. Form a region.

つぎに、この表面を覆うように、層間絶縁膜（図示せず）を形成する。層間絶縁膜は、たとえばＰＳＧ（リンをドーピングしたシリコン酸化膜）やＢＰＳＧ（ボロンおよびリンをドーピングしたシリコン酸化膜）により構成される。つぎに、層間絶縁膜の上に膜厚５００〜１０００ｎｍのアルミ配線を形成する。このようにして半導体基板１上にアルミ配線まで形成した後、これをパターニングし電極パッド２を形成する。
そしてスパッタリング法により窒化シリコン膜３を形成し、前記電極パッド２に開口するように窓を形成する。 Next, an interlayer insulating film (not shown) is formed so as to cover the surface. The interlayer insulating film is made of, for example, PSG (silicon oxide film doped with phosphorus) or BPSG (silicon oxide film doped with boron and phosphorus). Next, an aluminum wiring having a thickness of 500 to 1000 nm is formed on the interlayer insulating film. Thus, after forming even aluminum wiring on the semiconductor substrate 1, this is patterned and the electrode pad 2 is formed.
Then, a silicon nitride film 3 is formed by sputtering, and a window is formed so as to open in the electrode pad 2.

つぎに、図２に示すように、この上にスパッタリング法により膜厚２００ｎｍのＴｉＷ層４を形成した後、膜厚８００ｎｍの金層５を形成する。   Next, as shown in FIG. 2, a 200 nm-thick TiW layer 4 is formed thereon by sputtering, and then a 800 nm-thick gold layer 5 is formed.

そして、図３に示すように、レジストを塗布しフォトリソグラフィによりレジストパターンＲ１を形成する。   Then, as shown in FIG. 3, a resist is applied and a resist pattern R1 is formed by photolithography.

そして、図４に示すように、レジストパターンＲ１をマスクとして金層５のエッチングを行い、さらにこの金層５をマスクとして、ＴｉＷ層４をエッチングする。   Then, as shown in FIG. 4, the gold layer 5 is etched using the resist pattern R1 as a mask, and the TiW layer 4 is etched using the gold layer 5 as a mask.

この後、図５に示すように、レジストパターンＲ１を剥離する。   Thereafter, as shown in FIG. 5, the resist pattern R1 is peeled off.

そして、図６に示すように、感光性のポリイミド樹脂７を塗布する。   Then, as shown in FIG. 6, a photosensitive polyimide resin 7 is applied.

この後、図７に示すように、スクライブライン（図示せず）形成と同時にボンディングパッドに相当する領域のポリイミド樹脂７も除去するように形成したパターンを用いて露光を行う。   Thereafter, as shown in FIG. 7, exposure is performed using a pattern formed so as to remove the polyimide resin 7 in a region corresponding to the bonding pad simultaneously with the formation of a scribe line (not shown).

この後、図８に示すように、３００℃３０分の熱処理によりポリイミド樹脂をポストベークし、膜質の向上をはかる。   Thereafter, as shown in FIG. 8, the polyimide resin is post-baked by a heat treatment at 300 ° C. for 30 minutes to improve the film quality.

そして最後に、図９に示すように、Ｏ2プラズマ処理工程が実施され、表面に残存するポリマーやパーティクル（ごみ）Ｓの除去がなされる。 Finally, as shown in FIG. 9, an O 2 plasma treatment step is performed, and the polymer and particles (dust) S remaining on the surface are removed.

このようにして、図１に示したようなパッド構造を持つ半導体装置が形成される。   In this way, a semiconductor device having a pad structure as shown in FIG. 1 is formed.

かかる構成によれば、ポリイミド樹脂膜７がボンディングパッドの周縁の中間層およびボンディングパッドとの界面を覆うように形成されているため、下地の電極パッド２や中間層４が露呈することなく、良好にポリイミド樹脂膜で被覆保護されており長寿命で信頼性の高いパッド構造を得ることが可能となる。
また、ボンディングパッドを形成した後、ポリイミド樹脂膜７を形成しているため、効率よく良好に界面を被覆することが可能である。 According to such a configuration, since the polyimide resin film 7 is formed so as to cover the interface between the peripheral layer of the bonding pad and the bonding pad, the underlying electrode pad 2 and the intermediate layer 4 are not exposed and are excellent. Further, it is possible to obtain a pad structure having a long life and high reliability because it is covered and protected with a polyimide resin film.
Further, since the polyimide resin film 7 is formed after the bonding pad is formed, the interface can be efficiently and satisfactorily covered.

なお、前記第１の実施形態においては、金のボンディングパッドを形成する場合について説明したが、中間層としてはＴｉ／ＴｉＮなど他の層を用いてもよく、またさらにチタン層やパラジウム層などの密着層を介在させたりすることも可能である。   In the first embodiment, the case where the gold bonding pad is formed has been described. However, as the intermediate layer, other layers such as Ti / TiN may be used. Further, a titanium layer, a palladium layer, or the like may be used. It is also possible to interpose an adhesion layer.

さらにまたパッド電極についてもアルミニウムに限定されることなく、アルミニウム−シリコン（Ａｌ−Ｓｉ）、アルミニウム−シリコン−銅（Ａｌ−Ｓｉ−Ｃｕ）、銅（Ｃｕ）等の場合にも適用可能である。   Furthermore, the pad electrode is not limited to aluminum, but can be applied to aluminum-silicon (Al-Si), aluminum-silicon-copper (Al-Si-Cu), copper (Cu), and the like.

次に本発明の第２の実施形態について説明する。
前記実施形態では、スパッタリング法によってボンディングパッドを形成するパッド構造について説明したが、さらに膜厚を大きくする必要がある場合にはスパッタリング法によって形成した金層上にめっき層を形成し、より膜厚の厚いボンディングパッドを形成することも可能である。図１０乃至図１９は本発明の第２の実施形態の半導体装置の製造工程を示す図である。 Next, a second embodiment of the present invention will be described.
In the above embodiment, the pad structure for forming the bonding pad by the sputtering method has been described. However, when it is necessary to further increase the film thickness, a plating layer is formed on the gold layer formed by the sputtering method, and the film thickness is increased. It is also possible to form a thick bonding pad. 10 to 19 are views showing a manufacturing process of the semiconductor device according to the second embodiment of the present invention.

この方法では、電極パッド２上にスパッタリング法により膜厚２００ｎｍのＴｉＷ層４を形成した後、膜厚２００ｎｍの金層を形成するがこの工程までは前記第１の実施形態で説明した図２の工程までと同様である。   In this method, a 200 nm-thick TiW layer 4 is formed on the electrode pad 2 by sputtering, and then a 200 nm-thick gold layer is formed. Up to this step, the process of FIG. The process is the same as before.

そして、図１１に示すように、レジストを塗布しフォトリソグラフィにより金めっき工程におけるマスクを構成するレジストパターンＲ３を形成する。   Then, as shown in FIG. 11, a resist is applied and a resist pattern R3 constituting a mask in the gold plating process is formed by photolithography.

そして、図１２に示すように、膜厚２〜５ミクロン程度となるように金めっき層５ｔを形成し、ボンディングパッドとなる領域の金の膜厚を大きくする。   Then, as shown in FIG. 12, a gold plating layer 5t is formed so as to have a thickness of about 2 to 5 microns, and the thickness of the gold in the region to be a bonding pad is increased.

さらに、図１３に示すように、レジストパターンＲ３を剥離する。
この後図１４に示すように、表面の金層を軽くエッチングし、めっき層から露呈するスパッタリングで形成した金層５を除去し、ＴｉＷ層を露呈せしめる。 Further, as shown in FIG. 13, the resist pattern R3 is peeled off.
Thereafter, as shown in FIG. 14, the gold layer on the surface is lightly etched, the gold layer 5 formed by sputtering exposed from the plating layer is removed, and the TiW layer is exposed.

そして後図１５に示すように、この金層５ｔをマスクとして、ＴｉＷ層４をエッチングする。   Then, as shown in FIG. 15, the TiW layer 4 is etched using the gold layer 5t as a mask.

そして、図１６に示すように、感光性のポリイミド樹脂７を塗布する。   Then, as shown in FIG. 16, a photosensitive polyimide resin 7 is applied.

この後、図１７に示すように、スクライブライン（図示せず）形成と同時にボンディングパッドに相当する領域のポリイミド樹脂７も除去するように形成したパターンを用いて露光を行う。   Thereafter, as shown in FIG. 17, exposure is performed using a pattern formed so as to remove polyimide resin 7 in a region corresponding to a bonding pad simultaneously with the formation of a scribe line (not shown).

この後、図１８に示すように、３００℃３０分の熱処理によりポリイミド樹脂をポストベークし、膜質の向上をはかる。   Thereafter, as shown in FIG. 18, the polyimide resin is post-baked by a heat treatment at 300 ° C. for 30 minutes to improve the film quality.

そして最後に、図１９に示すように、表面に残存するポリマーやパーティクル（ごみ）を除去するために、Ｏ2プラズマ処理工程が実施される。 Finally, as shown in FIG. 19, an O 2 plasma treatment step is performed to remove the polymer and particles (dust) remaining on the surface.

このようにして、厚いボンディングパッドを有する半導体装置が形成される。   In this way, a semiconductor device having a thick bonding pad is formed.

かかる構成によれば、ボンディングパッドが厚く形成されているため、さらなるボンディング性の向上を図ることが可能となる。このようにしてより長寿命で信頼性の高いパッド構造を得ることが可能となる。   According to such a configuration, since the bonding pad is formed thick, it is possible to further improve the bondability. In this way, it is possible to obtain a pad structure with a longer life and higher reliability.

次に本発明の第３の実施形態について説明する。
前記第１および第２の実施形態では、ワイヤボンディング法により実装される半導体装置について説明したが、図２０に示すように、バンプ６を形成し、ダイレクトボンディング法による接続領域も混在するような構造とすることも可能である。ここではバンプ６に半導体チップ２０がフェースダウンで直接接続されており、両半導体チップ間領域はポリイミド樹脂２１を充填せしめられている。 Next, a third embodiment of the present invention will be described.
In the first and second embodiments, the semiconductor device mounted by the wire bonding method has been described. However, as shown in FIG. 20, the bump 6 is formed and the connection region by the direct bonding method is also mixed. It is also possible. Here, the semiconductor chip 20 is directly connected to the bump 6 face down, and the area between the two semiconductor chips is filled with a polyimide resin 21.

製造に際しては前記第２の実施形態と同様の方法が用いられるが、図１２に示したように金層５ｔをめっき形成した後、ワイヤボンディング領域はレジスト被覆し、バンプを形成すべき領域にのみ再度めっきを施し厚い金めっき層からなるバンプ６を形成する。   In manufacturing, the same method as in the second embodiment is used. However, after the gold layer 5t is formed by plating as shown in FIG. 12, the wire bonding region is coated with a resist, and only the region where the bump is to be formed. Plating is performed again to form a bump 6 made of a thick gold plating layer.

あとは、前記第２の実施形態と同様に形成する。ここで５はボンディングパッドであり、他端をリードフレームなどの実装部材に接続されたボンディングワイヤＷが接続されている。
このようにして極めて容易に信頼性の高い半導体装置を提供することが可能となる、 The rest is formed in the same manner as in the second embodiment. Reference numeral 5 denotes a bonding pad, to which a bonding wire W having the other end connected to a mounting member such as a lead frame is connected.
In this way, it becomes possible to provide a highly reliable semiconductor device very easily.

なお、上述の実施形態においては、下地層として、フィールド酸化膜およびこの上に形成されたアルミ配線とにより構成される下地配線層を例に説明したが、下地層はこれに限定されるものではない。この発明における下地層とは、凹凸状表面を有する層全般を意味するものである。   In the above-described embodiment, the base wiring layer composed of the field oxide film and the aluminum wiring formed thereon is described as an example of the base layer. However, the base layer is not limited to this. Absent. The underlayer in this invention means the whole layer which has an uneven surface.

以上説明してきたように、本発明によれば、樹脂絶縁膜が、前記ボンディングパッドの周縁を覆うように、形成されているため、下地の電極パッドや中間層が露呈することなく、樹脂絶縁膜で被覆されており、半導体装置の長寿命化および信頼性の向上を図ることが可能となることから、ＶＬＳＩに有効に適用可能である。   As described above, according to the present invention, since the resin insulating film is formed so as to cover the periphery of the bonding pad, the resin insulating film is exposed without exposing the underlying electrode pad and the intermediate layer. Since it is possible to extend the life of the semiconductor device and improve the reliability, it can be effectively applied to VLSI.

本発明の第１の実施形態による半導体装置を示す図である。1 is a diagram illustrating a semiconductor device according to a first embodiment of the present invention. 本発明の第１の実施形態による半導体装置の製造工程を示す図である。It is a figure which shows the manufacturing process of the semiconductor device by the 1st Embodiment of this invention. 本発明の第１の実施形態による半導体装置の製造工程を示す図である。It is a figure which shows the manufacturing process of the semiconductor device by the 1st Embodiment of this invention. 本発明の第１の実施形態による半導体装置の製造工程を示す図である。It is a figure which shows the manufacturing process of the semiconductor device by the 1st Embodiment of this invention. 本発明の第１の実施形態による半導体装置の製造工程を示す図である。It is a figure which shows the manufacturing process of the semiconductor device by the 1st Embodiment of this invention. 本発明の第１の実施形態による半導体装置の製造工程を示す図である。It is a figure which shows the manufacturing process of the semiconductor device by the 1st Embodiment of this invention. 本発明の第１の実施形態による半導体装置の製造工程を示す図である。It is a figure which shows the manufacturing process of the semiconductor device by the 1st Embodiment of this invention. 本発明の第１の実施形態による半導体装置の製造工程を示す図である。It is a figure which shows the manufacturing process of the semiconductor device by the 1st Embodiment of this invention. 本発明の第１の実施形態による半導体装置の製造工程を示す図である。It is a figure which shows the manufacturing process of the semiconductor device by the 1st Embodiment of this invention. 本発明の第２の実施形態による半導体装置の製造工程を示す図である。It is a figure which shows the manufacturing process of the semiconductor device by the 2nd Embodiment of this invention. 本発明の第２の実施形態による半導体装置の製造工程を示す図である。It is a figure which shows the manufacturing process of the semiconductor device by the 2nd Embodiment of this invention. 本発明の第２の実施形態による半導体装置の製造工程を示す図である。It is a figure which shows the manufacturing process of the semiconductor device by the 2nd Embodiment of this invention. 本発明の第２の実施形態による半導体装置の製造工程を示す図である。It is a figure which shows the manufacturing process of the semiconductor device by the 2nd Embodiment of this invention. 本発明の第２の実施形態による半導体装置の製造工程を示す図である。It is a figure which shows the manufacturing process of the semiconductor device by the 2nd Embodiment of this invention. 本発明の第２の実施形態による半導体装置の製造工程を示す図である。It is a figure which shows the manufacturing process of the semiconductor device by the 2nd Embodiment of this invention. 本発明の第２の実施形態による半導体装置の製造工程を示す図である。It is a figure which shows the manufacturing process of the semiconductor device by the 2nd Embodiment of this invention. 本発明の第２の実施形態による半導体装置の製造工程を示す図である。It is a figure which shows the manufacturing process of the semiconductor device by the 2nd Embodiment of this invention. 本発明の第２の実施形態による半導体装置の製造工程を示す図である。It is a figure which shows the manufacturing process of the semiconductor device by the 2nd Embodiment of this invention. 本発明の第２の実施形態による半導体装置の製造工程を示す図である。It is a figure which shows the manufacturing process of the semiconductor device by the 2nd Embodiment of this invention. 本発明の第３の実施形態による半導体装置を示す図である。It is a figure which shows the semiconductor device by the 3rd Embodiment of this invention. 従来例の半導体装置を示す図である。It is a figure which shows the semiconductor device of a prior art example. 従来例の半導体装置の製造工程を示す図である。It is a figure which shows the manufacturing process of the semiconductor device of a prior art example. 従来例の半導体装置の製造工程を示す図である。It is a figure which shows the manufacturing process of the semiconductor device of a prior art example. 従来例の半導体装置の製造工程を示す図である。It is a figure which shows the manufacturing process of the semiconductor device of a prior art example. 従来例の半導体装置の製造工程を示す図である。It is a figure which shows the manufacturing process of the semiconductor device of a prior art example. 従来例の半導体装置の製造工程を示す図である。It is a figure which shows the manufacturing process of the semiconductor device of a prior art example.

符号の説明Explanation of symbols

１ シリコン基板
２ 電極パッド
３ 窒化シリコン膜
４ 中間層
５ パッド層
６ バンプ
７ ポリイミド樹脂膜 DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Electrode pad 3 Silicon nitride film 4 Intermediate layer 5 Pad layer 6 Bump 7 Polyimide resin film

Claims (12)

所望の素子領域の形成された半導体基板と、
前記半導体基板表面、あるいは前記半導体基板表面に形成された配線層にコンタクトするように形成された電極パッドと、
前記電極パッドの端縁を覆う窒化シリコン膜と、
前記電極パッド表面に中間層を介して形成された金層からなるボンディングパッドとを含み、
前記ボンディングパッドと前記中間層との界面が側壁に露呈しないように、前記ボンディングパッドおよび前記中間層の端縁の周縁を覆い、前記窒化シリコン膜上に形成された樹脂絶縁膜とを含むことを特徴とする半導体装置。 A semiconductor substrate on which a desired element region is formed;
An electrode pad formed so as to contact the semiconductor substrate surface or a wiring layer formed on the semiconductor substrate surface;
A silicon nitride film covering an edge of the electrode pad;
A bonding pad consisting of a gold layer formed on the surface of the electrode pad via an intermediate layer,
Including a resin insulating film formed on the silicon nitride film and covering a peripheral edge of the edge of the bonding pad and the intermediate layer so that an interface between the bonding pad and the intermediate layer is not exposed to the side wall. A featured semiconductor device. 前記樹脂絶縁膜はポリイミド樹脂膜であることを特徴とする請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein the resin insulating film is a polyimide resin film. 前記中間層は腐食性材料で構成され、前記ボンディングパッドは、前記中間層の端縁を覆うように形成されることを特徴とする請求項１又は２に記載の半導体装置。   The semiconductor device according to claim 1, wherein the intermediate layer is made of a corrosive material, and the bonding pad is formed so as to cover an edge of the intermediate layer. 前記中間層はチタンタングステン（ＴｉＷ）層を含むことを特徴とする請求項１乃至３のいずれかに記載の半導体装置。   The semiconductor device according to claim 1, wherein the intermediate layer includes a titanium tungsten (TiW) layer. 前記電極パッドは、アルミニウムを含む金属膜からなることを特徴とする請求項１乃至４のいずれかに記載の半導体装置。   5. The semiconductor device according to claim 1, wherein the electrode pad is made of a metal film containing aluminum. 前記電極パッドは、銅薄膜であることを特徴とする請求項１乃至４のいずれかに記載の半導体装置。   The semiconductor device according to claim 1, wherein the electrode pad is a copper thin film. 所望の素子領域の形成された半導体基板と、
前記半導体基板表面、あるいは前記半導体基板表面に形成された配線層にコンタクトするように形成された第１及び第２の電極パッドと、
前記第１及び第２の電極パッドの端縁の周縁を覆う窒化シリコン層と、
前記第１の電極パッド表面に中間層を介して形成された金層からなるボンディングパッドと、
前記半導体基板上に形成された第２の電極パッド表面に中間層を介して形成されたバンプとを含み、
前記ボンディングパッドと前記中間層との界面が側壁に露呈しないように、前記ボンディングパッドの周縁を覆うとともに、
前記バンプの側面とともに露呈する、前記バンプと前記中間層との界面を覆うように、少なくとも前記バンプの周辺部および前記ボンディングパッドの周辺部で前記窒化シリコン膜上に形成された樹脂絶縁膜とを含むことを特徴とする半導体装置。 A semiconductor substrate on which a desired element region is formed;
First and second electrode pads formed to contact the semiconductor substrate surface or a wiring layer formed on the semiconductor substrate surface;
A silicon nitride layer covering the periphery of the edge of the first and second electrode pads;
A bonding pad comprising a gold layer formed on the surface of the first electrode pad via an intermediate layer;
A bump formed on the surface of the second electrode pad formed on the semiconductor substrate via an intermediate layer,
Covering the periphery of the bonding pad so that the interface between the bonding pad and the intermediate layer is not exposed to the side wall,
Exposed to together and the side of the bump, the so bumps and cover the interface between the intermediate layer, at least the bump near portion and the bonding pad resin insulating film formed on the silicon nitride film in the peripheral portion of the A semiconductor device comprising: 前記半導体装置は複数のバンプを具備しており、これら複数のバンプのうち第１のバンプを介して、他の半導体チップがフェースダウンで接続されており、
第２のバンプを介して、ボンディングワイヤの一端が接続されこのボンディングワイヤの他端を介して電気的接続が実現される請求項７に記載の半導体装置。 The semiconductor device includes a plurality of bumps, and other semiconductor chips are connected face down through the first bump among the plurality of bumps.
The semiconductor device according to claim 7, wherein one end of the bonding wire is connected via the second bump, and electrical connection is realized via the other end of the bonding wire. 所望の素子領域の形成された半導体基板表面、あるいは前記半導体基板表面に形成された配線層にコンタクトするように電極パッドを形成する工程と、
前記電極パッド上に窒化シリコン膜を形成する工程と、
前記電極パッド表面の一部が露呈するように、前記窒化シリコン膜を開口する工程と、
前記電極パッド表面に中間層を形成する工程と、
前記中間層表面にボンディングパッドとなるパッド層を金層で形成し、これら中間層およびパッド層をパターニングする工程と、
前記ボンディングパッドと前記中間層との界面の側壁が露呈しないように、前記ボンディングパッドと前記中間層のパターンの端縁の周縁を覆うように、前記窒化シリコン膜上に、樹脂絶縁膜を形成する工程とを含むことを特徴とする半導体装置の製造方法。 Forming an electrode pad so as to contact a semiconductor substrate surface on which a desired element region is formed, or a wiring layer formed on the semiconductor substrate surface;
Forming a silicon nitride film on the electrode pad;
As part of the electrode pad surface is exposed, a step of opening the mouth of the silicon nitride film,
Forming an intermediate layer on the electrode pad surface;
Forming a pad layer to be a bonding pad on the surface of the intermediate layer with a gold layer, and patterning the intermediate layer and the pad layer;
A resin insulating film is formed on the silicon nitride film so as to cover a peripheral edge of a pattern of the bonding pad and the intermediate layer so that a sidewall of the interface between the bonding pad and the intermediate layer is not exposed. A method for manufacturing a semiconductor device, comprising: a step. 前記樹脂絶縁膜を形成する工程は、ポリイミド樹脂膜を塗布する工程を含むことを特徴とする請求項９に記載の半導体装置の製造方法。   The method for manufacturing a semiconductor device according to claim 9, wherein the step of forming the resin insulating film includes a step of applying a polyimide resin film. 前記中間層の形成工程は、スパッタリング法によりチタンタングステン（ＴｉＷ）層を形成する工程を含むことを特徴とする請求項９または１０に記載の半導体装置の製造方法。   The method of manufacturing a semiconductor device according to claim 9, wherein the intermediate layer forming step includes a step of forming a titanium tungsten (TiW) layer by a sputtering method. 前記パッド層を形成する工程は金層をスパッタリングにより形成する工程を含むことを特徴とする請求項１１に記載の半導体装置の製造方法。   12. The method of manufacturing a semiconductor device according to claim 11, wherein the step of forming the pad layer includes a step of forming a gold layer by sputtering.
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