JP2001196407A - Semiconductor device and method of forming semiconductor device - Google Patents
Semiconductor device and method of forming semiconductor deviceInfo
- Publication number
- JP2001196407A JP2001196407A JP2000006507A JP2000006507A JP2001196407A JP 2001196407 A JP2001196407 A JP 2001196407A JP 2000006507 A JP2000006507 A JP 2000006507A JP 2000006507 A JP2000006507 A JP 2000006507A JP 2001196407 A JP2001196407 A JP 2001196407A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- package
- bump
- protective material
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H10W72/012—
-
- H10W72/01225—
-
- H10W72/0711—
-
- H10W72/07141—
-
- H10W72/20—
-
- H10W72/234—
-
- H10W72/242—
-
- H10W72/252—
-
- H10W72/552—
-
- H10W74/014—
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
(57)【要約】
【課題】 ウエハ状態でICパッケージを作成し、IC
チップと同じ大きさのICパッケージを提供すること。
【解決手段】 ウエハ状態で電極パッドにバンプを接着
した後で、保護材料を塗布し、バンプ部分を露出させ
る。その後スクライブラインでウエハを切断し、ICパ
ッケージを完成させる。
(57) [Summary] [Problem] To prepare an IC package in a wafer state,
To provide an IC package of the same size as a chip. SOLUTION: After bonding a bump to an electrode pad in a wafer state, a protective material is applied to expose a bump portion. Thereafter, the wafer is cut along a scribe line to complete an IC package.
Description
【0001】[0001]
【発明の属する技術分野】本発明はICチップと同じ大
きさの、いわゆるチップサイズパッケージの構造と、そ
の製造方法に関する。The present invention relates to a structure of a so-called chip size package having the same size as an IC chip, and a method of manufacturing the same.
【0002】[0002]
【従来の技術】これまでに作成されているチップサイズ
パッケージと呼ばれるものは、ICチップを一個に分離
してからICパッケージを作成していた。2. Description of the Related Art In a so-called chip size package which has been manufactured, an IC package is manufactured after separating an IC chip into one.
【0003】[0003]
【発明が解決しようとする課題】ICパッケージの中に
ICを入れるためには、かなりの余裕度を取らねばなら
ず、チップサイズパッケージといいながら、実際のサイ
ズはICチップよりかなり大きくなっていた。また、I
Cパッケージ製造の工程が複雑で長いため費用がかか
り、かつ作成期間が長かった。In order to put an IC in an IC package, a considerable margin must be taken, and the actual size of the IC package is considerably larger than that of an IC chip. . Also, I
The process of manufacturing the C package was complicated and long, so it was expensive and the production period was long.
【0004】[0004]
【課題を解決するための手段】上記の問題点を解決する
ために、本発明はウエハ状態でICパッケージを作成
し、ICチップと同じ大きさのICパッケージを提供す
る。すなわち、ウエハ状態で電極パッドにバンプを接着
した後で、保護材料を塗布し、バンプ部分を露出させ
る。その後スクライブラインでウエハを切断し、ICパ
ッケージを完成させる。SUMMARY OF THE INVENTION In order to solve the above problems, the present invention provides an IC package in a wafer state, and provides an IC package having the same size as an IC chip. That is, after bonding the bumps to the electrode pads in a wafer state, a protective material is applied to expose the bump portions. Thereafter, the wafer is cut along a scribe line to complete an IC package.
【0005】[0005]
【実施例】本発明は、集積回路(IC)チップと同じ大
きさのICパッケージを提供する技術に関するものであ
る。以下に本発明の実施例を図面に基づいて説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention relates to a technique for providing an IC package having the same size as an integrated circuit (IC) chip. Hereinafter, embodiments of the present invention will be described with reference to the drawings.
【0006】図1は、ウエハサイズで形成された本発明
の構造を示すICパッケージの断面図を示す。半導体基
板1の表面に電極パッド2が形成されている。また、半
導体基板1の表面は保護膜3でおおわれている。半導体
基板内には集積回路が形成されている。図1では半導体
基板内の集積回路は省略する。FIG. 1 is a sectional view of an IC package showing a structure of the present invention formed in a wafer size. An electrode pad 2 is formed on a surface of a semiconductor substrate 1. The surface of the semiconductor substrate 1 is covered with a protective film 3. An integrated circuit is formed in a semiconductor substrate. In FIG. 1, the integrated circuit in the semiconductor substrate is omitted.
【0007】以上のようにしてICチップが構成され
る。本発明は、このICチップの電極パッド2にバンプ
4が接着している。バンプ4の形状は図1に示すように
凸形をしている。ICチップの表面は保護材料5で覆わ
れている。An IC chip is configured as described above. In the present invention, the bumps 4 are bonded to the electrode pads 2 of the IC chip. The shape of the bump 4 is convex as shown in FIG. The surface of the IC chip is covered with a protective material 5.
【0008】以上のようなICパッケージは次のような
特徴がある。The above IC package has the following features.
【0009】(1)ICチップと同じ大きさである。(1) It is the same size as an IC chip.
【0010】(2)バンプ4の上で保護材料5で切れて
いるため、ICチップは完全に保護材料でおおわれてい
る。この事により、ICチップヘの外部環境からの異物
の浸入は阻止されている。例えば外部の水分の浸入がな
いため、ICチップの水分による問題である、電極パッ
ドの腐食等は発生しない。(2) Since the bumps 4 are cut by the protective material 5, the IC chip is completely covered with the protective material. This prevents foreign substances from entering the IC chip from the external environment. For example, since there is no intrusion of external moisture, corrosion of the electrode pads, which is a problem due to the moisture of the IC chip, does not occur.
【0011】(3)バンプ4の柱部分4aは保護材料5
より飛び出しているため、外部電極との接続が容易であ
る。この事を図2により説明する。図2(a)は、図1
のウエハサイズで形成されたICパッケージの集合体を
個片にした状態の1個のICパッケージの断面構造図で
ある。図2(b)は、図2(a)のICパッケージを実
装基板に取付けた状態を示す。実装基板16の表面に配
線17が形成されている。配線17とバンプ14の柱部
分14aが接着している。バンプ14の柱部分14aが
保護材料15より飛び出しているため、外部配線17と
の接続が容易となる。(3) The pillar portion 4a of the bump 4 is made of a protective material 5
Since it is more protruding, connection with an external electrode is easy. This will be described with reference to FIG. FIG. 2A shows FIG.
FIG. 4 is a cross-sectional structural view of one IC package in a state where an assembly of IC packages formed with the same wafer size is singulated. FIG. 2B shows a state where the IC package of FIG. 2A is mounted on a mounting board. The wiring 17 is formed on the surface of the mounting board 16. The wiring 17 and the pillar portion 14a of the bump 14 are adhered. Since the pillar portions 14a of the bumps 14 protrude from the protective material 15, the connection with the external wiring 17 is facilitated.
【0012】(4)保護材料5はICチップを強固に保
持しているため、ICパッケージの強度はICチップ単
体の強度に比較し、格段に向上している。(4) Since the protection material 5 firmly holds the IC chip, the strength of the IC package is significantly improved as compared with the strength of the IC chip alone.
【0013】(5)構造が簡単なため、材料費を含めた
製造コストが非常に安い。(5) Since the structure is simple, manufacturing costs including material costs are very low.
【0014】以上のように、本発明によるICパッケー
ジはチップサイズパッケージとして使用できる。As described above, the IC package according to the present invention can be used as a chip size package.
【0015】次に、本発明のICパッケージの製造方法
について詳細に述べる。Next, a method of manufacturing an IC package according to the present invention will be described in detail.
【0016】図3(a)は、ICチップがまだ切断され
ていない段階のウエハ状態を示す図である。ウエハ内に
は多数のICが存在する。21は半導体基板、22は電
極パッド、23は保護膜である。半導体基板21内には
半導体素子が多数形成されている。半導体基板21は、
シリコン(Si)半導体やガリウムひ素などの化合物半
導体、あるいは他の半導体である。電極パッド22の材
料は、アルミニウム(Al)や、アルミニウムの合金
や、不純物元素の入ったアルミニウム。あるいは銅(C
u)や、銅の合金や不純物の入った銅、あるいは他の金
属などである。保護膜23の材料は,シリコン酸化膜
(SiO2)やシリコン窒化膜(SiNx)やポリイミ
ド膜、あるいは他の絶縁膜などである。FIG. 3A is a view showing a wafer state at a stage where an IC chip has not been cut yet. There are many ICs in a wafer. 21 is a semiconductor substrate, 22 is an electrode pad, and 23 is a protective film. Many semiconductor elements are formed in the semiconductor substrate 21. The semiconductor substrate 21
It is a compound semiconductor such as a silicon (Si) semiconductor or gallium arsenide, or another semiconductor. The material of the electrode pad 22 is aluminum (Al), an aluminum alloy, or aluminum containing an impurity element. Or copper (C
u), copper alloys, copper containing impurities, or other metals. The material of the protective film 23 is a silicon oxide film (SiO2), a silicon nitride film (SiNx), a polyimide film, or another insulating film.
【0017】次に図3(b)に示すように、ICが多数
形成されたウエハ状態のままで、電極パッド22にバン
プ24を接着する。Next, as shown in FIG. 3B, the bumps 24 are bonded to the electrode pads 22 in a wafer state in which a large number of ICs are formed.
【0018】図3(c)は、図3(b)の1個の電極パ
ッドを拡大した図である。バンプ24の形状は図3
(c)に示すように凸形の形状をするように形成する。
ひとつの形成方法として、ワイヤボンダー装置を用いる
方法がある。FIG. 3 (c) is an enlarged view of one electrode pad of FIG. 3 (b). The shape of the bump 24 is shown in FIG.
It is formed so as to have a convex shape as shown in FIG.
As one forming method, there is a method using a wire bonder device.
【0019】すなわち図4(a)において、金属線34
の先をワイヤボンディング装置で丸い金属ボール35を
形成する。次に図4(b)に示すように、金属ボール3
5をICの電極パッド32に押し付け、熱圧着か超音波
圧着などの方法により金属ボール35とICの電極パッ
ド32を接着する。次に図4(c)に示すように・金属
線34を適当な長さの所で切断する。以上の事をウエハ
レベルで行うのであるが、ウエハサイズで見ればバンプ
36の高さはばらつきがあるので全体の高さをそろえる
ために、図4(c)の工程の後でべベリングという工程
を加える事もある。That is, in FIG.
Is formed into a round metal ball 35 with a wire bonding apparatus. Next, as shown in FIG.
5 is pressed against the electrode pad 32 of the IC, and the metal ball 35 and the electrode pad 32 of the IC are bonded by a method such as thermocompression bonding or ultrasonic compression bonding. Next, as shown in FIG. 4C, the metal wire 34 is cut at an appropriate length. The above process is performed at the wafer level. However, the height of the bumps 36 varies from the viewpoint of the wafer size. In order to make the overall height uniform, a process called beveling is performed after the process of FIG. May be added.
【0020】バンプ34、35の材料として金(A
u)、パラジウム(Pd)、アルミニウム(Al)、銀
(Ag)、鉛(Pd)と錫(Sn)の半田合金、銀(A
g)と錫(Sn)の合金、その他の金属などがある。Gold (A) is used as a material for the bumps 34 and 35.
u), palladium (Pd), aluminum (Al), silver (Ag), a solder alloy of lead (Pd) and tin (Sn), silver (A
g) and an alloy of tin (Sn) and other metals.
【0021】次に図3(d)に示すように、保護材料2
5を付着する。図3(e)は、図3(d)の1個の電極
部分を拡大した図である。保護材料25は液体状の材料
で、ウエハ全体に塗布する事ができる。塗布した時の液
体状の厚みは、硬化後の最終的な厚みを考慮して決定し
なければならない。すなわちバンプ24の柱部分が充分
に露出し、実装する時に実装基板上の配線と接着する程
度にバンプ24の柱部分を確保できるように、塗布後の
液体状の厚みを調整する。塗布した後で適当な温度でべ
一クして液体状のものを固形化する。このベーク温度を
適度に選ぶことにより材料25は、より安定した保護材
料となり、ICを機械的化学的に強化する。Next, as shown in FIG.
5 is attached. FIG. 3E is an enlarged view of one electrode portion of FIG. 3D. The protective material 25 is a liquid material and can be applied to the entire wafer. The liquid thickness when applied must be determined in consideration of the final thickness after curing. That is, the liquid thickness after application is adjusted so that the pillars of the bumps 24 are sufficiently exposed and the pillars of the bumps 24 are secured to the extent that they adhere to the wiring on the mounting board during mounting. After the application, the liquid is solidified by baking at an appropriate temperature. By appropriately selecting this bake temperature, the material 25 becomes a more stable protective material and mechanically and chemically strengthens the IC.
【0022】これでウエハの中に多数のICパッケージ
が完成したわけであるが、次にこれらをひとつひとつ分
離する工程について述べる。Now that a number of IC packages have been completed in the wafer, the process of separating these ICs one by one will now be described.
【0023】ウエハ内のスクライブラインに沿ってダイ
シング装置を用いて切断し、個々のICパッケージに分
離する。これにより個片のICパッケージが形成され
る。図3ではバンプの柱部分24aの途中に保護材料2
5が来るようにしたが、図5に示すように、バンプの水
平部分より下に保護材料45が来るようにしても良い。The wafer is cut along a scribe line in the wafer by using a dicing apparatus, and separated into individual IC packages. Thereby, an individual IC package is formed. In FIG. 3, the protective material 2 is placed in the middle of the pillar portion 24a of the bump.
5, the protective material 45 may be provided below the horizontal portion of the bump, as shown in FIG.
【0024】[0024]
【発明の効果】以上、説明したようにウエハ状態でIC
パッケージを作成するので、工程が少なくなり、大幅な
費用削減と大幅な納期短縮ができる。As described above, the IC in the wafer state is used as described above.
Since the package is created, the number of processes is reduced, and the cost and the delivery time can be significantly reduced.
【0025】また、凸形バンプを使用し保護材料がバン
プの水平部分を覆っているので、信頼性と品質が非常に
高い。Also, since the bumps are used and the protection material covers the horizontal portions of the bumps, the reliability and quality are very high.
【図1】本発明の半導体装置であるウエハサイズのIC
パッケージの構造を示す図である。FIG. 1 is a wafer-sized IC that is a semiconductor device of the present invention.
FIG. 3 is a diagram illustrating a structure of a package.
【図2】本発明の半導体装置を実装状態を示す図であ
る。FIG. 2 is a diagram showing a mounted state of the semiconductor device of the present invention.
【図3】本発明の半導体装置の製造方法を示す図であ
る。FIG. 3 is a diagram illustrating a method of manufacturing a semiconductor device according to the present invention.
【図4】本発明の半導体装置に用いるバンプを作成する
方法を示す図である。FIG. 4 is a diagram illustrating a method of forming a bump used in the semiconductor device of the present invention.
【図5】本発明の半導体装置の製造方法の他の実施例で
ある。FIG. 5 is another embodiment of the method of manufacturing a semiconductor device according to the present invention.
1、11、21、31、41 半導体基板 2、12、22、32、42 電極パッド 3、13、23、33、43 保護膜 4、14、24、36、44 バンプ 5、15、25、45 保護材料 4a,14a,24a,44a バンプの柱部分 1, 11, 21, 31, 41 Semiconductor substrate 2, 12, 22, 32, 42 Electrode pad 3, 13, 23, 33, 43 Protective film 4, 14, 24, 36, 44 Bump 5, 15, 25, 45 Protective material 4a, 14a, 24a, 44a Column of bump
Claims (5)
の電極パッドに凸形バンプが接着しており、凸形バンプ
の水平部分の一部と柱部分が露出し他の部分は保護材料
でおおわれている事を特徴とする半導体装置。1. A convex bump is adhered to an electrode pad of a semiconductor substrate on which a semiconductor element is formed, and a part of a horizontal part and a pillar part of the convex bump are exposed, and the other part is covered with a protective material. A semiconductor device characterized in that:
している事を特徴とする請求項1記載の半導体装置。2. The semiconductor device according to claim 1, wherein the convex bump pillar portion protrudes from the protective material.
の電極パッドに凸形バンプが接着しており、凸形バンプ
の柱部分が露出し他の部分は保護材料でおおわれている
事を特徴とする半導体装置。3. A convex bump is adhered to an electrode pad of a semiconductor substrate on which a semiconductor element is formed, and a pillar portion of the convex bump is exposed and another portion is covered with a protective material. Semiconductor device.
の電極パッドに凸形バンプが接着しており、凸形バンプ
の水平部分の一部と柱部分が露出し他の部分は保護材料
でおおわれている半導体装置において、半導体基板の中
に半導体素子を形成した後に、半導体素子の電極パッド
にバンプを接着する工程と、半導体素子を保護する材料
を塗布する工程と、前記保護材料を熱処理する工程を含
む事を特徴とする半導体装置の製造方法。4. A convex bump is adhered to an electrode pad of a semiconductor substrate on which a semiconductor element is formed, a part of a horizontal part and a pillar part of the convex bump are exposed, and the other part is covered with a protective material. Forming a semiconductor element in a semiconductor substrate, bonding a bump to an electrode pad of the semiconductor element, applying a material for protecting the semiconductor element, and heat-treating the protective material in the semiconductor device. A method for manufacturing a semiconductor device, comprising:
用いて形成する事を特徴とする請求項4記載の半導体装
置の製造方法。5. The method according to claim 4, wherein the convex bumps are formed using a wire bonding apparatus.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000006507A JP2001196407A (en) | 2000-01-14 | 2000-01-14 | Semiconductor device and method of forming semiconductor device |
| CN01101509A CN1306300A (en) | 2000-01-14 | 2001-01-13 | Semiconductor device and its mfg. method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000006507A JP2001196407A (en) | 2000-01-14 | 2000-01-14 | Semiconductor device and method of forming semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2001196407A true JP2001196407A (en) | 2001-07-19 |
Family
ID=18535025
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000006507A Withdrawn JP2001196407A (en) | 2000-01-14 | 2000-01-14 | Semiconductor device and method of forming semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP2001196407A (en) |
| CN (1) | CN1306300A (en) |
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Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100481415C (en) * | 2004-03-12 | 2009-04-22 | 联华电子股份有限公司 | Chip package and method of manufacturing the same |
| CN100578766C (en) * | 2006-08-29 | 2010-01-06 | 日月光半导体制造股份有限公司 | Manufacturing method of chip package structure |
-
2000
- 2000-01-14 JP JP2000006507A patent/JP2001196407A/en not_active Withdrawn
-
2001
- 2001-01-13 CN CN01101509A patent/CN1306300A/en active Pending
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