JP7530238B2 - Semiconductor optical device and its manufacturing method - Google Patents

Description

The present invention relates to a semiconductor optical element and a method for manufacturing the same.

High-speed response is required for semiconductor optical elements used in optical communications. Reducing parasitic capacitance is an effective way to improve high-speed response. Semiconductor optical elements have pad electrodes for electrical connection to the outside. Pad electrodes have a large area compared to other electrodes, which causes large parasitic capacitance.

JP 2006-32819 A JP 2011-09294 A

Patent document 1 discloses reducing parasitic capacitance by interposing an insulating film between the pad electrode and the passivation film. The insulating film is formed locally, and an extraction electrode is formed from the pad electrode beyond the insulating film. The edge of the insulating film rises sharply, so there is a possibility that the extraction electrode may be cut off. Patent document 2 discloses an insulating layer with a stepped surface, but does not disclose reducing parasitic capacitance by thickening part of the insulating layer.

The present invention aims to reduce the parasitic capacitance of the pad electrode and reduce the possibility of disconnection of the extraction electrode.

(1) The semiconductor optical element according to the present invention comprises a semiconductor substrate, a mesa portion extending in a stripe shape in a first direction and a pedestal portion adjacent to the mesa portion in a second direction perpendicular to the first direction, a compound semiconductor layer on the semiconductor substrate, an additional insulating film having a top surface and a side surface, with an obtuse internal angle between the top surface and the side surface, on the pedestal portion of the compound semiconductor layer, a protruding portion overlapping the additional insulating film, a passivation film covering the compound semiconductor layer and the additional insulating film while avoiding at least a portion of the mesa portion, a mesa electrode on at least a portion of the mesa portion, a pad electrode on the passivation film within the range of the protruding portion, and a lead electrode on the passivation film continuously within and outside the range of the protruding portion, connecting the pad electrode and the mesa electrode, and having a width narrower than that of the pad electrode.

According to the present invention, the parasitic capacitance of the pad electrode is reduced by the presence of the additional insulating film. In addition, the interior angle between the top surface and side surface of the additional insulating film is obtuse, and a convex portion of the passivation film is formed corresponding to this shape, so the possibility of the extraction electrode being cut off can be reduced.

(2) The semiconductor optical element described in (1) may be characterized in that the passivation film includes a first portion that contacts the top surface of the additional insulating film and a second portion that contacts the side surface of the additional insulating film and is lower than the first portion.

(3) The semiconductor optical element described in (2) may be characterized in that the first portion and the second portion are integrally continuous without interruption throughout.

(4) The semiconductor optical element described in (2) may be characterized in that the first portion and the second portion are at least partially separated.

(5) The semiconductor optical element described in (4) may be characterized in that the first portion is completely separated from the second portion and is located within the range of the upper surface of the additional insulating film.

(6) The semiconductor optical element according to any one of (1) to (5) may be characterized in that at least one of the passivation film and the additional insulating film is made of a multi-layer structure.

(7) The semiconductor optical element according to any one of (1) to (6) may be characterized in that the passivation film has a thickness equal to that of the additional insulating film.

(8) The method for manufacturing a semiconductor optical device according to the present invention includes forming a compound semiconductor layer on a semiconductor substrate, the compound semiconductor layer having a mesa portion extending in a stripe shape in a first direction and a pedestal portion adjacent to the mesa portion in a second direction perpendicular to the first direction, forming an additional insulating film on the pedestal portion of the compound semiconductor layer, the additional insulating film having a top surface and a side surface and an obtuse internal angle between the top surface and the side surface, forming a passivation film by chemical vapor deposition, the passivation film having a protrusion that overlaps the additional insulating film and covers the compound semiconductor layer and the additional insulating film while avoiding at least a part of the mesa portion, and forming electrodes, the electrodes including a mesa electrode on at least a part of the mesa portion, a pad electrode on the passivation film within the range of the protrusion, and an extraction electrode that is continuously on the passivation film within and outside the range of the protrusion, connects the pad electrode and the mesa electrode, and is narrower in width than the pad electrode.

According to the present invention, the parasitic capacitance of the pad electrode is reduced by the presence of the additional insulating film. In addition, the interior angle between the top surface and side surface of the additional insulating film is obtuse, and a convex portion of the passivation film is formed corresponding to this shape, so that the possibility of the extraction electrode being cut off can be reduced.

(9) The method for manufacturing a semiconductor optical element described in (8) may be characterized in that in the step of forming the passivation film, the film material is deposited on the upper surface of the additional insulating film so as not to protrude above the side surface.

(10) The method for manufacturing a semiconductor optical element described in (9) may be characterized in that the film material is deposited on the upper surface to form a first portion, and is deposited around the additional insulating film to form a second portion.

(11) The method for manufacturing a semiconductor optical element described in (10) may be characterized in that the step of forming the passivation film is completed at a thickness such that the second portion is not at least partially in contact with the first portion.

(12) The method for manufacturing a semiconductor optical element described in (10) may be characterized in that the process for forming the passivation film is performed until the second portion has a thickness such that the second portion is entirely in contact with the first portion.

(13) The method for manufacturing a semiconductor optical element according to any one of (1) to (12) may be characterized in that at least one of the passivation film and the additional insulating film is formed as a stack of multiple layers.

(14) The method for manufacturing a semiconductor optical element according to any one of (1) to (13) may be characterized in that the passivation film is formed to have a thickness equal to that of the additional insulating film.

(15) The method for manufacturing a semiconductor optical element according to any one of (1) to (14) may be characterized in that the step of forming the additional insulating film includes dry etching.

1 is a plan view of a semiconductor optical device according to a first embodiment. 2 is a cross-sectional view taken along line II-II of the semiconductor optical device shown in FIG. FIG. 3 is an enlarged view of a portion surrounded by a dashed line in FIG. 2 . 5A to 5C are diagrams for explaining a method for manufacturing a semiconductor optical device according to an embodiment. 5A to 5C are diagrams for explaining a method for manufacturing a semiconductor optical device according to an embodiment. 5A to 5C are diagrams for explaining a method for manufacturing a semiconductor optical device according to an embodiment. 5A to 5C are diagrams for explaining a method for manufacturing a semiconductor optical device according to an embodiment. 5A to 5C are diagrams for explaining a method for manufacturing a semiconductor optical device according to an embodiment. 13 is a cross-sectional view of an additional insulating film and a passivation film according to a modified example. FIG. 11 is a cross-sectional view of an additional insulating film and a passivation film according to a comparative example. FIG. FIG. 11 is a plan view of a semiconductor optical device according to a second embodiment. 12 is a cross-sectional view taken along line XII-XII of the semiconductor optical device shown in FIG. 11.

The following describes an embodiment of the present invention in detail with reference to the drawings. Components with the same reference numerals in all the drawings have the same or equivalent functions, and their repeated explanation will be omitted. Note that the size of the figures does not necessarily correspond to the magnification.

[First embodiment]
Fig. 1 is a plan view of the semiconductor optical device according to the first embodiment. Fig. 2 is a cross-sectional view of the semiconductor optical device taken along line II-II of Fig. 1. The semiconductor optical device is a ridge-type semiconductor laser.

[Semiconductor substrate]
The semiconductor optical device has a semiconductor substrate 10. The semiconductor substrate 10 is an n-type InP substrate, a p-type InP substrate, or a semi-insulating semiconductor substrate. A lower electrode 12 (e.g., a cathode) is provided on the back surface of the semiconductor substrate 10. The lower electrode 12 is made of multiple layers (e.g., a three-layer structure of a Ti layer, a Pt layer, and an Au layer).

[Compound semiconductor layer]
The semiconductor optical device has a compound semiconductor layer 14. The compound semiconductor layer 14 is on a semiconductor substrate 10 and is composed of multiple layers. The bottom layer of the multiple layers is a lower cladding layer 16. The lower cladding layer 16 has the same conductivity type (e.g., n-type) as the semiconductor substrate 10. An active layer 18 is on the lower cladding layer 16. The active layer 18 is composed of a multiple quantum well layer and optical confinement layers sandwiching the multiple quantum well layer above and below. An upper cladding layer 20 is on the active layer 18. The conductivity type (e.g., p-type) of the upper cladding layer 20 is opposite to the conductivity type (e.g., n-type) of the semiconductor substrate 10. A diffraction grating is formed between the active layer 18 and the upper cladding layer 20, and other semiconductor layers (e.g., an etching stop layer) may be present. A contact layer 22 is on the upper cladding layer 20.

The upper cladding layer 20 and the contact layer 22 are separated into multiple parts. The compound semiconductor layer 14 has a mesa portion 24 that extends in a stripe shape in the first direction D1. The mesa portion 24 is composed of a part of the upper cladding layer 20 and a part of the contact layer 22. The active layer 18 is located below the mesa portion 24.

The compound semiconductor layer 14 has a pedestal portion 26 adjacent to the mesa portion 24 in the second direction D2 perpendicular to the first direction D1. There is a pedestal portion 26 on each side of the mesa portion 24. One pedestal portion 26 (left side) is larger than the other pedestal portion 26 (right side). The pedestal portion 26 is composed of a part of the upper cladding layer 20 and a part of the contact layer 22. The pedestal portion 26 and the mesa portion 24 are separated by a groove 28.

[Additional insulating film]
3 is an enlarged view of the portion surrounded by the dashed line in FIG. 2. The semiconductor optical device has an additional insulating film 30. The additional insulating film 30 is locally formed on the contact layer 22. The additional insulating film 30 has an upper surface 32 and a side surface 34. The interior angle α between the upper surface 32 and the side surface 34 is an obtuse angle. The additional insulating film 30 has an upper surface 32 smaller than a lower surface 36, and is trapezoidal in cross section. The additional insulating film 30 is on the larger pedestal portion 26 (left side in FIG. 2). The additional insulating film 30 is made of a plurality of laminated layers. The upper layer 38 is, for example, a SiO ₂ film. Since the SiO ₂ film has low adhesion to the compound semiconductor layer 14 (contact layer 22), a PSG (Phosphorus Silicon Glass) film is disposed as the lower layer 40 to ensure adhesion.

[Passivation film]
The semiconductor optical device has a passivation film 42. The passivation film 42 is made of a plurality of laminated layers (e.g., a PSG film and a _SiO2 film). The passivation film 42 has the same thickness as the additional insulating film 30.

The passivation film 42 covers the compound semiconductor layer 14 and the additional insulating film 30, and also covers the inner side surface 44 (e.g., the end surface of the upper cladding layer 20 and the end surface of the contact layer 22) and bottom surface (e.g., part of the top surface of the active layer 18) of the groove 28. The passivation film 42 also covers the side surface of the mesa portion 24, but has an opening to avoid (expose) part of the mesa portion 24 (e.g., the top surface). The top surface of the mesa portion 24 is part of the contact layer 22.

The passivation film 42 has a protruding portion 46 that overlaps the additional insulating film 30. At the protruding portion 46, the passivation film 42 does not contact the compound semiconductor layer 14 (contact layer 22). The passivation film 42 includes a first portion 48 that contacts the upper surface 32 of the additional insulating film 30. The passivation film 42 includes a second portion 50 that contacts the side surface 34 of the additional insulating film 30 and is lower than the first portion 48. The second portion 50 contacts the compound semiconductor layer 14 (contact layer 22). The first portion 48 and the second portion 50 are at least partially separated as shown in FIG. 3. For example, the first portion 48 may be completely separated from the second portion 50 and located within the range of the upper surface 32 of the additional insulating film 30. In that case, the first portion 48 is island-shaped inside the second portion 50. Alternatively, slits may be formed intermittently around the first portion 48.

[Upper electrode]
The semiconductor optical device has an upper electrode 52 (e.g., an anode). The upper electrode 52 may be made of multiple layers (e.g., a three-layer structure of a Ti layer, a Pt layer, and a Au layer) and may have a uniform structure overall. The upper electrode 52 is located on the passivation film 42 and is insulated from the compound semiconductor layer 14 except for a part of it (the mesa portion 24).

The upper electrode 52 has a mesa electrode 54. The mesa electrode 54 extends in the first direction D1. The mesa electrode 54 is located on at least a portion of the mesa portion 24 (a portion not covered by the passivation film 42). The mesa electrode 54 is in contact with and electrically connected to the upper surface (contact layer 22) of the mesa portion 24 through an opening in the passivation film 42.

The upper electrode 52 has a pad electrode 56. The pad electrode 56 is on the larger pedestal portion 26 (left side in FIG. 2). The pad electrode 56 is on the passivation film 42 within the range of the protrusion 46 (or the additional insulating film 30). The pad electrode 56 is a region to which a wire (not shown) is bonded for electrical connection with the outside. The planar shape of the pad electrode 56 may be a circle, a rectangle, a rounded rectangle, or another polygon. The pad electrode 56 has a large area compared to other parts of the upper electrode 52, and therefore has a large parasitic capacitance. However, the passivation film 42 and the additional insulating film 30 made of a material (PSG/SiO ₂ ) with a smaller dielectric constant than a semiconductor are laminated below the pad electrode 56, so that the parasitic capacitance can be reduced.

The upper electrode 52 has an extraction electrode 58. The extraction electrode 58 is continuously on the passivation film 42 within and outside the range of the protrusion 46 (or the additional insulating film 30). The extraction electrode 58 connects the pad electrode 56 and the mesa electrode 54. The connection portion of the extraction electrode 58 and the pad electrode 56 is within the range of the protrusion 46 (or the additional insulating film 30). The connection portion of the extraction electrode 58 and the mesa electrode 54 is outside the protrusion 46 (or the additional insulating film 30). The extraction electrode 58 extends in the second direction D2 and is narrower in width in the first direction D1 than the pad electrode 56.

[Production method]
4 to 8 are diagrams for explaining a method for manufacturing a semiconductor optical device according to an embodiment of the present invention. In this embodiment, in order to manufacture multiple semiconductor optical devices, a semiconductor substrate 10 is prepared in the form of a wafer.

As shown in Fig. 4, the compound semiconductor layer 14 is formed on the semiconductor substrate 10. For the formation, MOCVD (Metal Organic Chemical Vapor Deposition) is applied. More specifically, the lower cladding layer 16, the active layer 18, the upper cladding layer 20, and the contact layer 22 are formed in this order. The upper cladding layer 20 may be formed after forming a diffraction grating (not shown) on the active layer 18. Next, an etching mask 60 is formed from an oxide film such as a _SiO2 film by CVD (Chemical Vapor Deposition).

As shown in FIG. 5, a groove 28 is formed in the compound semiconductor layer 14 by wet etching using a mixture of hydrochloric acid and phosphoric acid. The groove 28 separates the contact layer 22 and the upper cladding layer 20 into a plurality of parts. A mesa portion 24 extending in a stripe shape in the first direction D1 (FIG. 1) is formed between a pair of grooves 28. A pedestal portion 26 is formed next to the mesa portion 24 in the second direction D2 perpendicular to the first direction D1. In the second direction D2, the width of the upper surface of the mesa portion 24 is about 2.0 μm, and the width of the groove 28 is about 10 μm. The etching mask 60 is then removed.

6, an additional insulating film 30 having a thickness of, for example, 0.5 μm is formed on the surface of the compound semiconductor layer 14 (including the inner side surface 44 and the bottom surface of the groove 28) by chemical vapor deposition. The additional insulating film 30 is formed in multiple layers. For example, as shown in FIG. 3, a lower layer 40 is formed from PSG, and an upper layer 38 is formed from _SiO2 .

As shown in Fig. 7, the additional insulating film 30 is dry etched using the resist mask 62. The etchant is _C2F6 . In this way, the additional insulating film 30 is patterned on the pedestal portion 26 of the compound semiconductor layer 14. Since dry etching is applied, the side surface 34 of the additional insulating film 30 becomes as shown in Fig. _3. That is, the interior angle α between the upper surface 32 and the side surface 34 of the additional insulating film 30 is an obtuse angle. The additional insulating film 30 has a quadrangle shape in a plan view. Thereafter, the resist mask 62 is removed.

8, a passivation film 42 is formed by chemical vapor deposition. The passivation film 42 is formed in multiple layers, for example, a lower layer is formed from PSG and an upper layer is formed from _SiO2 . The passivation film 42 is formed so as to cover the compound semiconductor layer 14 and the additional insulating film 30. As a result, the passivation film 42 has a protruding portion 46 that overlaps the additional insulating film 30 and protrudes.

As shown in FIG. 3, the chemical vapor deposition film material is deposited on the upper surface 32 of the additional insulating film 30 so as not to protrude above the side surface 34 of the additional insulating film 30. This is thought to be because the film material deposited on the upper surface 32 of the additional insulating film 30 migrates from the upper surface 32 of the additional insulating film 30 along the side surface 34 onto the contact layer 22.

The film material is deposited on the upper surface 32 to form a first portion 48, and is deposited around the additional insulating film 30 to form a second portion 50. The process of forming the passivation film 42 ends with a thickness such that the second portion 50 is not at least partially in contact with the first portion 48. For example, the passivation film 42 is formed to have a thickness (e.g., 0.5 μm) equal to that of the additional insulating film 30. This can reduce stress on the semiconductor layer.

As shown in FIG. 2, an opening is formed in the passivation film 42 above a portion of the mesa portion 24. Etching is used for the formation. This allows the contact layer 22 to be exposed above the mesa portion 24. Then, as shown in FIG. 1 and FIG. 2, the upper electrode 52 is formed. The upper electrode 52 is formed by forming an electrode film by electron beam evaporation and then etching it. The electrode film is formed of multiple layers (Ti layer, Pt layer, Au layer).

The upper electrode 52 includes a mesa electrode 54 on at least a portion of the mesa portion 24, a pad electrode 56 on the passivation film 42 within the range of the protrusion 46, and an extraction electrode 58 that is continuous on the passivation film 42 within and outside the range of the protrusion 46, connects the pad electrode 56 and the mesa electrode 54, and is narrower than the pad electrode 56.

As shown in FIG. 3, the presence or absence of the additional insulating film 30 creates a step, which can cause the passivation film 42 above it to break. However, because the interior angle α between the top surface 32 and the side surface 34 of the additional insulating film 30 is an obtuse angle, the extraction electrode 58 formed on it slopes gently downward and is not broken.

Then, the semiconductor substrate 10 is polished from the back side until it has the desired thickness, the lower electrode 12 is formed, and after processes such as electrode alloying, the wafer-shaped semiconductor substrate 10 is cut into individual semiconductor optical elements.

[Modification]
9 is a cross-sectional view of the additional insulating film and the passivation film according to the modified example. In the modified example, the process of forming the passivation film 66 is performed until the second portion 70 reaches a thickness that contacts (connects) the first portion 68 as a whole. As a result, the first portion 48 and the second portion 70 are integrally continuous as a whole. Alternatively, the passivation film 66 may be continuous as a whole without any breaks due to an error in the thickness of the additional insulating film 72 and the passivation film 66. Even in such a structure, if the interior angle α between the upper surface 74 and the side surface 76 of the additional insulating film 72 is obtuse, the passivation film 66 is formed so that the surface is gently inclined, and the lead electrode 78 thereon also has a gently inclined shape without any breaks.

[Comparative Example]
10 is a cross-sectional view of the additional insulating film and the passivation film according to the comparative example. In the process of forming the additional insulating film 130, a lower layer 140 (PSG film) and an upper layer 138 ( _SiO2 film) are formed on the entire surface of the compound semiconductor layer 114, and then the additional insulating film 130 is formed by patterning them. When the patterning is performed by wet etching, a recess is formed on the side surface 134 of the additional insulating film 130 by side etching due to the difference in etching rate between the lower layer 140 and the upper layer 138. Therefore, the interior angle β between the upper surface 132 and the side surface 134 of the additional insulating film 130 is an acute angle.

The film material deposited by chemical vapor deposition on the additional insulating film 130 of this shape attempts to migrate onto the contact layer 22, but because the angle between the top surface 132 and the side surface 134 is acute, it is difficult to move along the side surface 134, and the passivation film 142 protrudes from the edge of the top surface 132 of the additional insulating film 130 due to the influence of surface tension. When an extraction electrode 158 is formed on such a passivation film 142, the protruding portion of the passivation film 142 becomes an overhang when the metal film is deposited. As a result, the top portion of the extraction electrode 158 on the additional insulating film 130 and the outer portion are separated and disconnected. Or, even if it is partially connected, the thickness is thin, which may be a factor in the pad electrode peeling off during wire bonding.

If the passivation film 142 is formed to a thickness at least twice that of the additional insulating film 130, the passivation film 142 will be continuous overall, and the extraction electrode 158 will also be continuous. However, if the passivation film 142 is too thick, the stress on the compound semiconductor layer 114 will increase, which is undesirable in terms of characteristics and reliability. Similarly, the connectivity can be improved by making the extraction electrode 158 thicker, but this will increase the stress caused by the metal film, which is undesirable.

Second Embodiment
Fig. 11 is a plan view of a semiconductor optical device according to a second embodiment. Fig. 12 is a cross-sectional view of the semiconductor optical device taken along line XII-XII of Fig. 11. The semiconductor optical device is an electroabsorption modulator and has a buried hetero (BH) structure.

The semiconductor optical device has a semiconductor substrate 210 (e.g., an n-type InP substrate). A lower electrode 212 (e.g., a cathode) is provided on the back surface of the semiconductor substrate 210. The semiconductor optical device has a compound semiconductor layer 214 on the semiconductor substrate 210.

The compound semiconductor layer 214 has a mesa portion 224 extending in a stripe shape in the first direction D1 (optical axis direction). The mesa portion 224 is formed by stacking an active layer 218, a cladding layer 216, and a contact layer 222 in this order from the semiconductor substrate 210. The active layer 218 is an optical confinement layer sandwiching a multiple quantum well layer above and below, and functions here as an absorption layer.

The compound semiconductor layer 214 has a pedestal portion 226 adjacent to the mesa portion 224 in the second direction D2 perpendicular to the first direction D1. The pedestal portion 226 is on each side of the mesa portion 224 and is a buried layer of the mesa portion 224. In other words, the pedestal portion 226 is in contact with the side surface of the mesa portion 224. One pedestal portion 226 (left side in FIG. 11) is larger than the other pedestal portion 226 (right side in FIG. 11). The pedestal portion 226 has an inclined surface 264 adjacent to the upper surface of the mesa portion 224. The lower end of the inclined surface 264 is adjacent to the upper surface of the mesa portion 224. The inclined surface 264 is inclined so as to become higher in the direction away from the mesa portion 224.

Details of the additional insulating film 230 are as described in the first embodiment. The passivation film 242 has a protruding portion 246 that overlaps the additional insulating film 230. The passivation film 242 covers the compound semiconductor layer 214 (the upper surface of the pedestal portion 226) and the additional insulating film 230. The passivation film 242 does not cover the mesa portion 224 (as a whole), and does not cover the inclined surface 264 of the pedestal portion 226. Other details of the passivation film 242 are as described in the first embodiment.

On the passivation film 242 is an upper electrode 252 (e.g., an anode). The upper electrode 252 has a uniform structure (e.g., a three-layer structure of a Ti layer, a Pt layer, and an Au layer) overall. The mesa electrode 254 is on at least a portion (e.g., the entire upper surface) of the mesa portion 224 and is in contact with the mesa portion 224 (contact layer 222). The mesa electrode 254 extends in the first direction D1 (the direction in which the mesa portion 224 extends). The end of the mesa portion 224 in the width direction (second direction D2) may be in contact with the inclined surface 264 of the pedestal portion 226. The pad electrode 256 is on the passivation film 242 (or above the additional insulating film 230) within the range of the protrusion 246. The pad electrode 256 is above the larger pedestal portion 226 (left side in FIG. 11). Other details of the pad electrode 256 are as described in the first embodiment.

The extraction electrode 258 is continuously located on the passivation film 242 within and outside the range of the protrusion 246, connects the pad electrode 256 and the mesa electrode 254, and is narrower in width than the pad electrode 256. A portion of the extraction electrode 258 is located on the inclined surface 264 of the pedestal portion 226 and may be in contact with the inclined surface 264. Other details of the extraction electrode 258 are as described in the first embodiment.

The present invention is not limited to the above-described embodiment, and various modifications are possible. For example, the configuration described in the embodiment can be replaced with a substantially identical configuration, a configuration that provides the same action and effect, or a configuration that can achieve the same purpose.

REFERENCE SIGNS LIST 10 semiconductor substrate, 12 lower electrode, 14 compound semiconductor layer, 16 lower cladding layer, 18 active layer, 20 upper cladding layer, 22 contact layer, 24 mesa portion, 26 pedestal portion, 28 groove, 30 additional insulating film, 32 upper surface, 34 side surface, 36 lower surface, 38 upper layer, 40 lower layer, 42 passivation film, 44 inner surface, 46 convex portion, 48 first portion, 50 second portion, 52 upper electrode, 54 mesa electrode, 56 pad electrode, 58 extraction electrode, 60 etching mask, 62 resist mask, 66 passivation film, 68 first portion, 70 second portion, 72 additional insulating film, 74 upper surface, 76 side surface, 78 extraction electrode, 114 compound semiconductor layer, 130 additional insulating film, 132 upper surface, 134 Side surface, 138 upper layer, 140 lower layer, 142 passivation film, 158 extraction electrode, 210 semiconductor substrate, 212 lower electrode, 214 compound semiconductor layer, 216 cladding layer, 218 active layer, 222 contact layer, 224 mesa portion, 226 pedestal portion, 230 additional insulating film, 242 passivation film, 246 protrusion, 252 upper electrode, 254 mesa electrode, 256 pad electrode, 258 extraction electrode, 264 inclined surface, D1 first direction, D2 second direction.

Claims (9)

A semiconductor substrate;
a compound semiconductor layer on the semiconductor substrate, the compound semiconductor layer having a mesa portion extending in a stripe shape in a first direction and a pedestal portion adjacent to the mesa portion in a second direction perpendicular to the first direction;
an additional insulating film having a top surface and a side surface, the interior angle between the top surface and the side surface being an obtuse angle, the additional insulating film being located on the pedestal portion of the compound semiconductor layer;
a passivation film having a protruding portion overlapping the additional insulating film and covering the compound semiconductor layer and the additional insulating film while avoiding at least a portion of the mesa portion;
a mesa electrode overlying at least a portion of the mesa portion;
a pad electrode located on the passivation film within the range of the protrusion;
a lead electrode that is continuously disposed on the passivation film within and outside the range of the protrusion, connects the pad electrode and the mesa electrode, and is narrower than the pad electrode;
having
the passivation film includes a first portion in contact with the top surface of the additional insulating film and a second portion in contact with the side surface of the additional insulating film and lower than the first portion;
The first portion and the second portion are at least partially separated . 2. The semiconductor optical device according to claim 1 ,
The first portion is completely separated from the second portion and is located within the range of the upper surface of the additional insulating film. 3. The semiconductor optical device according to claim 1 ,
At least one of the passivation film and the additional insulating film is made of a plurality of laminated layers. 4. The semiconductor optical device according to claim 1,
The passivation film has a thickness equal to that of the additional insulating film. forming a compound semiconductor layer on a semiconductor substrate, the compound semiconductor layer having a mesa portion extending in a stripe shape in a first direction and a pedestal portion adjacent to the mesa portion in a second direction perpendicular to the first direction;
forming an additional insulating film on the pedestal portion of the compound semiconductor layer, the additional insulating film having a top surface and a side surface, the interior angle between the top surface and the side surface being an obtuse angle;
forming a passivation film by chemical vapor deposition, the passivation film having a protruding portion overlapping the additional insulating film and covering the compound semiconductor layer and the additional insulating film while avoiding at least a part of the mesa portion; and
forming an electrode;
Including,
forming the passivation film to include a first portion in contact with the top surface of the additional insulating film and a second portion in contact with the side surface of the additional insulating film and lower than the first portion;
forming the first portion and the second portion to be at least partially separated;
The method for manufacturing a semiconductor optical element, wherein the electrodes include a mesa electrode on at least a portion of the mesa portion, a pad electrode on the passivation film within the range of the convex portion, and an extraction electrode that is continuously on the passivation film within and outside the range of the convex portion, connects the pad electrode and the mesa electrode, and is narrower than the pad electrode. A method for manufacturing a semiconductor optical device according to claim 5 , comprising the steps of:
A method for manufacturing a semiconductor optical device, wherein in the step of forming the passivation film, a film material is deposited on the upper surface of the additional insulating film so as not to protrude above the side surfaces of the additional insulating film. A method for manufacturing a semiconductor optical device according to claim 5 or 6 , comprising the steps of:
At least one of the passivation film and the additional insulating film is formed of a plurality of laminated layers. A method for manufacturing a semiconductor optical device according to any one of claims 5 to 7 , comprising the steps of:
The method for manufacturing a semiconductor optical device further comprises forming the passivation film so as to have a thickness equal to that of the additional insulating film. A method for manufacturing a semiconductor optical device according to any one of claims 5 to 8 , comprising the steps of:
A method for manufacturing a semiconductor optical device, wherein the step of forming the additional insulating film includes dry etching.

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