JP3129284B2 - Method for manufacturing semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

It relates to a semiconductor integrated circuit device the invention BACKGROUND OF THE INVENTION relates to manufacturing <br/> manufacturing method of a semiconductor integrated circuit device which is particularly capacitors formed above the semiconductor elements formed on a semiconductor substrate.

[0002]

2. Description of the Related Art Generally, when a target circuit is formed in a semiconductor integrated circuit device, it is sometimes required to form an active element and a passive element on a semiconductor substrate.
In this case, is the capacitor (capacitor) configured to utilize capacitance generated between a semiconductor substrate and a wiring layer formed thereon or between a plurality of wiring layers having a laminated structure on the semiconductor substrate? Used. In such a semiconductor integrated circuit device, a large-capacity capacitor may be required. In such a case, a pair of electrodes constituting a capacitor is formed on a passivation film on a semiconductor substrate in order to satisfy a required capacitance. Forming is being done. FIG.
FIG. 1 is a cross-sectional view showing an example thereof. A required element is formed on a semiconductor substrate 111, and an interlayer insulating film 112 and required signal wiring 113 and power supply wiring 114 are formed on the semiconductor substrate 111. Further, a passivation film 115 is deposited so as to cover the wirings, a lower electrode 116 is formed on the passivation film 115, and an upper electrode 118 is further formed thereon via a capacitor insulating film 117. The electrode 119, the capacitor insulating film 117, and the upper electrode 118 form a capacitor 119. Here, a bonding pad 120 is formed on a part of the conductive film constituting the lower electrode 116, and an uppermost passivation film 125 is formed on the entire surface.

In the above-mentioned conventional semiconductor integrated circuit device,
The lower electrode 116 and the upper electrode 118 constituting the capacitor 119 are formed over a plane region covering the signal wiring 113 so as to satisfy required capacitance. Therefore, the lower electrode 116 and the signal wiring 113 are opposed to each other with the passivation film 115 interposed therebetween, and a capacitor using the passivation film 115 as a capacitance insulating film is parasitic. Therefore, in the signal wiring 113, a wiring capacitance is increased by a parasitic capacitance generated between the signal wiring 113 and the lower electrode 116, a signal transmission speed on the signal wiring 113 is reduced, and a semiconductor integrated circuit device capable of high-speed operation is realized. Would be difficult to do.

[0004] In order to reduce the parasitic capacitance between the electrodes and wirings which are vertically arranged oppositely via an insulating film, an air bridge structure has been conventionally proposed. For example, in Japanese Patent Application Laid-Open No. 7-193125, in order to reduce the capacitance between wirings that are three-dimensionally crossed with each other, a hollow structure is used between the wirings, and the capacitance between the crossing wirings is reduced by utilizing the low dielectric constant of air. We are trying to reduce it. In Japanese Patent Application Laid-Open No. 5-343543, a space is formed between a wiring formed on a semiconductor substrate and a power supply wiring extending over the wiring to reduce the parasitic capacitance between the two wirings.

[0005]

However, in the above-described conventional air bridge structure, since the upper wiring has a bridge structure as a structure for providing a cavity between wirings that are three-dimensionally crossed on the semiconductor substrate, the mechanical structure is difficult. There is a problem in terms of typical strength. In particular, according to the technique disclosed in the latter publication, the wiring in the upper layer is supported only by the electrical connection portion, so that when the wiring length is long, the intermediate portion is easily deformed, and the reliability is lacking. In this regard, the technique disclosed in the former publication is effective in preventing deformation of the intermediate portion because a plurality of portions of the wiring are supported by the insulating film. However,
Since this configuration is a technology that selectively leaves the supporting insulating film at the same time as forming the wiring, if the electrode is formed over a large area such as a capacitor, the lower side of the lower electrode of the capacitor It is difficult to form a cavity in the cavity, and it is difficult to apply the cavity.

An object of the present invention is to provide an air gap between an electrode constituting a capacitor and a wiring formed on a semiconductor substrate, thereby making it possible to reduce a parasitic capacitance between the electrode and the wiring. An object of the present invention is to provide a method for manufacturing a semiconductor integrated circuit device.

[0007]

According to the present invention, there is provided a semiconductor device comprising:
A passivation film is formed on the formed semiconductor substrate.
And a lower electrode and a capacitive insulator on the passivation film.
Semiconductor with a capacitor in which the membrane and upper electrode are sequentially stacked
A method for manufacturing a semiconductor integrated circuit device, comprising:
Forming a passivation film on the substrate;
Solution film selectively etched to required area
Forming a plurality of recessed grooves at intervals;
Stopper insulating film is formed on the surface of the solution film and the groove.
Process and the stopper insulating film in the concave groove are etched.
Embedding a material having a selectivity ratio,
A lower electrode on the surface of the membrane and the buried material;
Forming a capacitor by forming an insulating film and upper electrode
And selectively etch the material embedded in the groove.
Removing step.

In another method for manufacturing a semiconductor integrated circuit device according to the present invention, a step of forming a passivation film on the semiconductor substrate and a step of selectively etching the passivation film to a required region are performed. forming a plurality of grooves at intervals, wherein the process is a passivation film <br/> embedding the certain etching selectivity material, the passivation film and the surface of the embedded material in said groove The method includes a step of forming a capacitor by forming a lower electrode, a capacitor insulating film, and an upper electrode thereon, and a step of selectively etching and removing a material embedded in the concave groove .

As described above, by arranging a plurality of air gaps in the passivation film immediately below the lower electrode of the capacitor, the region in which the air gap is formed is replaced with a cavity in the passivation film immediately below the lower electrode. The substantial area of the passivation is reduced, and the dielectric constant of the entire passivation film is reduced. For this reason, the parasitic capacitance between the lower electrode and the signal wiring is reduced, the signal transmission speed in the signal wiring is improved,
The semiconductor integrated circuit device can operate at high speed. Further, since the lower electrode is supported by the passivation film in a region other than the air gap, the mechanical strength is not reduced, and the semiconductor device is configured as a highly reliable semiconductor integrated circuit device.

[0010]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a plan view of an embodiment of the present invention and a sectional view taken along line AA of the embodiment. Various semiconductor elements not shown are formed on the main surface of the semiconductor substrate 11, an interlayer insulating film 12 is formed thereon, and a plurality of signal wirings 13 are formed.
The power supply wiring 14 is formed in a required pattern.
A passivation film 15 made of a silicon oxide film is applied so as to cover the signal wiring 13 and the power wiring 14, and a lower electrode 16 made of a metal film such as aluminum is formed on the passivation film 15 in a required pattern. A capacitor insulating film 17 made of a silicon oxide film or a silicon nitride film is formed thereon, and an upper electrode 18 made of a metal film such as aluminum is formed thereon so as to face the lower electrode 16. The lower electrode 16, the capacitor insulating film 17, and the upper electrode 1
8, a capacitor 19 is formed. Further, a bonding pad 20 is formed of a part of the metal film constituting the lower electrode 16. Further, through holes 21 and 22 are opened in the passivation film 15,
The lower electrode 16 and the upper electrode 18 are connected to the GND forming the power wiring 14 through the through holes 21 and 22.
The wiring is connected to the wiring and the VDD wiring, respectively. In the passivation film 15 in a region immediately below the lower electrode 16, a concave groove having a striped planar shape is formed, and an air gap 23 hollowed by the concave groove is formed. In this embodiment, a silicon nitride film 24 is formed on the surface of the air gap 23. An uppermost passivation film 25 is formed on the upper electrode 18.

According to this structure, since the region where the air gap 23 is formed in the passivation film 15 immediately below the lower electrode 16 is formed of a cavity, that is, an air layer, the area where the passivation film exists is reduced. As a result, the dielectric constant of the entire passivation film 15 is reduced. Therefore, the parasitic capacitance between the lower electrode 16 and the signal wiring 13 is reduced, the signal transmission speed in the signal wiring is improved, and a semiconductor integrated circuit device that can operate at high speed can be obtained. By the way, the air gap 23
When the width is set to m, the parasitic capacitance can be reduced by about 30%. On the other hand, in this structure, the lower electrode 16 is supported by the passivation film 15 in a region other than the air gap 23 because the lower surface thereof is in contact with the surface of the passivation film 15.
The lower electrode 16 and the capacitor 19 are configured as a highly reliable semiconductor integrated circuit device without a decrease in mechanical strength.

2 to 4 are views showing a method of manufacturing the semiconductor integrated circuit device of FIG. 1 in the order of steps. In each of the drawings, (a) is a plan view, and (b) is a sectional view taken along the line BB. First, as shown in FIGS. 2A and 2B, the semiconductor substrate 1
1, a semiconductor element (not shown) is formed, and an interlayer insulating film 12, a power supply wiring 13, and a signal wiring 14 are formed thereon, and a passivation film 15 is formed so as to cover these wirings.
To form Next, a photoresist film 30 is formed on the passivation film 15.
Are opened in a stripe shape. Then, by selectively etching the passivation film 15 using the photoresist 30 as a mask, the passivation film 15 is removed.
Then, a groove 31 having a stripe shape is opened.

Next, as shown in FIGS. 3A and 3B, a thin silicon nitride film 24 as a stopper insulating film is formed on the passivation film 15, and B
A PSG film 32 is applied to cover the groove 31. afterwards,
The BPSG film 32 is etched back to flatten the surface so that the BPSG film 3 is formed only inside the concave groove 31.
Leave 2. At this time, the silicon nitride film 24 remains on the passivation film 15.

Next, as shown in FIGS. 4A and 4B, through holes 21 and 22 are opened at required portions of the passivation film 15 using a photoresist (not shown), and an aluminum film is deposited. The lower electrode 16 is formed by forming this into a required pattern. At the same time, a part of the aluminum film forms a bonding pad 2.
0 is formed. At this time, the aluminum is buried in the through holes 21 and 22, and the lower electrode 16 is electrically connected to the power supply wiring 14 via the through hole 21.
Further, a silicon nitride film is formed thereon, and selectively etched into a pattern shape covering the lower electrode 16 to form a capacitor insulating film 17, and further, an aluminum film serving as an upper electrode is deposited thereon, and The upper electrode 18 is formed by patterning the aluminum film, and the capacitor 19 is formed. At this time, the upper electrode 18 is connected to the power supply wiring 14 through the through hole 22.

Then, the BPSG film 32 is wet-etched under conditions that increase the etching selectivity with respect to the silicon nitride film 24. Thus, the BPSG film 32 in the groove 31 is removed by etching. At this time, even under the lower electrode 16, the etchant penetrates into the groove 31 through both ends of the groove 31, so that the BPSG film 32 immediately below the lower electrode 16 is also etched away. As a result, as shown in FIG. 1, the air gap 23 including the concave groove 31 is formed immediately below the lower electrode 16. Thereafter, the uppermost passivation film 25 is deposited. At this time, the uppermost passivation film 25 is not deposited immediately below the lower electrode 16, and the air gap 23 is maintained.

Here, the plane shape of the air gap is
The present invention is not limited to the above-mentioned stripe shape.
1 with respect to the BPSG film 32 buried in
If the configuration allows the etchant to penetrate just below
For example, it may be formed in a lattice shape. Air gap 2
In order to increase the area of 3 as much as possible, the width of a plurality of locations along the length direction of the concave groove may be widened, and an air gap may be formed in the widened portion. The shape of the widened portion may be rectangular or circular. Further, if the air gap is arranged as directly as possible above the wiring, the air gap effect can be further enhanced.

In the above embodiment, in order to selectively remove the BPSG film 32 buried in the concave groove 31 from the passivation film 15 by etching, the silicon film is formed as a stopper film on the surface of the passivation film 15 and the concave groove 31. Although the nitride film 24 is formed, the stopper film 24 can be omitted if a material having a large etching selectivity with respect to the passivation film 15 is embedded in the concave groove 31. Note that the passivation film in the present invention is not necessarily limited to a film provided for sealing an element, and may be an insulating film for insulating upper and lower wirings or a conductive layer, which is called an interlayer insulating film. Needless to say, it includes.

[0018]

As described above, according to the present invention, it is possible to manufacture a semiconductor integrated circuit device having a structure in which a plurality of air gaps are arranged in a passivation film immediately below a lower electrode of a capacitor.
It is possible. Semiconductor integrated circuit device manufactured in this way.
Then, the passivation film just below the lower electrode is
Since the region where the air gap is formed is replaced with a cavity, the substantial area of passivation is reduced, and the dielectric constant of the entire passivation film is reduced. Therefore, the overall dielectric constant of the passivation film between the wiring connected to the semiconductor element and the lower electrode forming the capacitor formed thereon is reduced, and the parasitic capacitance between the lower electrode and the wiring is reduced. Can be reduced. On the other hand, since the lower electrode is supported by the passivation film in a region other than the air gap, a decrease in mechanical strength can be prevented, and a highly reliable semiconductor integrated circuit device can be configured.

[Brief description of the drawings]

FIG. 1 is a plan view of an embodiment of a semiconductor integrated circuit device according to the present invention, and a cross-sectional view taken along line AA thereof.

2A and 2B are a plan view and a cross-sectional view taken along the line BB of the method for manufacturing the semiconductor integrated circuit device in FIG.

3A and 3B are a plan view and a sectional view taken along the line BB of the method for manufacturing the semiconductor integrated circuit device in FIG.

4A and 4B are a plan view showing the method of manufacturing the semiconductor integrated circuit device of FIG.

FIG. 5 is a sectional view of a conventional semiconductor integrated circuit device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Semiconductor substrate 12 Interlayer insulating film 13 Signal wiring 14 Power supply wiring 15 Passivation film 16 Lower electrode 17 Capacitive insulating film 18 Upper electrode 19 Capacitor 21, 22 Through hole 23 Air gap 24 Silicon nitride film 25 Uppermost passivation film 31 Groove 32 BPSG film

Claims (2)

(57) [Claims] 1. A method according to claim 1, wherein a semiconductor element is formed on a semiconductor substrate.
A passivation film is formed, and the passivation
A lower electrode, a capacitor insulating film, and an upper electrode are sequentially laminated on the film.
Manufacturing method of a semiconductor integrated circuit device having a
There are, forming a passivation film on the semiconductor substrate, and forming the passivation film is selectively etched with a plurality of grooves at a predetermined interval in the predetermined region, the passivation film and the groove Forming a stopper insulating film on the surface of the substrate, burying a material having an etching selectivity with the stopper insulating film in the groove, a lower electrode on the surface of the passivation film and the buried material, A method for manufacturing a semiconductor integrated circuit device, comprising: a step of forming a capacitor by forming a capacitor insulating film and an upper electrode; and a step of selectively etching and removing a material buried in the concave groove. 2. On a semiconductor substrate on which a semiconductor element is formed.
A passivation film is formed, and the passivation
A lower electrode, a capacitor insulating film, and an upper electrode are sequentially laminated on the film.
Manufacturing method of a semiconductor integrated circuit device having a
There are, forming a passivation film on the semiconductor substrate, forming a plurality of grooves at a predetermined interval in the predetermined region by selectively etching the passivation film, the in said groove Embedding a material having an etching selectivity with the passivation film; forming a capacitor by forming a lower electrode, a capacitor insulating film, and an upper electrode on the surface of the passivation film and the buried material; Selectively removing the material buried in the groove by etching.