JP7294156B2 - Semiconductor device manufacturing method - Google Patents

Description

The present disclosure relates to a method of manufacturing a semiconductor device.

It is known that when a semiconductor device such as a MOSFET (Metal-Oxide-Semiconductor Field-Effect-Transistor) is used as a switching element, a pn diode structurally built into the MOSFET can be used as a freewheeling diode. For example, a method has been proposed in which an SBD (Shottky-Barrier-Diode) is incorporated in the device and used as a freewheeling diode (see, for example, Patent Document 1).

A method of manufacturing an SBD-embedded MOSFET has a step of removing an oxide film on a substrate in a region where a Schottky electrode is to be formed. However, the adhesion between the photoresist and its underlying NiSi may deteriorate due to variations in the manufacturing process. For this reason, when the oxide film is removed by wet etching, an etchant penetrates from the interface between the photoresist and NiSi and etches the gate oxide film, resulting in a short circuit between the gate and the source or deterioration of the gate oxide film characteristics. I had a problem. In order to avoid this problem, a method of removing the oxide film by dry etching has also been proposed.

WO2016/052261

However, when the oxide film is removed by dry etching, an etching damage layer is formed in the region of the drift layer forming the Schottky electrode. As a result, there is a problem that the leak current increases and the Schottky characteristic deteriorates.

The present disclosure has been made to solve the problems described above, and an object thereof is to obtain a method of manufacturing a semiconductor device capable of preventing characteristic deterioration.

A method of manufacturing a semiconductor device according to the present disclosure includes steps of forming a drift layer of a first conductivity type on an upper surface of a semiconductor substrate; forming a well region; forming a first conductivity type source region in the well region; forming a gate insulating film on the drift layer, the well region and the source region; forming a gate electrode on the gate insulating film so as to face the region 1, the well region and the source region; forming a protective film on the gate insulating film so as to face the second region; forming an interlayer insulating film on the gate insulating film, the gate electrode and the protective film; and leaving the interlayer insulating film formed on the gate electrode while leaving the protective film a step of removing by dry etching the interlayer insulating film formed above and the interlayer insulating film and the gate insulating film formed between the gate electrode and the protective film; forming a first ohmic electrode on the well region and the source region exposed by dry etching the gate insulating film; forming a second ohmic electrode on the lower surface of the semiconductor substrate; removing the protective film exposed by dry etching an interlayer insulating film and the gate insulating film under the protective film; and forming a Schottky electrode thereon.

In the present disclosure, since dry etching is performed while the second region is protected by the protective film, no etching damage layer is formed in the second region where the Schottky electrode is to be formed. Therefore, deterioration of characteristics can be prevented.

FIG. 4 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the first embodiment; FIG. 4 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the first embodiment; FIG. 4 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the first embodiment; FIG. 4 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the first embodiment; FIG. 4 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the first embodiment; FIG. 4 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the first embodiment; FIG. 4 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the first embodiment; FIG. 4 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the first embodiment; FIG. 4 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the first embodiment; FIG. 4 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the first embodiment; FIG. 4 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the first embodiment; FIG. 4 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the first embodiment; FIG. 4 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the first embodiment; FIG. 4 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the first embodiment; FIG. 10 is a cross-sectional view showing a method of manufacturing a semiconductor device according to Comparative Example 1; FIG. 11 is a cross-sectional view showing a method of manufacturing a semiconductor device according to Comparative Example 2; FIG. 11 is a cross-sectional view showing a method of manufacturing a semiconductor device according to Comparative Example 2; FIG. 11 is a cross-sectional view showing a method of manufacturing a semiconductor device according to a second embodiment;

A method of manufacturing a semiconductor device according to an embodiment will be described with reference to the drawings. The same reference numerals are given to the same or corresponding components, and repetition of description may be omitted.

Embodiment 1.
1 to 14 are cross-sectional views showing the method of manufacturing the semiconductor device according to the first embodiment. First, as shown in FIG. 1, an n-type drift layer 2 is epitaxially grown on the upper surface of a semiconductor substrate 1 by a chemical vapor deposition (CVD) method.

Next, a mask (not shown) having a plurality of openings is formed of photoresist or the like on the surface of the drift layer 2 . This mask is used to ion-implant Al, which is a p-type impurity, into the drift layer 2 . After that, the implantation mask is removed. Through this step, a well region 5 is formed between the first region 3 and the second region 4 of the drift layer 2, as shown in FIG. A plurality of mutually-spaced regions into which Al ions are implanted become p-type well regions 5 . The first region 3 and the second region 4 are surface layer regions of the drift layer 2 separated from each other and arranged between the plurality of well regions 5 .

Next, an implantation mask (not shown) having an opening above the well region 5 is formed using photoresist or the like. Using this mask, the well region 5 is ion-implanted with N, which is an n-type impurity. The N ion implantation depth is made shallower than the thickness of the well region 5 . Through this process, an n-type source region 6 is formed in the well region 5, as shown in FIG. Of the N-implanted regions, the n-type region becomes the n-type source region 6 .

Next, an implantation mask (not shown) having an opening above the well region 5 is formed using photoresist or the like. Using this mask, p-type impurity Al ions are implanted into the portion of the well region 5 on the side of the second region 4 . After that, the implantation mask is removed. Through this process, well contact regions 7 are formed as shown in FIG. The impurity concentration of well contact region 7 is higher than that of well region 5 . Thereby, good electrical contact between the ohmic electrode and the well contact region 7, which will be described later, can be obtained. Moreover, it is desirable to heat the semiconductor substrate 1 or the drift layer 2 to 150° C. or higher when ion-implanting the p-type impurity. Thereby, the resistance of the well contact region 7 can be reduced.

Next, annealing is performed at 1300 to 1900° C. for 30 seconds to 1 hour in an inert gas atmosphere such as argon gas using a heat treatment apparatus. This annealing electrically activates the implanted N and Al ions.

Next, as shown in FIG. 5, the surfaces of the drift layer 2, well region 5, source region 6, and well contact region 7 are thermally oxidized to form a gate insulating film 8 of silicon oxide thereon. .

Next, as shown in FIG. 6, a conductive polysilicon film is formed on the gate insulating film 8 by low pressure CVD and patterned. Through this step, the gate electrode 9 is formed on the gate insulating film 8 so as to face the first region 3 and the portions of the well region 5 and the source region 6 on the first region 3 side.

Next, a SiN film is formed on the gate insulating film 8 and the gate electrode 9 by plasma CVD and patterned. Through this step, a protective film 10 is formed on the gate insulating film 8 so as to face the second region 4, as shown in FIG. The protective film 10 is also formed over part of the well region 5 and the well contact region.

Next, an interlayer insulating film 11 is formed on the gate insulating film 8, the gate electrode 9 and the protective film 10 by low pressure CVD. Next, as shown in FIG. 8, while leaving the interlayer insulating film 11 formed on the gate electrode 9, the interlayer insulating film 11 formed on the protective film 10, the gate electrode 9 and the protective film 10 are separated. The interlayer insulating film 11 and the gate insulating film 8 formed between are removed by dry etching. As a result, a contact hole penetrating the interlayer insulating film 11 and the gate insulating film 8 to reach the well contact region 7 and the source region 6 is formed. A portion of the well contact region 7 and the source region 6 are exposed within the contact hole.

Next, as shown in FIG. 9, a metal film 12 mainly composed of Ni is formed by a sputtering method or the like. Then, heat treatment is performed at a temperature of 600 to 1100° C. to react the exposed silicon carbide layer of well region 5 and source region 6 with metal film 12 to form silicide. Thereby, a first ohmic electrode 13 is formed on the exposed well region 5 and source region 6 . Next, as shown in FIG. 10, the metal film 12 other than the silicide is removed by wet etching using sulfuric acid, nitric acid, hydrochloric acid, or a mixture of these and hydrogen peroxide.

Next, a metal film containing Ni as a main component is formed on the lower surface of the semiconductor substrate 1 and heat-treated. Through this process, a second ohmic electrode 14 is formed on the lower surface of the semiconductor substrate 1, as shown in FIG.

Next, as shown in FIG. 12, the protective film 10 exposed by dry etching the interlayer insulating film 11 is removed by wet etching with hot phosphoric acid or the like. Next, as shown in FIG. 13, the gate insulating film 8 under the protective film 10 is removed by wet etching using hydrofluoric acid or the like.

Next, as shown in FIG. 14, a Schottky electrode 15 is formed by sputtering or the like on the second region 4 exposed by removing the protective film 10 and the gate insulating film 8 . It is preferable to deposit a metal such as Ti, Mo or Ni as the Schottky electrode 15 . Next, a wiring metal such as Al is formed on the surface of the semiconductor substrate 1 by sputtering or vapor deposition, and processed into a predetermined shape by photolithography. Through this process, the source electrode 16 connected to the first ohmic electrode 13 and Schottky electrode 15, and the gate pad and gate wiring connected to the gate electrode 9 are formed. Furthermore, a drain electrode 17 that is a metal film is formed on the surface of the second ohmic electrode 14 . The semiconductor device according to the present embodiment is manufactured through the above steps.

Next, the effects of this embodiment will be described in comparison with Comparative Examples 1 and 2. FIG. 15A and 15B are cross-sectional views showing a method for manufacturing a semiconductor device according to Comparative Example 1. FIG. In Comparative Example 1, the oxide film on the second region 4 is removed by dry etching. However, the etching damage layer 18 is formed in the second region 4 where the Schottky electrode is to be formed, resulting in an increase in leak current and deterioration in Schottky characteristics. In contrast, in the present embodiment, since dry etching is performed while the second region 4 is protected by the protective film 10, the etching damage layer 18 is not formed in the second region 4 where the Schottky electrode is to be formed. . Therefore, deterioration of characteristics can be prevented.

The protective film 10 is preferably formed so as to cover not only the second region 4 but also part of the well region 5 and the well contact region 7 . As a result, even if the formation position of the protective film 10 is displaced due to process variations, the entire second region 4 through which the Schottky current flows is protected.

16 and 17 are cross-sectional views showing a method for manufacturing a semiconductor device according to Comparative Example 2. FIG. As shown in FIG. 16, an oxide film 19 is formed on the second region 4 forming the Schottky electrode. As shown in FIG. 17, oxide film 19 is removed by wet etching using photoresist 20 as a mask. However, the adhesion between the photoresist 20 and the first ohmic electrode 13 made of NiSi may deteriorate due to variations in the manufacturing process. The etchant penetrates from this interface and etches the gate oxide film 8, which causes a problem of a short circuit failure between the gate and the source or deterioration of the characteristics of the gate oxide film.

In contrast, in the present embodiment, the gate insulating film 8 and the interlayer insulating film 11 are oxide films, and the protective film 10 is SiN. The etching rate of SiN can be made sufficiently smaller than the etching rate of the oxide film. Therefore, when the protective film 10 is etched, the etching rate of the protective film 10 becomes smaller than the etching rates of the interlayer insulating film 11 and the gate insulating film 8 . Then, the protective film 10 is removed by wet etching using hot phosphoric acid. Since the oxide film, which is the material of the gate insulating film 8 and the interlayer insulating film 11, is not etched by hot phosphoric acid, it is possible to prevent the etchant from entering from the interface between them. Since the thickness of the gate insulating film 8 is as thin as 1/10 or less of the thickness of the interlayer insulating film 11, the wet etching time for the gate insulating film 8 is short. Therefore, penetration of the etchant during wet etching of the gate insulating film 8 does not pose a problem.

Embodiment 2.
18A and 18B are cross-sectional views showing the method for manufacturing the semiconductor device according to the second embodiment. In Embodiment 1, after forming gate electrode 9 as shown in FIG. 6, protective film 10 is formed as shown in FIG. On the other hand, in this embodiment, the protective film 10 is a polysilicon film, and the gate electrode 9 is also a polysilicon film. Then, by changing the mask pattern when forming the gate electrode 9, the gate electrode 9 and the protective film 10 are formed at the same time. As a result, the manufacturing man-hours can be reduced more than in the first embodiment. Also, the protective film 10 is removed by wet etching using tetramethylammonium hydroxide or the like. As a result, the etching rate of the polysilicon film can be made sufficiently smaller than the etching rate of the oxide film. Since the oxide film, which is the material of the gate insulating film 8 and the interlayer insulating film 11, is not etched by tetramethylammonium hydroxide, it is possible to prevent the etchant from entering from the interface between them. Other steps and effects are the same as those of the first embodiment.

Semiconductor substrate 1 is not limited to being made of silicon, and may be made of a wide bandgap semiconductor having a larger bandgap than silicon. Wide bandgap semiconductors are, for example, silicon carbide, gallium nitride-based materials, or diamond. A semiconductor device formed of such a wide bandgap semiconductor can be miniaturized because of its high withstand voltage and allowable current density. By using this miniaturized semiconductor device, a semiconductor module incorporating this semiconductor device can also be miniaturized and highly integrated. Moreover, since the heat resistance of the semiconductor device is high, the radiation fins of the heat sink can be made smaller, and the water-cooled portion can be air-cooled, so that the semiconductor module can be further made smaller. Moreover, since the power loss of the semiconductor device is low and the efficiency is high, the efficiency of the semiconductor module can be improved.

REFERENCE SIGNS LIST 1 semiconductor substrate 2 drift layer 3 first region 4 second region 5 well region 6 source region 8 gate insulating film 9 gate electrode 10 protective film 11 interlayer insulating film 13 first region ohmic electrode, 14 second ohmic electrode, 15 Schottky electrode

Claims (8)

forming a first conductivity type drift layer on the upper surface of a semiconductor substrate;
forming a well region of a second conductivity type between the first region and the second region of the drift layer;
forming a first conductivity type source region in the well region;
forming a gate insulating film on the drift layer, the well region and the source region;
forming a gate electrode on the gate insulating film so as to face the first region, the well region and the source region;
forming a protective film on the gate insulating film so as to face the second region;
forming an interlayer insulating film on the gate insulating film, the gate electrode and the protective film;
The interlayer insulating film formed on the protective film while leaving the interlayer insulating film formed on the gate electrode, and the interlayer insulating film formed between the gate electrode and the protective film. and a step of removing the gate insulating film by dry etching;
forming a first ohmic electrode on the well region and the source region exposed by dry etching the interlayer insulating film and the gate insulating film;
forming a second ohmic electrode on the lower surface of the semiconductor substrate;
a step of dry etching the interlayer insulating film to remove the exposed protective film and the gate insulating film under the protective film;
and forming a Schottky electrode on the second region exposed by removing the protective film and the gate insulating film. 2. The method of manufacturing a semiconductor device according to claim 1, wherein when etching said protective film, the etching rate of said protective film is lower than the etching rate of said interlayer insulating film and said gate insulating film. the gate insulating film and the interlayer insulating film are oxide films;
3. The method of manufacturing a semiconductor device according to claim 2, wherein said protective film is SiN. 4. The method of manufacturing a semiconductor device according to claim 3, wherein said protective film is removed by wet etching using hot phosphoric acid. 3. The method of manufacturing a semiconductor device according to claim 1, wherein said protective film is a polysilicon film. 6. The method of manufacturing a semiconductor device according to claim 5, wherein said protective film and said gate electrode are formed simultaneously. the gate insulating film and the interlayer insulating film are oxide films;
7. The method of manufacturing a semiconductor device according to claim 5, wherein said protective film is removed by wet etching using tetramethylammonium hydroxide. 8. The method of manufacturing a semiconductor device according to claim 1, wherein said semiconductor substrate is made of a wide bandgap semiconductor.

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