JP2020038944A - Semiconductor device and manufacturing method thereof, power conversion device, three-phase motor system, automobile, and railway vehicle - Google Patents

Abstract

To improve the performance of a semiconductor device.
A semiconductor device has a SiC power MISFET formation region MR and a SiC-SBD formation region DR. An n ⁻ -type epitaxial layer 12 is formed on an n-type semiconductor substrate 11. the n ^- -type epitaxial layer 12, p ⁺ -type body region 14 is formed, p ⁺ -type body region 14, n ⁺⁺ -type source region 19 and n ⁺ -type current spreading region 18 Are formed. through the n ⁺⁺ -type source region 19, the trench TR to reach the p ⁺ -type body region 14, a gate electrode 21 is formed. The source wiring electrode 2 is formed on the interlayer insulating film 22, and the source wiring electrode 2 is electrically connected to the n ⁺⁺ -type source region 19 in the SiC power MISFET formation region MR via the barrier metal film 23. And electrically connected to the n ⁻ -type epitaxial layer 12 in the SiC-SBD formation region DR.
[Selection diagram] FIG.

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, a power conversion device using the semiconductor device, a three-phase motor system, an automobile and a railway vehicle, and more particularly to a semiconductor device using silicon carbide.

  2. Description of the Related Art In a metal insulating film semiconductor field effect transistor (MISFET), which is one of power semiconductor devices, conventionally, a power MISFET using a silicon (Si) substrate (hereinafter referred to as a Si power MISFET) is used. It was mainstream.

  However, a power MISFET using a silicon carbide (SiC) substrate (hereinafter, referred to as a SiC power MISFET) can achieve higher breakdown voltage and lower loss than a Si power MISFET. For this reason, SiC power MISFETs have received particular attention in the field of low power or environmentally friendly inverter technology.

  When the SiC power MISFET has the same breakdown voltage as the Si power MISFET, the on-resistance can be reduced. Since SiC has about seven times the electric field strength against dielectric breakdown as compared with Si, the epitaxial layer serving as the drift layer can be made thinner in the SiC substrate.

  Patent Document 1 discloses a technique in which a SiC power MISFET is used in an inverter or the like. In the inverter, since a current can flow bidirectionally through the channel, a synchronous rectification operation without using an external SiC-SBD (Schottky Barrier Diode) is expected. When performing the synchronous rectification operation, when the SiC power MISFETs of each of the upper arm and the lower arm of the inverter are simultaneously turned on, the SiC power MISFET of each of the upper arm and the lower arm is prevented in order to prevent the current from being short-circuited. There is a dead time at which the gate signal is stopped at the time of switching. At this dead time, the return current flows through the body diode of the SiC power MISFET. However, when a forward current flows through the body diode of the SiC power MISFET, a forward deterioration phenomenon is known in which the hole current degrades the drift layer of the SiC and the on-resistance of the SiC power MISFET increases.

Patent Literature 2 discloses a method in which a SiC power MISFET and a SiC-SBD are mixedly mounted in the same chip as a method of realizing the synchronous rectification operation while suppressing the forward deterioration phenomenon as described above. . As a result, the forward voltage (V _f ) of the embedded SiC-SBD becomes lower than the V _f of the body diode which is a pn diode, so that the hole current flowing through the body diode is suppressed, and the forward degradation occurs. Can be suppressed.

  Patent Document 3 discloses a SiC power MISFET in which a trench is formed in a channel region and a gate electrode is embedded in the trench.

WO 2015/189929 Japanese Patent Application No. 2006-184627 International Publication No. WO 2016/129068

However, when the area of the mixed been SiC-SBD with SiC power MISFET is not sufficient, than V _f of the body diode is a pn diode, it is impossible to sufficiently lower the V _f of SiC-SBD. As a result, forward degradation occurs. Therefore, the forward degradation can be suppressed by increasing the area of the SiC-SBD per chip. However, if the area of the SiC-SBD per chip is large, the area of the SiC power MISFET per chip becomes relatively small. Become smaller. Then, there arises a problem that the channel resistance component per chip increases and the on-resistance increases. In particular, in a low-breakdown-voltage SiC power MISFET for automobiles and industries, the above problem is remarkable because an increase in on-resistance is caused by an increase in a channel resistance component.

  Therefore, in order to solve the above problem, by increasing the channel width of the SiC power MISFET independently of the area of the SiC power MISFET per chip, even if the area of the SiC-SBD per chip is increased, It is necessary to consider a structure that can suppress an increase in on-resistance. From such a study, it is desired to improve the performance of the semiconductor device in which the SiC power MISFET and the SiC-SBD are mixed.

  Other problems and novel features will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of a typical embodiment disclosed in the present application.

  A semiconductor device according to an embodiment is a semiconductor device having a first region in which a MISFET is formed and a second region in which a Schottky barrier diode is formed. The semiconductor device includes a first electrode formed on the back surface side of the substrate, and a first semiconductor layer of the first conductivity type formed on the semiconductor substrate. In the semiconductor device, a first impurity region of a second conductivity type formed in the first semiconductor layer in the first region, and a first semiconductor region formed in the first impurity region of the first region. A second impurity region of the first conductivity type having a higher impurity concentration than the layer and a third impurity region of the first conductivity type. Also, the semiconductor device is formed in the first region so as to penetrate the second impurity region and is located in the first impurity region, a bottom surface, a first side surface in contact with the second impurity region, and a third impurity region. A trench having a second side surface in contact with the region and facing the first side surface; and a gate electrode formed in the trench with a gate insulating film interposed therebetween. In addition, the semiconductor device has an interlayer insulating film formed on the gate electrode, and is formed on the interlayer insulating film, is electrically connected to the second impurity region in the first region, and is connected to the first semiconductor in the second region. A second electrode electrically connected to the layer.

  According to one embodiment disclosed in the present application, the performance of a semiconductor device can be improved.

FIG. 2 is a plan view of a semiconductor chip which is the semiconductor device of the first embodiment. FIG. 2 is a perspective view of a principal part of the semiconductor device of the first embodiment; FIG. 3 is a cross-sectional view of the semiconductor device according to the first embodiment; FIG. 3 is a cross-sectional view of the semiconductor device according to the first embodiment; 5 is a graph showing experimental results by the present inventors. 5 is a graph showing experimental results by the present inventors. FIG. 3 is a large process diagram schematically illustrating the manufacturing process of the semiconductor device of the first embodiment. FIG. 4 is a cross-sectional view showing a manufacturing step of the semiconductor device of the first embodiment. FIG. 9 is a cross-sectional view showing a manufacturing step following FIG. 8. FIG. 10 is a cross-sectional view showing a manufacturing step following FIG. 9. FIG. 11 is a cross-sectional view showing a manufacturing step following FIG. 10. FIG. 12 is a cross-sectional view showing a manufacturing step following FIG. 11. FIG. 13 is a cross-sectional view showing a manufacturing step following FIG. 12. FIG. 14 is a cross-sectional view showing a manufacturing step following FIG. 13. FIG. 15 is a cross-sectional view showing a manufacturing step following FIG. 14. FIG. 16 is a cross-sectional view showing a manufacturing step following FIG. 15. FIG. 17 is a cross-sectional view showing a manufacturing step following FIG. 16. FIG. 18 is a cross-sectional view showing a manufacturing step following FIG. 17; FIG. 19 is a cross-sectional view showing a manufacturing step following FIG. 18. FIG. 20 is a cross-sectional view showing a manufacturing step following FIG. 19. FIG. 15 is a perspective view of a principal part of the semiconductor device of the second embodiment. FIG. 14 is a sectional view of the semiconductor device of the second embodiment; FIG. 15 is a cross-sectional view showing a manufacturing step of the semiconductor device of the second embodiment. FIG. 24 is a cross-sectional view showing a manufacturing step following FIG. 23. FIG. 25 is a cross-sectional view showing a manufacturing step following FIG. 24. FIG. 17 is a perspective view of a principal part of the semiconductor device of the third embodiment. FIG. 14 is a cross-sectional view of the semiconductor device according to the third embodiment; FIG. 19 is a perspective view of a principal part of the semiconductor device of the fourth embodiment. FIG. 14 is a cross-sectional view of a semiconductor device according to a fourth embodiment. FIG. 14 is a circuit diagram illustrating a power conversion device according to a fifth embodiment. FIG. 15 is a schematic diagram illustrating a configuration of an electric vehicle that is a vehicle according to a sixth embodiment. FIG. 17 is a circuit diagram showing a boost converter according to a sixth embodiment. FIG. 15 is a schematic diagram illustrating a configuration of a railway vehicle according to a seventh embodiment.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and their repeated description will be omitted. In the following embodiments, description of the same or similar parts will not be repeated in principle, unless necessary.

(Embodiment 1)
<Structure of the semiconductor device of the present embodiment>
FIG. 1 is a plan view of a semiconductor chip 1 which is a semiconductor device of the present embodiment. Although FIG. 1 is a plan view, in order to make the drawing easy to see, an electrode 2 for source wiring, an electrode 3 for gate wiring, an n ⁺⁺ guard ring 4 and a p-type floating field limiting ring (FLR: (Floating Field Limiting Ring) 5 is hatched. FIG. 1 also shows an enlarged plan view of a part of an active region 6 where main semiconductor elements of the semiconductor chip 1 are formed.

  As shown in FIG. 1, a source wiring electrode 2 and a gate wiring electrode 3 are formed in the center of a semiconductor chip 1. Below the source wiring electrode 2 is an active region 6 in which main semiconductor elements such as an n-type SiC power MISFET and SiC-SBD are formed. In the active region 6, a plurality of trenches TR formed in a stripe shape in plan view are formed, and a SiC power MISFET is formed using these trenches TR. The structure of each of these semiconductor elements will be described later in detail.

  A region surrounded by a broken line in the source wiring electrode 2 is a source pad 2a, and a region surrounded by a broken line in the gate wiring electrode 3 is a gate pad 3a. Although not shown here, the semiconductor chip 1 is covered with a protective film, and the regions exposed from the openings formed in the protective film are the source pad 2a and the gate pad 3a. An external connection terminal such as wire bonding or a clip (copper plate) is connected to the upper surface of each of the source pad 2a and the gate pad 3a, thereby electrically connecting the semiconductor chip 1 to another chip or a wiring board. It is possible to do.

A triple p-type FLR 5 is formed on the outer periphery of the source wiring electrode 2 and the gate wiring electrode 3, and an n ⁺⁺ guard ring 4 is formed on the outer circumference of the p-type FLR 5. By forming a plurality of p-type FLRs 5 around the active region 6, the maximum electric field portion shifts to the p-type FLR 5 during the off operation of the SiC power MISFET, so that the breakdown occurs at the outermost p-type FLR 5. Therefore, the breakdown voltage of the SiC power MISFET can be increased. FIG. 1 shows three p-type FLR5, but the number of p-type FLR5 is not limited to three and may be more or less than three. The n ⁺⁺ guard ring 4 has a function of protecting the SiC power MISFET formed in the active region 6.

  Hereinafter, the structures of the SiC power MISFET and the SiC-SBD will be described with reference to FIGS.

FIG. 2 is a perspective view of a main part of the semiconductor device of the present embodiment, and shows a SiC power MISFET and a SiC-SBD which are semiconductor elements formed in the active region 6. In FIG. 2, since each impurity region formed near the surface of n ⁻ type epitaxial layer 12 is mainly shown, n type semiconductor substrate 11, gate electrode 21, source electrode 2 and the like are omitted. I have. FIG. 3 is a sectional view taken along the line AA shown in FIG. 2, and FIG. 4 is a sectional view taken along the line BB shown in FIG.

In the description of the present embodiment, “ ⁻ ”, “ ⁺ ”, and the like are added to the notation of “n-type”, but these are symbols indicating relative impurity concentrations. For example, in the case of n-type, the order of “n ⁻ ”, “n”, “n ⁺ ” and “n ⁺⁺ ” means that the impurity concentration of the n-type impurity is high. The notation of “p-type” is the same as that of “n-type”.

Semiconductor substrate (substrate) 11 used in the present embodiment is a compound semiconductor substrate containing carbon and silicon, and specifically, is an n ⁺ -type silicon carbide (SiC) substrate. The n-type semiconductor substrate 11 has a front surface and a back surface opposite to the front surface.

On the back side of the n-type semiconductor substrate 11, an n ⁺ -type drain region 13 is formed. A silicide layer 24 is formed below the n ⁺ type drain region 13, and a drain wiring electrode 25 is formed below the silicide layer 24. The silicide layer 24 is made of, for example, nickel silicide (NiSi). The drain wiring electrode 25 is, for example, a laminated film of a titanium (Ti) film, a nickel (Ni) film, and a gold (Au) film. The thickness of the drain wiring electrode 25 is, for example, 0.5 to 1.0 μm. It is. The drain wiring electrode 25 is not limited to these laminated films, and may be a single layer film composed of one of them, or may be a conductive film different from these.

  The drain wiring electrode 25 functions as a drain electrode of the SiC power MISFET in the SiC power MISFET formation region MR, and functions as a SiC-SBD cathode electrode in the SiC-SBD formation region DR. Although not shown, the drain wiring electrode 25 is electrically connected to a device outside the semiconductor chip 1 via a conductive film for external connection such as a solder ball or a bump electrode.

An n ⁻ -type epitaxial layer (semiconductor layer) 12 having a lower impurity concentration than that of the n-type semiconductor substrate 11 and made of silicon carbide (SiC) is formed on the n-type semiconductor substrate 11. The n ⁻ -type epitaxial layer 12 functions as a drift layer in the present embodiment.

A p ⁺ type body region (impurity region) 14 is formed in the n ⁻ type epitaxial layer 12. The p ⁺ type body region mainly functions as a channel region of the SiC power MISFET.

An n-type JFET region (impurity region) 16 having an impurity concentration higher than that of the n ⁻ -type epitaxial layer 12 is formed between the adjacent p ⁺ -type body regions 14 in the Y direction of FIG. I have.

In the p ⁺ -type body region 14, a p ⁺⁺ -type body potential fixed region (impurity region) 15 having a higher impurity concentration than the p ⁺ -type body region 14, and higher than the n-type JFET region 16. An n ⁺⁺ type source region (impurity region) 19 having an impurity concentration is formed. In the p ⁺ type body region 14, an n ⁺ type current diffusion region (impurity region) 18 having a higher impurity concentration than the n type JFET region 16 is formed. A part of the n ⁺ -type current diffusion region 18 extends to the n-type JFET region 16 adjacent to the p ⁺ -type body region 14. A p ⁺ -type electric field relaxation region (impurity region) 17 is formed on the n ⁺ -type current diffusion region 18 and the n-type JFET region 16.

The source wiring electrode 2 is electrically connected to the n ⁺⁺ -type source region 19 and the p ⁺⁺ -type body potential fixed region 15, and a source potential is applied when the SiC power MISFET operates. A drain wiring electrode 25 is electrically connected to the n ⁺ -type current diffusion region 18 via the n-type JFET region 16, the n ⁻ -type epitaxial layer 12, the n ⁺ -type drain region 13, and the silicide layer 24. Connected, and a drain potential is applied when the SiC power MISFET operates.

The n ⁻ -type epitaxial layer 12 opposite to the n ⁺⁺ -type source region 19 with the p ⁺⁺ -type body potential fixed region 15 as a boundary is a SiC-SBD formation region DR. In other words, the p ⁺⁺ type body potential fixed region 15 is located between the n ⁺⁺ type source region 19 of the SiC power MISFET formation region MR and the n ⁻ type epitaxial layer 12 of the SiC-SBD formation region DR. positioned. As described later, the source wiring electrode 2 is electrically connected to the n ⁻ -type epitaxial layer 12 in the SiC-SBD formation region DR.

N SiC power MISFET formation region MR ^- the type of epitaxial layer 12 through the n ⁺⁺ -type source region 19, so as to reach the p ⁺ -type body region 14, a plurality of trenches TR is formed . As shown in FIGS. 2 and 3, each of the plurality of trenches TR extends in the Y direction. Then, as shown in FIGS. 2 and 4, a plurality of trenches TR are formed adjacent to each other in the X direction.

  A gate electrode 21 is embedded in each of the plurality of trenches TR via a gate insulating film 20. The gate insulating film 20 is, for example, an insulating film such as a silicon oxide film, and the thickness of the gate insulating film 20 is, for example, 5 to 150 nm. The gate electrode 21 is a conductive film such as a polycrystalline silicon film, and the thickness of the gate electrode 21 is, for example, 0.01 to 4 μm.

Part of the gate electrode 21 is also formed outside the trench TR, and the gate electrodes 21 formed inside each of the plurality of trenches TR are integrated with each other. Note that, as shown in FIG. 3, the end of the gate electrode 21 formed outside the trench TR is located on the n ⁺⁺ -type source region 19.

  Although not shown, the gate electrode 3 is electrically connected to the gate wiring electrode 3 shown in FIG. 1, and a gate potential is applied when the SiC power MISFET operates.

As shown in FIG. 3, in the Y direction, the first side surface S1 of the trench TR is in contact with the n ⁺⁺ -type source region 19, and the second side surface S2 of the trench TR, which is the side surface facing the first side surface S1, , N ⁺ -type current diffusion regions 18. In addition, as shown in FIG. 4, the third side surface S3 of the trench TR and the fourth side surface S4 of the trench TR facing the third side surface S3 in the X direction are in the p ⁺ type body region. In contact. Further, the bottom surface of trench TR is in contact with the p ⁺ type body region.

Thus, n ⁺ -type path from current spreading region 18 to n ⁺⁺ -type source region 19 through the p ⁺ -type body region 14 becomes the current path of the SiC power MISFET. That is, the channel region of the SiC power MISFET is formed in the p ⁺ -type body region in contact with the third side surface S3, the fourth side surface S4, and the bottom surface of the trench TR, and in particular, the p region in contact with the third side surface S3 and the fourth side surface S4 ^{The +} type body region is the main part of the channel region.

The gate electrode 21 of the SiC power MISFET is covered with an interlayer insulating film 22. The interlayer insulating film 22 is an insulating film such as a silicon oxide film, for example. The interlayer insulating film 22 includes a part of the n ⁺⁺ source region 19, the p ⁺⁺ body potential fixed region 15, and the n ⁻ epitaxial layer 12 of the SiC-SBD formation region DR. An opening OP1 that opens is formed.

  A barrier metal film 23 is formed inside the opening OP1 and on the interlayer insulating film 22, and the source wiring electrode 2 is formed on the barrier metal film 23. The barrier metal film 23 is a conductive film such as a titanium (Ti) film, and the source wiring electrode 2 is a conductive film such as an aluminum (Al) film.

The source wiring electrode 2 buried in the opening OP1 is connected to the n ⁺⁺ -type source region 19, the p ⁺⁺ -type body potential fixing region 15, and the SiC-SBD formation region via the barrier metal film 23. It is connected to the DR n ⁻ -type epitaxial layer 12. A source potential is applied to these regions from the source wiring electrode 2. That is, in the SiC power MISFET formation region MR, the barrier metal film 23 and the source wiring electrode 2 function as a source electrode and constitute an ohmic contact portion. In the SiC-SBD formation region DR, the barrier metal film 23 functions as an anode electrode and forms a Schottky contact portion.

  The gate wiring electrode 3 shown in FIG. 1 is formed of the same conductive film as the source wiring electrode 2, and is connected to a part of the gate electrode 21 via the barrier metal film 23. That is, the barrier metal film 23 and the gate wiring electrode 3 connected to a part of the gate electrode 21 in the SiC power MISFET formation region MR constitute an ohmic contact portion.

  Although not shown, a protective film such as a silicon oxide film or a polyimide film is formed on the source wiring electrode 2 and the gate wiring electrode 3. The exposed regions are the source pad 2a and the gate pad 3a shown in FIG.

Hereinafter, parameters such as the depth and the impurity concentration of each component in the present embodiment will be described. Each of the depths (first to sixth depths) shown below is a depth from the surface of the n ⁻ -type epitaxial layer 12. In other words, these depths are the thickness of each impurity region.

The n-type semiconductor substrate 11 has, for example, an impurity concentration of 1 × 10 ¹⁸ to 1 × 10 ²¹ cm ⁻³ .

The n ⁻ -type epitaxial layer 12 has a thickness of, for example, 5 to 50 μm, and has an impurity concentration of, for example, 1 × 10 ¹⁴ to 1 × 10 ¹⁷ cm ⁻³ .

The n ⁺ type drain region 13 has an impurity concentration of, for example, 1 × 10 ¹⁹ to 1 × 10 ²¹ cm ⁻³ .

The p ⁺ type body region 14 has a depth (first depth) of, for example, 0.5 to 2.0 μm, and has an impurity concentration of, for example, 1 × 10 ¹⁶ to 1 × 10 ¹⁹ cm ⁻³ . The maximum impurity concentration of the p ⁺ -type body region 14 is, for example, in the range of 1 × 10 ¹⁷ to 1 × 10 ¹⁹ cm ⁻³ .

The p ⁺⁺ -type body potential fixing region 15 has a depth (second depth) of, for example, 0.1 to 1.0 μm, and has an impurity concentration of, for example, 1 × 10 ¹⁹ to 1 × 10 ²¹ cm ^−3. Have.

The n ⁺⁺ type source region 19 has a depth (third depth) of, for example, 0.1 to 1.0 μm, and has an impurity concentration of, for example, 1 × 10 ¹⁹ to 1 × 10 ²¹ cm ⁻³ .

The n ⁺ type current diffusion region 18 has a depth of, for example, 0.1 to 1.0 μm (fourth depth), and has an impurity concentration of, for example, 5 × 10 ^{17 to} 5 × 10 ¹⁸ cm ⁻³ .

The p ⁺ -type electric field relaxation region 17 has a depth of, for example, 0.01 to 0.5 μm (fifth depth), and has, for example, an impurity concentration of 1 × 10 ¹⁷ to 1 × 10 ¹⁹ cm ⁻³ .

The n-type JFET region 16 has, for example, a depth of 0.3 to 2.5 μm (sixth depth) and an impurity concentration of, for example, 1 × 10 ¹⁴ to 1 × 10 ¹⁷ cm ⁻³ .

Hereinafter, parameters regarding trench TR shown in FIGS. 3 and 4 will be described. The depth H of trench TR from the surface of n ⁻ -type epitaxial layer 12 is smaller than the depth (first depth) of p ⁺ -type body region 14 and is, for example, 0.1 to 1.5 μm. In the trench TR, the length L1 in the direction (Y direction) parallel to the channel length is, for example, 1.0 to 3.0 μm, and the length L2 in the direction (X direction) parallel to the channel width is, for example, 0. 0.1 to 2.0 μm. The length L3, which is the interval between the trenches TR in the direction (X direction) parallel to the channel width, is, for example, about 0.1 to 2.0 μm.

  Such a SiC power MISFET and a SiC-SBD are mixedly mounted on the semiconductor chip 1 which is the semiconductor device of the present embodiment.

<Main features of the semiconductor device of the present embodiment>
In the semiconductor device of the present embodiment, a plurality of trenches TR are formed in SiC power MISFET formation region MR, and a gate electrode 21 is buried in each trench TR via a gate insulating film 20. For this reason, the bottom surface of the trench TR and both side surfaces (the third side surface S3 and the fourth side surface S4) of the trench TR along the Y direction constitute a channel region of the SiC power MISFET. Therefore, the SiC power MISFET using the trench gate according to the present embodiment can expect higher channel mobility than the planar MISFET in which the trench TR is not formed in the n ⁻ type epitaxial layer 12.

  Further, in the X direction, the sum (L2 + L3) of the length L2, which is the width of the trench TR, and the length L3, which is the interval between the trenches TR, is reduced, and the depth H of the trench TR is further increased. Thus, the channel width in the semiconductor chip 1 can be increased, and the channel resistance can be reduced.

  Further, the structure shown in FIG. 2 shows an active region 6 which is a part of the semiconductor device of the present embodiment, and the active region 6 is repeatedly arranged in the semiconductor device of the present embodiment. Thus, it has a plurality of SiC power MISFET formation regions MR and a plurality of SiC-SBD formation regions DR.

  In the following description, the size of one active region 6 (one SiC power MISFET formation region MR and one SiC-SBD formation region DR) in the Y direction is referred to as an element size. In the X direction, the sum (L2 + L3) of the length L2 that is the width of the trench TR and the length L3 that is the interval between the trenches TR is referred to as a trench dimension. Further, in this embodiment, two SiC power MISFETs are formed in the SiC power MISFET formation region MR, and these two SiC power MISFETs are connected in parallel. The SiC power MISFET is treated as substantially one SiC power MISFET group.

In this element dimensions, by increasing the proportion of SiC-SBD formation region DR, since than V _f of the body diode is a pn diode in SiC power MISFET, a V _f of SiC-SBD can be sufficiently reduced, Forward degradation can be suppressed.

  Here, when the ratio of the SiC power MISFET formation region MR to the device dimensions decreases, the channel width decreases, and the channel resistance increases. That is, as the ratio of the SiC-SBD formation region DR is increased, the device dimensions are increased, and the channel resistance is increased. However, in this embodiment, an increase in the ratio of the depth H of the trench TR to the trench dimension (L2 + L3) can suppress an increase in channel resistance.

  Therefore, when the semiconductor chip 1 of the present embodiment is used, even if the synchronous rectification operation is performed without attaching the external SiC-SBD, the deterioration in the forward direction does not occur and the problem that the conduction loss increases is suppressed. can do.

  FIGS. 5 and 6 are graphs showing experimental results by the present inventors, and show the relationship between the ratio of the depth H of the trench TR to the trench dimension (L2 + L3) and the channel resistance in the present embodiment. . Note that the practical range described in FIGS. 5 and 6 is an area determined by the present inventors to be applicable to an actual product.

  FIG. 5 shows a case where the size of the SiC power MISFET formation region MR in the Y direction is 7 μm, the size of the SiC-SBD formation region DR in the Y direction is 3 μm, and the element size is 10 μm. As can be seen from the graph, the channel resistance decreases as the value of H / (L2 + L3) increases.

For example, when the value of H / (L2 + L3) is 0.25, the channel resistance is about 4 mΩ · cm ² . On the other hand, if the depth H of the trench TR is increased or the trench dimension (L2 + L3) is reduced, the value of H / (L2 + L3) becomes 5.00, and the channel resistance at this time is 0.2 mΩ · cm. ^{About 2} and small enough to be ignored.

  FIG. 6 shows a case where the size of the SiC-SBD formation region DR is further increased from the state of FIG. 5 in order to suppress the forward degradation. That is, FIG. 6 shows a case where the size of the SiC power MISFET formation region MR in the Y direction is 7 μm, the size of the SiC-SBD formation region DR in the Y direction is 13 μm, and the element size is 20 μm.

For example, when the value of H / (L2 + L3) is 0.25, the channel resistance is about 8 mΩ · cm ^2, which is higher than that in FIG. On the other hand, if the depth H of the trench TR is increased or the trench dimension (L2 + L3) is reduced, the value of H / (L2 + L3) becomes 0.50, and the channel resistance at this time is about 4 mΩ · cm ² . is there. When the value of H / (L2 + L3) is 5.00, the channel resistance is about 0.4 mΩ · cm ^2, which is negligibly small.

  From the results of FIGS. 5 and 6, the ratio of the depth H of the trench TR to the trench dimension (L2 + L3), that is, the value of H / (L2 + L3) is preferably 0.25 or more and 5.00 or less, It is more preferable that the value of H / (L2 + L3) is 0.50 or more and 5.00 or less. For further miniaturization of the semiconductor device, it is more preferable that the depth H of the trench TR is larger than the trench dimension (L2 + L3). That is, it is more preferable that the value of H / (L2 + L3) is larger than 1.00.

  As described above, in the present embodiment, the trench TR with respect to the trench size (L2 + L3) does not depend on the element size (the total size of the size of the SiC power MISFET formation region MR and the size of the SiC-SBD formation region DR). By adjusting the ratio of the depth H, that is, the value of H / (L2 + L3), the channel resistance can be changed, and the increase in the channel resistance can be suppressed.

As described above, in the present embodiment, the SiC power MISFET and the SiC-SBD are mixedly mounted in the same semiconductor chip 1, so that the _{Vf of} the SiC-SBD is higher than the _Vf of the body diode which is a pn diode. _f can be sufficiently reduced, and the increase in channel resistance can be suppressed. As a result, an increase in on-resistance can be suppressed, and the performance of the semiconductor device can be improved.

<Method of Manufacturing Semiconductor Device of Present Embodiment>
Hereinafter, a method for manufacturing the semiconductor device of the present embodiment will be described with reference to FIGS. FIG. 7 is a large process diagram schematically illustrating a method for manufacturing a semiconductor device. 8 to 20 are cross-sectional views showing a method for manufacturing a semiconductor device, and show AA cross sections as in FIG.

  Note that parameters such as the depth and the impurity concentration of each component in the present embodiment are the same as those described above, and thus description thereof will be omitted in the following description.

<Large process P1>
The large process P1 in FIG. 7 will be described. The large process P1 is mainly a process of forming the n ⁻ -type epitaxial layer 12.

  First, as shown in FIG. 8, an n-type semiconductor substrate 11 is prepared. The semiconductor substrate 11 is a 4H-SiC substrate into which an n-type impurity such as nitrogen (N) has been introduced. The n-type semiconductor substrate 11 has both a Si surface and a C surface, but the surface of the n-type semiconductor substrate 11 may be either a Si surface or a C surface.

Next, an n ⁻ -type epitaxial layer 12 made of silicon carbide (SiC) is formed on the surface of the n-type semiconductor substrate 11 by an epitaxial growth method. The impurity concentration of the n ⁻ -type epitaxial layer 12 depends on the device rating of the SiC semiconductor device, but is, for example, in the range of 1 × 10 ¹⁴ to 1 × 10 ¹⁷ cm ⁻³ .

As described above, first, the n-type semiconductor substrate 11 is prepared, and then the n ⁻ -type epitaxial layer 12 may be formed on the n-type semiconductor substrate 11. An SiC epitaxial substrate having the n ⁻ -type epitaxial layer 12 formed on the substrate 11 may be purchased. That is, in the present embodiment, the n-type semiconductor substrate 11 on which the n ⁻ -type epitaxial layer 12 is formed may be prepared by any means.

<Large process P2>
The large process P2 in FIG. 7 will be described. The large process P2 is a process of forming each impurity region mainly by ion implantation.

First, as shown in FIG. 8, an n ⁺ -type drain region 13 is formed on the back surface of the n-type semiconductor substrate 11 by, for example, introducing nitrogen by ion implantation.

Next, as shown in FIG. 9, a mask pattern MP1 that selectively covers the surface of the n ⁻ -type epitaxial layer 12 is formed. As a material constituting the mask pattern MP1, an inorganic material such as a SiO ₂ film, a Si film or a SiN film, or an organic material such as a resist film or a polyimide film can be used. The thickness of the mask pattern MP1 is, for example, 1.0 to 3.0 μm. In a later step, the width of the mask pattern MP1 covering the portion to be the n-type JFET region 16 is about 1.0 to 5.0 μm, and the width of the mask pattern MP1 covering the portion to be the SBD region is 1 It is about 0.0 to 10 μm.

Next, using the mask pattern MP1 as a mask, for example, aluminum is ion-implanted to form a p ⁺ -type body region 14 in the n ⁻ -type epitaxial layer 12. After that, the mask pattern MP1 is removed.

Although not shown, a pattern for opening the p ⁺ -type FLR 5 shown in FIG. 1 is also formed in the mask pattern MP1. Therefore, the same steps as the formation of the p ⁺ -type body region 14, p ⁺ -type FLR5 also formed. Further, the structure of the terminal portion is not limited to the p ⁺ -type FLR5, and may be, for example, a junction termination extension (JTE) structure.

Next, as shown in FIG. 10, a mask pattern MP2 that selectively covers the surface of the n ⁻ -type epitaxial layer 12 is formed. The material of the mask pattern MP2 is the same as the material of the mask pattern MP1, and the thickness of the mask pattern MP2 is, for example, 0.5 to 3.0 μm.

Next, using the mask pattern MP2 as a mask, for example, aluminum is ion-implanted to form a p ⁺⁺ -type body potential fixing region 15 in the p ⁺ -type body region 14. After that, the mask pattern MP2 is removed.

Next, as shown in FIG. 11, a mask pattern MP3 that selectively covers the surface of the n ⁻ -type epitaxial layer 12 is formed. The material of the mask pattern MP3 is the same as the material of the mask pattern MP1, and the thickness of the mask pattern MP3 is, for example, 1.0 to 5.0 μm.

Next, using the mask pattern MP3 as a mask, for example, nitrogen is ion-implanted to form an n-type JFET region 16 in the n ⁻ -type epitaxial layer 12. Next, using the mask pattern MP3 as a mask, for example, aluminum is ion-implanted to form ap ⁺ -type electric field relaxation region 17 on the surface of the n-type JFET region 16. After that, the mask pattern MP3 is removed.

Next, as shown in FIG. 12, a mask pattern MP4 that selectively covers the surface of the n ⁻ -type epitaxial layer 12 is formed. The material of the mask pattern MP4 is the same as that of the mask pattern MP1, and the thickness of the mask pattern MP4 is, for example, 0.5 to 3.0 μm.

Next, using the mask pattern MP4 as a mask, nitrogen is ion-implanted, for example, so that the n ⁺ -type current diffusion region 18 is located at a position extending between the p ⁺ -type body region 14 and the n-type JFET region 16. To form Next, using the mask pattern MP4 as a mask, for example, aluminum is ion-implanted so that the n ⁺ -type current is connected to the p ⁺ -type electric field relaxation region 17 formed on the surface of the n-type JFET region 16. A p ⁺ -type electric field relaxation region 17 is formed on the surface of the diffusion region 18. As a result, the p ⁺ -type electric field relaxation region 17 is formed so as to extend over the n ⁺ -type current diffusion region 18 and the n-type JFET region 16. After that, the mask pattern MP4 is removed.

Next, as shown in FIG. 13, a mask pattern MP5 that selectively covers the surface of the n ⁻ -type epitaxial layer 12 is formed. The material of the mask pattern MP5 is the same as the material of the mask pattern MP1, and the thickness of the mask pattern MP5 is, for example, 1.0 to 4.0 μm.

Next, using the mask pattern MP5 as a mask, for example, nitrogen is ion-implanted to form an n ⁺⁺ -type source region 19 in the p ⁺ -type body region 14. Although not shown, a pattern for opening the n ⁺⁺ type guard ring 4 shown in FIG. 1 is also formed in the mask pattern MP5. Therefore, the same steps as forming the n ⁺⁺ -type source region 19, n ⁺⁺ type guard ring 4 is also formed. After that, the mask pattern MP5 is removed.

<Large process P3>
The large process P3 in FIG. 7 will be described. The major step P3 is mainly an annealing (heat treatment) step for activating impurities contained in each impurity region.

As shown in FIG. 14, a carbon (C) film CF is deposited on the surface of the n ⁻ -type epitaxial layer 12 and on the back surface of the semiconductor substrate 11 by, for example, a plasma CVD (Chemical Vapor Deposition) method. The thickness of the carbon film CF is, for example, 0.03 μm. The annealing step is performed in a state where the surface of the n ⁻ -type epitaxial layer 12 and the back surface of the semiconductor substrate 11 are covered with the carbon film CF. This annealing step is performed at a temperature of 1500 ° C. or higher for about 2 to 3 minutes. By this annealing step, the impurities contained in each impurity region are activated. Thereafter, the carbon film CF is removed by, for example, oxygen plasma processing.

<Large process P4>
The large process P4 in FIG. 7 will be described. The large process P4 is mainly a process of forming the trench TR and the gate electrode 21.

First, as shown in FIG. 15, a mask pattern MP6 that selectively covers the surface of the n ⁻ -type epitaxial layer 12 is formed. The material of the mask pattern MP6 is the same as that of the mask pattern MP1, and the thickness of the mask pattern MP6 is, for example, 0.5 to 2.0 μm.

Next, by performing dry etching using the mask pattern MP6 as a mask, a trench TR that penetrates the n ⁺⁺ -type source region 19 and reaches the p ⁺ -type body region 14 is formed. Further, trench TR is formed so as to penetrate p ⁺ -type electric field relaxation region 17 and n ⁺ -type current diffusion region 18. The bottom surface of trench TR is located in p ⁺ -type body region 14. After that, the mask pattern MP6 is removed.

Next, as shown in FIG. 16, an insulating film such as a silicon oxide film is formed on each side surface and bottom surface of the trench TR and on the surface of the n ⁻ -type epitaxial layer 12 by, for example, the CVD method. A certain gate insulating film 20 is formed.

  Next, a conductive film 21a such as a polycrystalline silicon film into which an n-type or p-type impurity is introduced is formed on the gate insulating film 20 by, for example, a CVD method.

  Next, as shown in FIG. 17, a mask pattern MP7 that selectively covers the surface of the conductive film 21a is formed. The material of the mask pattern MP7 is the same as that of the mask pattern MP1, and the thickness of the mask pattern MP7 is, for example, 0.5 to 2.0 μm.

  Next, by performing dry etching using the mask pattern MP7 as a mask, the conductive film 21a exposed from the mask pattern MP7 is removed, and the gate electrode 21 on which the conductive film 21a is processed is formed. After that, the mask pattern MP7 is removed.

<Large process P5>
The large process P5 in FIG. 7 will be described. The large process P5 is a process for forming the source wiring electrode (SBD electrode) 2 mainly.

First, as shown in FIG. 18, an interlayer insulating film 22 made of, for example, a silicon oxide film is formed on the n ⁻ -type epitaxial layer 12 by, for example, a CVD method so as to cover the gate electrode 21. Thereafter, if necessary, the interlayer insulating film 22 may be polished by using a CMP (Chemical Mechanical Polishing) method or the like, and the surface of the interlayer insulating film 22 may be planarized.

Next, as shown in FIG. 19, a mask pattern MP8 that covers the gate electrode 21 and selectively covers a part of the n ⁻ -type epitaxial layer 12 is formed. The material of the mask pattern MP8 is the same as that of the mask pattern MP1, and the thickness of the mask pattern MP8 is, for example, 1.0 to 3.0 μm.

Next, by performing a dry etching process or a wet etching process using the mask pattern MP8 as a mask, the interlayer insulating film 22 and the gate insulating film 20 exposed from the mask pattern MP8 are removed, and an opening is formed in the interlayer insulating film 22. OP1 is formed. Here, the gate electrode 21 is covered with the interlayer insulating film 22, and at the bottom of the opening OP1, a part of the n ⁺⁺ -type source region 19, the p ⁺⁺ -type body potential fixing region 15, and the SiC -The n ⁻ -type epitaxial layer 12 in the SBD formation region DR is exposed. Although not shown, an opening pattern for embedding the gate wiring electrode 3 shown in FIG. 1 is also formed in the mask pattern MP8 formed on a part of the gate electrode 21. Therefore, an opening that opens a part of the gate electrode 21 is also formed in the interlayer insulating film 22 by the same process as the formation process of the opening OP1. After that, the mask pattern MP8 is removed.

  Next, as shown in FIG. 20, a barrier metal film 23 made of a conductive film such as a titanium film is formed by sputtering, for example, inside the opening OP1 and on the interlayer insulating film 22. Next, the source wiring electrode 2 made of a conductive film such as an aluminum film is formed on the barrier metal film 23 by, for example, a sputtering method.

The source wiring electrode 2 buried in the opening OP1 is part of the n ⁺⁺ -type source region 19, the p ⁺⁺ -type body potential fixing region 15, and the SiC- It is connected to the n ⁻ type epitaxial layer 12 in the SBD formation region DR. The barrier metal film 23 connected to the n ⁻ -type epitaxial layer 12 in the SiC-SBD formation region DR forms a Schottky contact portion.

  Although not shown, an opening for partially opening the gate electrode 21 is also formed in the interlayer insulating film 22 as described above. The gate wiring electrode 3 shown in FIG. 1 is formed in the same step as the source wiring electrode 2, and is formed in this opening. The barrier metal film 23 and the gate wiring electrode 3 connected to a part of the gate electrode 21 in the SiC power MISFET formation region MR constitute an ohmic contact portion.

  Thereafter, although not shown, a protective film such as a silicon oxide film or a polyimide film is formed on the source wiring electrode 2 and the gate wiring electrode 3, and a part of the source wiring electrode 2 is formed on the protective film. In addition, an opening for opening a part of the gate wiring electrode 3 is formed. The regions exposed from this opening become the source pad 2a and the gate pad 3a.

  After the above steps, the silicide layer 24 and the drain wiring electrode 25 are formed on the back surface of the semiconductor substrate 11 to obtain the structure shown in FIG.

First, a metal film such as a nickel (Ni) film is formed in the n ⁺ -type drain region 13 by, for example, a sputtering method. The thickness of this metal film is, for example, 0.1 μm. Next, the metal film is subjected to a heat treatment using a laser. By this heat treatment, the metal film and the n ⁺ -type drain region 13 react with each other, and the material included in the metal film and the material included in the n ⁺ -type drain region 13 are formed on the entire lower surface of the n ⁺ -type drain region 13. Is formed. The silicide layer 24 is made of, for example, nickel silicide (NiSi). Thereafter, the unreacted metal film that has not been silicided is removed by, for example, wet etching.

  Next, the drain wiring electrode 25 is formed on the lower surface of the silicide layer 24. The drain wiring electrode 25 is obtained by sequentially stacking a titanium film, a nickel film, and a gold film by, for example, a sputtering method. The drain wiring electrode 25 is not limited to these laminated films, and may be a single layer film composed of one of them, or may be a conductive film different from these.

  As described above, the semiconductor device of the present embodiment is manufactured.

(Embodiment 2)
Hereinafter, the semiconductor device of the second embodiment will be described with reference to FIGS. In the following description, differences from the first embodiment will be mainly described.

  FIG. 21 is a perspective view of a main part of the semiconductor device of the second embodiment, and shows a SiC power MISFET and a SiC-SBD which are semiconductor elements formed in the active region 6 as in the first embodiment. . FIG. 22 is a sectional view taken along line AA shown in FIG. The cross-sectional view along the line BB is the same as FIG. 4 of the first embodiment.

  As shown in FIG. 22, the difference between the second embodiment and the first embodiment is that an opening OP2 is formed in the interlayer insulating film 22 in the SiC power MISFET formation region MR and the SiC-SBD formation region DR An opening OP3 is formed in the interlayer insulating film 22. Then, at the bottom of the opening OP2 in the SiC power MISFET formation region MR, a silicide layer 26 is formed in order to realize more reliable ohmic contact.

In the SiC-SBD formation region DR, an opening OP3 that opens a part of the n ⁻ -type epitaxial layer 12 and the p ⁺⁺ -type body potential fixing region 15 is formed in the interlayer insulating film 22. A barrier metal film 23 and a source wiring electrode 2 are formed in the opening OP3. The barrier metal film 23 is directly connected to the n ⁻ -type epitaxial layer 12 to form a Schottky contact portion.

In the SiC power MISFET formation region MR, an opening OP2 that opens a part of the n ⁺⁺ source region 19 and a part of the p ⁺⁺ body potential fixing region 15 is formed in the interlayer insulating film 22. I have. A silicide layer 26 is formed in the opening OP2, and a barrier metal film 23 and a source wiring electrode 2 are formed on the silicide layer 26. The silicide layer 26 has a lower resistance than the material forming the barrier metal film 23, and is made of a material different from that of the barrier metal film 23, for example, nickel silicide (NiSi). The source wiring electrode 2 is connected to a part of the n ⁺⁺ -type source region 19 and a part of the p ⁺⁺ -type body potential fixing region 15 via the silicide layer 26 and the barrier metal film 23, and forms an ohmic contact. Unit.

That is, in the second embodiment, in the SiC power MISFET formation region MR, the silicide layer 26 is in direct contact with a part of the n ⁺⁺ -type source region 19 and the p ⁺⁺ -type body potential fixing region 15, thereby increasing the Realized reliable ohmic contact. Therefore, the performance of the semiconductor device can be further improved.

In the SiC power MISFET formation region MR, the material constituting the silicide layer 26 is not limited to nickel silicide, and may be made of another material such as cobalt silicide (CoSi ₂ ) in order to make the ohmic contact portion more appropriate. It may be a material.

In order to prevent the formation position of the opening OP2 from being too close to the formation position of the opening OP3, as shown in FIG. 22, the boundary between the SiC power MISFET formation region MR and the SiC-SBD formation region DR. The width in the Y direction of the p ⁺⁺ -type body potential fixing region 15 located in the region may be wider than in the first embodiment.

<Method of Manufacturing Semiconductor Device of Second Embodiment>
Hereinafter, a method for manufacturing the semiconductor device of the second embodiment will be described with reference to FIGS. The manufacturing method of the second embodiment is the same as that of the first embodiment up to FIG. 18, and FIG. 23 shows a manufacturing process following FIG.

First, as shown in FIG. 23, the gate electrode 21 and the n ⁻ -type epitaxial layer 12 of the SiC-SBD formation region DR are covered, and a part of the n ⁺ -type source region 19 and the p ⁺ -type A mask pattern MP9 that opens a part of the body potential fixing region 15 is formed. The material of the mask pattern MP9 is the same as the material of the mask pattern MP1, and the thickness of the mask pattern MP9 is, for example, 1.0 to 3.0 μm.

Next, by performing dry etching using the mask pattern MP9 as a mask, the interlayer insulating film 22 and the gate insulating film 20 exposed from the mask pattern MP9 are removed, and an opening OP2 is formed in the interlayer insulating film 22. . Here, the gate electrode 21 and the n ⁻ -type epitaxial layer 12 in the SiC-SBD formation region DR are covered with the interlayer insulating film 22, and a part of the n ⁺⁺ -type source region 19 is formed on the bottom surface of the opening OP 2. And a part of the p ⁺⁺ -type body potential fixing region 15 is exposed. Although not shown, an opening for partially opening the gate electrode 21 is also formed in the interlayer insulating film 22 during the step of forming the opening OP2. After that, the mask pattern MP9 is removed.

Next, as shown in FIG. 24, in the opening OP2, silicide is formed on the surface of each of a part of the n ⁺⁺ source region 19 and a part of the p ⁺⁺ body potential fixing region 15. A layer 26 is formed. To form the silicide layer 26, first, a metal film such as a nickel (Ni) film is deposited on the interlayer insulating film 22 including the inside of the opening OP2 by, for example, a sputtering method. The thickness of this metal film is, for example, about 0.05 μm.

Next, the metal film is subjected to a heat treatment at 600 to 1000 ° C. so that the material included in the metal film and the n ⁺⁺ source region 19 and the p ⁺⁺ body potential fixed region 15 are included. The material reacts to form a silicide layer 26 made of nickel silicide (NiSi) as these compounds. Although not shown, the silicide layer 26 is also formed on the bottom of the opening formed on a part of the gate electrode 21. Thereafter, the unreacted metal film is removed by, for example, wet etching using a solution containing sulfuric acid and aqueous hydrogen peroxide.

Next, as shown in FIG. 25, a mask pattern MP10 that opens the n ⁻ -type epitaxial layer 12 in the SiC-SBD formation region DR is formed. The material of the mask pattern MP10 is the same as the material of the mask pattern MP1, and the thickness of the mask pattern MP10 is, for example, 1.0 to 3.0 μm.

Next, by performing wet etching using the mask pattern MP10 as a mask, the interlayer insulating film 22 and the gate insulating film 20 exposed from the mask pattern MP10 are removed, and an opening OP3 is formed in the interlayer insulating film 22. . Thus, the n ⁻ -type epitaxial layer 12 in the SiC-SBD formation region DR is exposed at the bottom of the opening OP3. After that, the mask pattern MP10 is removed.

  Thereafter, the step of FIG. 20 of the first embodiment is performed, and the barrier metal film 23 and the source wiring electrode 2 are buried in the openings OP2 and OP3. Subsequent steps are the same as in the first embodiment.

In the second embodiment, dry etching is performed in the step of forming the opening OP2, and wet etching is performed in the step of forming the opening OP3. Since a Schottky contact is formed on the bottom surface of the opening OP3 in the SiC-SBD formation region DR, if the surface of the n ⁻ -type epitaxial layer 12 is damaged by etching, the Schottky characteristics may be degraded. Therefore, in the step of forming the opening OP3, it is preferable to apply a wet etching process with little etching damage.

Since the ohmic contact is formed on the bottom surface of the opening OP2 in the SiC power MISFET formation region MR, it is less necessary to consider etching damage than the Schottky contact. Further, a silicide layer 26 is formed on the bottom surface of the opening OP3. Therefore, even if etching damage remains on the surface of the n ⁺⁺ -type source region 19 and the surface of the p ⁺⁺ -type body potential fixing region 15, these surfaces react with the metal film for the silicide layer 26. And silicidation. Therefore, the bottom surface of the opening OP2 is less affected by the etching damage. The diameter of the opening OP2 is smaller than the diameter of the opening OP3. The dry etching is an anisotropic etching, and therefore is more suitable for forming a finer pattern than the wet etching which is an isotropic etching. For the above reasons, it is preferable to apply a dry etching process to the step of forming the opening OP2.

(Embodiment 3)
The semiconductor device according to the third embodiment will be described below with reference to FIGS. In the following description, differences from the first embodiment will be mainly described.

  FIG. 26 is a perspective view of a principal part of the semiconductor device of the third embodiment, and shows a SiC power MISFET and a SiC-SBD which are semiconductor elements formed in the active region 6, as in the first embodiment. . FIG. 27 is a sectional view taken along the line AA shown in FIG. The cross-sectional view along the line BB is the same as FIG. 4 of the first embodiment.

  As shown in FIGS. 26 and 27, the difference between the third embodiment and the first embodiment is that the SiC-SBD formation region DR includes a junction barrier Schottky diode, which is a kind of a Schottky barrier diode. A diode (JBS: Junction Barrier Schottky) is formed.

In the third embodiment, a plurality of p ⁺⁺ -type confined regions (impurity regions) 27 are formed in the n ⁻ -type epitaxial layer 12 in the SiC-SBD formation region DR. Similarly to the n ⁻ type epitaxial layer 12, these p ⁺⁺ type constricted regions 27 are exposed from the opening OP 1, and are electrically connected to the source wiring electrode 2 via the barrier metal film 23. ing.

Although the _Vf of the JBS is higher than the _Vf of the Schottky barrier diode (SiC-SBD) of the first embodiment, the JBS can suppress the leakage current at the time of blocking. That is, when the operation of the JBS, a depletion layer spreads from each p ⁺⁺ type confinement region 27, it is possible to narrow the current path between the p ⁺⁺ type confinement region 27 adjacent to each other, suppress the leakage current can do.

Further, the p ⁺⁺ -type constricted region 27 is formed in the same process as the p ⁺⁺ -type body potential fixed region 15 by changing the opening pattern of the mask pattern MP2 described in FIG. 10 of the first embodiment. be able to. Therefore, it is not necessary to newly add a manufacturing process, and an increase in manufacturing cost can be suppressed. Parameters such as the depth (thickness) and impurity concentration of the p ⁺⁺ -type constricted region 27 are the same as those of the p ⁺⁺ -type body potential fixed region 15.

The technology disclosed in the third embodiment may be applied to the semiconductor device in the second embodiment. In this case, the p ⁺⁺ -type constricted region 27 is located in the opening OP3 of the second embodiment.

(Embodiment 4)
Hereinafter, the semiconductor device of the fourth embodiment will be described with reference to FIGS. In the following description, differences from the first embodiment will be mainly described.

  FIG. 28 is a perspective view of a main part of the semiconductor device of the fourth embodiment, and shows a SiC power MISFET and a SiC-SBD which are semiconductor elements formed in the active region 6, as in the first embodiment. . FIG. 29 is a sectional view taken along the line AA shown in FIG. The cross-sectional view along the line BB is the same as FIG. 4 of the first embodiment.

  As shown in FIGS. 28 and 29, the difference between the fourth embodiment and the first embodiment is that the size of the SiC power MISFET formation region MR in the Y direction is increased and a plurality of SiC power MISFETs are mounted. It is. In the first embodiment, two SiC power MISFETs are connected in parallel. In the fourth embodiment, four SiC power MISFETs are connected in parallel, and these four SiC power MISFETs constitute one SiC power MISFET group. are doing.

By providing a plurality of SiC power MISFETs in the SiC power MISFET formation region MR in this manner, the size of the SiC power MISFET formation region MR is smaller than forming a pair of SiC power MISFETs and SiC-SBD in the active region 6. Can shrink. That is, since the total area of the p ⁺⁺ -type body potential fixing region 15 located at the boundary between the SiC power MISFET formation region MR and the SiC-SBD formation region DR can be reduced, the SiC power occupied per semiconductor chip 1 can be reduced. The ratio of the MISFET formation region MR can be reduced. As a result, it is possible to reduce the ON resistance and the _Vf of the SBD.

  Also, even when a plurality of SiC power MISFETs are provided in the SiC power MISFET formation region MR as in the fourth embodiment, the trench with respect to the trench size (L2 + L3) does not depend on the device size, as in the first embodiment. By adjusting the ratio of the depth H of TR, that is, the value of H / (L2 + L3), the channel resistance can be changed and the increase in the channel resistance can be suppressed.

  The technology disclosed in the fourth embodiment can be applied to the semiconductor devices in the second and third embodiments.

(Embodiment 5)
The semiconductor device described in each of the above embodiments can be used for a power converter that converts DC power to AC power, such as an inverter. The following describes a power conversion device according to Embodiment 5 with reference to FIG. FIG. 30 is a circuit diagram showing a power conversion device.

  As shown in FIG. 30, the inverter 102 has a SiC power MISFET 104 and a SiC-SBD 105 as switching elements. The SiC power MISFET 104 and the SiC-SBD 105 are formed in the same semiconductor chip, the SiC power MISFET 104 is the SiC power MISFET described in each of the above embodiments, and the SiC-SBD 105 is This is the SiC-SBD described in the embodiment. In the drawing, the body diode in the SiC power MISFET 104 is also shown.

  In each single phase, SiC power MISFET 104 and SiC-SBD 105 are connected in anti-parallel between power supply voltage Vcc and input potential of load (motor) 101 (upper arm), and input potential of load 101 and ground. The SiC power MISFET 104 and the SiC-SBD 105 are also connected in anti-parallel with the potential GND (lower arm). That is, in the load 101, two SiC power MISFETs 104 and two SiC-SBDs 105 are provided for each single phase, and six SiC power MISFETs 104 and six SiC-SBDs 105 are provided for three phases. Then, a control circuit 103 is connected to each gate electrode of the SiC power MISFET 104, and the control circuit 103 controls the SiC power MISFET 104. Therefore, by controlling the current flowing through the SiC power MISFET 104 constituting the inverter 102 by the control circuit 103, the DC power can be converted to the AC power and the load 101 can be driven.

  The function of the SiC power MISFET 104 constituting the inverter 102 will be described below. In order to control and drive the load 101, it is necessary to input a sine wave of a desired voltage to the load 101. The control circuit 103 controls the SiC power MISFET 104 and performs a pulse width modulation operation for dynamically changing the pulse width of the rectangular wave. The output rectangular wave is smoothed by passing through the inductor, and becomes a pseudo desired sine wave. The SiC power MISFET 104 has a function of generating a rectangular wave for performing the pulse width modulation operation.

  As described above, according to the fifth embodiment, by using the semiconductor device described in each of the above-described embodiments for SiC power MISFET 104, the power conversion device such as inverter 102 is equivalent to the high performance of SiC power MISFET 104. Can be improved in performance. Further, since the SiC power MISFET 104 has long-term reliability, the service life of the power converter can be extended.

  Further, the power converter can be used for a three-phase motor system. The load 101 shown in FIG. 30 is a three-phase motor, and by using the semiconductor device described in each of the above embodiments for the inverter 102, the performance of the three-phase motor system is increased and the service life is extended. Can be realized.

(Embodiment 6)
The three-phase motor system described in Embodiment 5 can be used for a vehicle such as a hybrid vehicle, an electric vehicle, or a fuel cell vehicle. An electric vehicle will be described below as an example of a vehicle using the three-phase motor system according to Embodiment 6 with reference to FIGS. FIG. 31 is a schematic diagram showing a configuration of an electric vehicle according to the sixth embodiment. FIG. 32 is a circuit diagram showing a boost converter according to the sixth embodiment.

  As shown in FIG. 31, the electric vehicle includes a three-phase motor 203 that can input and output power to and from a drive shaft 202 connected to the drive wheels 201a and 201b, and an inverter for driving the three-phase motor 203. 204 and a battery 205. Further, the electric vehicle includes a boost converter 208, a relay 209, and an electronic control unit 210. Boost converter 208 is connected to power line 206 connected to inverter 204 and power line 207 connected to battery 205.

  The three-phase motor 203 is a synchronous generator motor including a rotor in which permanent magnets are embedded and a stator in which three-phase coils are wound. The inverter 102 described in Embodiment 5 can be used as the inverter 204 in Embodiment 6.

  As shown in FIG. 32, boost converter 208 has a configuration in which reactor 211 and smoothing capacitor 212 are connected to inverter 213. Inverter 213 is similar to inverter 102 described in the fifth embodiment.

  An electronic control unit 210 in FIG. 31 includes a microprocessor, a storage device, and an input / output port, and receives a signal from a sensor for detecting a rotor position of the three-phase motor 203, a charge / discharge value of the battery 205, and the like. To receive. Further, electronic control unit 210 outputs a signal for controlling inverter 204, boost converter 208 and relay 209.

  Thus, according to the sixth embodiment, the power converter described in the fifth embodiment can be used for inverter 204 and boost converter 208 that are power converters. Further, the three-phase motor system described in Embodiment 5 can be used for a three-phase motor system including three-phase motor 203 and inverter 204. As a result, in the electric vehicle, lower energy, smaller size, lighter weight, and more efficient interior space can be achieved.

  Although the electric vehicle has been described in the fifth embodiment, the three-phase motor system according to each of the above-described embodiments can be applied to a hybrid vehicle that also uses an engine and a fuel cell vehicle in which the battery 205 is a fuel cell stack. Can be applied.

(Embodiment 7)
The three-phase motor system described in Embodiment 5 can be used for a railway vehicle. The following describes a railway vehicle using the three-phase motor system according to Embodiment 7 with reference to FIG. FIG. 33 is a schematic diagram showing a configuration of a railway vehicle according to the seventh embodiment.

  As shown in FIG. 33, electric power is supplied to the railway vehicle from an overhead line OW (for example, 25 kV) via a pantograph PG. In FIG. 33, reference numeral RT indicates a line, and reference numeral WH indicates a wheel.

  The voltage is reduced to 1.5 kV via the transformer 305, and the power is converted from AC to DC in the converter 303. Further, in the inverter 302, electric power is converted from direct current to alternating current via the capacitor 304, and the load 301, which is a three-phase motor, is driven. The railroad train is accelerated by rotating the wheels WH on the track RT by the load 301.

  Inverter 302 is similar to inverter 102 described in the fifth embodiment. Further, the SiC power MISFET and SiC-SBD described in each of the above embodiments are applied to the element configuration in converter 303. Further, the load 101 described in Embodiment 5 can be used as the load 301. In FIG. 33, the control circuit 103 described in the fifth embodiment is omitted. As described above, the three-phase motor system described in the fifth embodiment can be used for the three-phase motor system of the seventh embodiment. As a result, it is possible to reduce the energy consumption and the size and weight of the underfloor components in the railway vehicle.

  As described above, the invention made by the inventors of the present application has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and can be variously modified without departing from the gist thereof. .

DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Source wiring electrode 2a Source pad 3 Gate wiring electrode 3a Gate pad 4 n ⁺⁺ type guard ring 5 p ^- type floating field limiting ring (FLR)
6 active region 11 n-type semiconductor substrate 12 n ⁻ -type epitaxial layer 13 n ⁺ -type drain region 14 p ⁺ -type body region 15 p ⁺⁺ -type body potential fixed region 16 n-type JFET region 17 p ⁺ -type Electric field relaxation region 18 n ⁺ type current diffusion region 19 n ⁺⁺ type source region 20 gate insulating film 21 gate electrode 21 a conductive film 22 interlayer insulating film 23 barrier metal film 24 silicide layer 25 drain wiring electrode 26 silicide layer 27p ⁺⁺ type constricted region 101 Load 102 Inverter 103 Control circuit 104 SiC power MISFET
105 SiC-SBD
201a, 201b Drive wheel 202 Drive shaft 203 Three-phase motor 204 Inverter 205 Battery 206 Power line 207 Power line 208 Boost converter 209 Relay 210 Electronic control unit 211 Reactor 212 Smoothing capacitor 213 Inverter 301 Load 302 Inverter 303 Converter 304 Capacitor 305 Transformer CF Carbon film DR SiC-SBD formation region MP1 to MP10 Mask pattern MR SiC power MISFET formation region OP1, OP2 Opening OW Overhead wire P1 to P5 Large process PG Pantograph RT Line S1 to S4 First side to fourth side TR Trench WH Wheel

Claims (15)

A semiconductor device having a first region where a MISFET is formed and a second region where a Schottky barrier diode is formed,
A first conductivity type semiconductor substrate;
A first electrode formed on a back surface side of the semiconductor substrate in the first region and the second region;
A first semiconductor layer of the first conductivity type formed on the semiconductor substrate in the first region and the second region;
A first impurity region formed in the first semiconductor layer in the first region and having a second conductivity type opposite to the first conductivity type;
In the first region, the second impurity region of the first conductivity type and the third impurity of the first conductivity type formed in the first impurity region and having an impurity concentration higher than that of the first semiconductor layer. Area and
A bottom surface located in the first impurity region, a first side surface in contact with the second impurity region, and a second side surface in contact with the third impurity region and facing the first side surface; A trench penetrating the second impurity region in one region;
A gate electrode formed in the trench via a gate insulating film;
An interlayer insulating film formed on the gate electrode,
A second electrode formed on the interlayer insulating film, electrically connected to the second impurity region in the first region, and electrically connected to the first semiconductor layer in the second region;
A semiconductor device having: The semiconductor device according to claim 1,
A first opening for opening the second impurity region in the first region and the first semiconductor layer in the second region is formed in the interlayer insulating film;
The semiconductor device, wherein the second electrode is formed on the interlayer insulating film and in the first opening. The semiconductor device according to claim 1,
A second opening that opens the second impurity region in the first region, and a third opening that opens the first semiconductor layer in the second region, in the interlayer insulating film;
The semiconductor device, wherein the second electrode is formed on the interlayer insulating film, in the second opening, and in the third opening. The semiconductor device according to claim 3,
The second electrode includes a barrier metal film and a conductive film formed on the barrier metal film,
A silicide layer made of a material different from that of the barrier metal film is formed between the barrier metal film and the second impurity region in the second opening;
The semiconductor device, wherein the barrier metal film is in direct contact with the first semiconductor layer in the third opening. The semiconductor device according to claim 1,
The semiconductor device, wherein the plurality of fourth impurity regions of the second conductivity type are formed in the first semiconductor layer in the second region. The semiconductor device according to claim 1,
A fifth impurity region of the second conductivity type having a higher impurity concentration than the first impurity region is formed in the first impurity region;
The semiconductor device, wherein the fifth impurity region is located between the second impurity region in the first region and the first semiconductor layer in the second region. The semiconductor device according to claim 1,
The trench extends in a first direction in a plan view,
The first side surface and the second side surface are side surfaces perpendicular to the first direction, respectively.
A semiconductor device, wherein the plurality of trenches are formed so as to be adjacent to each other in a second direction orthogonal to the first direction. The semiconductor device according to claim 7,
When the depth of the trench is H, the width of the trench in the second direction is L2, and the distance between two adjacent trenches in the second direction is L3, the value of H / (L2 + L3) is , 0.25 or more and 5.00 or less. The semiconductor device according to claim 8, wherein
The channel resistance of the MISFET is adjusted by adjusting the value of H / (L2 + L3) without depending on the total size of the first region and the second region in the first direction. A semiconductor device that is capable of.   A power converter having the semiconductor device according to claim 1 as a switching element.   A three-phase motor system for driving a three-phase motor by converting DC power to AC power with the power converter according to claim 10.   An automobile having wheels driven by the three-phase motor system according to claim 11.   A railway vehicle that drives wheels with the three-phase motor system according to claim 11. A method of manufacturing a semiconductor device having a first region in which a MISFET is formed and a second region in which a Schottky barrier diode is formed,
(A) preparing the first conductivity type semiconductor substrate on which the first conductivity type epitaxial layer is formed;
(B) forming a first impurity region of a second conductivity type opposite to the first conductivity type in the epitaxial layer in the first region;
(C) forming, in the first region, a second impurity region of the first conductivity type and a third impurity region of the first conductivity type having a higher impurity concentration than the epitaxial layer in the first impurity region; Process,
(D) a bottom surface located in the first impurity region, a first side surface in contact with the second impurity region, and a second side surface in contact with the third impurity region and facing the first side surface, and Forming a trench through the second impurity region in the first region;
(E) forming a gate insulating film in the trench;
(F) forming a gate electrode on the gate insulating film so as to fill the trench;
(G) forming an interlayer insulating film on the gate electrode;
(H) forming a second electrode electrically connected to the second impurity region in the first region and electrically connected to the first semiconductor layer in the second region on the interlayer insulating film; Process,
(I) forming a first electrode on the back side of the semiconductor substrate in the first region and the second region;
A method for manufacturing a semiconductor device having: The method for manufacturing a semiconductor device according to claim 14,
(J) Between the step (g) and the step (h), a first opening reaching the second impurity region is formed in the first region by dry etching in the interlayer insulating film. Process,
(K) after the step (j), a step of forming a silicide layer on the second impurity region in the first opening;
(L) after the step (k), in the second region, forming a second opening reaching the epitaxial layer in the interlayer insulating film by wet etching;
Further having
In the step (h), the second electrode is formed so as to directly contact the silicide layer in the first opening, and is formed so as to directly contact the epitaxial layer in the second opening. A method for manufacturing a semiconductor device.

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