JP6336055B2 - Semiconductor device, semiconductor device manufacturing method, power conversion device, three-phase motor system, automobile, and railway vehicle - Google Patents

Description

  The present invention relates to a semiconductor device, a method for manufacturing a semiconductor device, a power conversion device, a three-phase motor system, an automobile, and a railway vehicle, and more particularly to improvement in reliability.

  2. Description of the Related Art Conventionally, in a power metal insulating semiconductor field effect transistor (MISFET), which is one of power semiconductor devices, a power MISFET using a silicon (Si) substrate (hereinafter referred to as Si power MISFET) is used. Was the mainstream.

  In contrast, a power MISFET (hereinafter referred to as a SiC power MISFET) using a silicon carbide (SiC) substrate (hereinafter referred to as a SiC substrate) can have a higher breakdown voltage and a lower loss than a Si power MISFET. It is. For this reason, particular attention is focused in the field of power-saving or environment-friendly inverter technology.

  The SiC power MISFET can reduce the on-resistance at the same breakdown voltage as compared with the Si power MISFET. This is because silicon carbide (SiC) has a dielectric breakdown electric field strength that is about seven times larger than that of silicon (Si), and the epitaxial layer serving as a drift layer can be thinned. However, considering the original characteristics that should be obtained from silicon carbide (SiC), it cannot be said that sufficient characteristics have been obtained yet, and further reduction of the on-resistance is desired from the viewpoint of efficient use of energy. ing.

  One of the problems to be solved with respect to the on-resistance of a SiC power MISFET having a DMOS (Double diffused Metal Oxide Semiconductor) structure is a channel parasitic resistance. In a low withstand voltage 600V withstand voltage DMOS, the channel parasitic resistance is the main cause of the parasitic resistance, and in a high withstand voltage 3300V withstand voltage DMOS, it is next to the drift resistance. Therefore, this reduction in channel parasitic resistance is necessary for the SiC power MISFET.

  The cause of the high channel parasitic resistance is the low channel mobility of the Si (0001) plane, which is the DMOS channel plane. In order to solve this problem, for example, as described in Patent Document 1, a trench is formed so as to dig a groove in a part of the p-type body layer of the DMOS and outside the body layer. A method for widening the typical channel width is disclosed. In order to reduce the channel parasitic resistance, the use of the (11-20) plane or (1-100) plane from which high channel mobility can be obtained has been studied. In order to use a surface with high channel mobility such as the (11-20) plane or the (1-100) plane, it is necessary to form a MOSFET structure having a trench structure on the (0001) plane substrate. However, in the MOSFET structure of the trench type structure, the gate insulating film and a part of the gate are formed not only below the p-type body layer supporting the breakdown voltage but also directly above the drift layer. Is applied, leading to dielectric breakdown. Therefore, attempts have been made to relax the electric field applied to the gate insulating film while having a trench structure. Patent Document 2 discloses a method of relaxing an electric field applied to a gate insulating film by forming a part of a p-type body layer at a position lower than a gate insulating film formed under a trench.

International Publication No. 2010/110246 JP 2009-260253 A

  However, since both Patent Document 1 and Patent Document 2 are structures in which a part of the trench structure is exposed to the outside of the p-type body layer, the electric field applied to the gate insulating film is higher than that of a normal DMOS. Therefore, even if the initial breakdown voltage is equal to or higher than the desired breakdown voltage, the reliability of the gate insulating film decreases with time. Therefore, the inventors of the present application have studied a structure that can be expected to have high reliability by suppressing the electric field applied to the gate insulating film while being a trench type that can be expected to have high channel mobility.

  An object of the present invention is to provide a silicon carbide semiconductor device having high performance and high reliability by using a trench structure and suppressing an electric field applied to a gate insulating film below the trench. As a result, the technology which realizes high performance of the power conversion device, the three-phase motor system, the automobile, and the railway vehicle is provided.

  In the present invention, a first conductivity type semiconductor substrate, a drain electrode formed on the back side of the semiconductor substrate, a first conductivity type drift layer formed on the semiconductor substrate, and a first conductivity type source. A first conductivity type current diffusion layer electrically connected to the drift region, a second conductivity type body layer in contact with the source region and the current diffusion layer, a source region, a body layer, and a current A trench extending to the diffusion layer and shallower than the body layer and having a bottom surface in contact with the body layer; a gate insulating film formed on an inner wall of the trench; and a gate electrode formed on the gate insulating film; Thus, the above-described problem is solved.

  According to the present invention, a high performance and high reliability silicon carbide semiconductor device can be provided. As a result, high performance of the power conversion device, the three-phase motor system, the automobile, and the railway vehicle can be realized.

It is a principal part top view of the semiconductor chip of the Example of this invention. It is a principal part bird's-eye view of the SiC power MISFET structure of the Example of this invention. It is process drawing for demonstrating the manufacturing method of the semiconductor device of the Example of this invention. It is principal part sectional drawing of the manufacturing process of the semiconductor device for demonstrating the manufacturing process of the semiconductor device of the Example of this invention. It is principal part sectional drawing of the manufacturing process of the semiconductor device for demonstrating the manufacturing process of the semiconductor device of the Example of this invention. It is principal part sectional drawing of the manufacturing process of the semiconductor device for demonstrating the manufacturing process of the semiconductor device of the Example of this invention. It is principal part sectional drawing of the manufacturing process of the semiconductor device for demonstrating the manufacturing process of the semiconductor device of the Example of this invention. It is principal part sectional drawing of the manufacturing process of the semiconductor device for demonstrating the manufacturing process of the semiconductor device of the Example of this invention. It is a principal part top view of the manufacturing process of the semiconductor device for demonstrating the manufacturing process of the semiconductor device of the Example of this invention. FIG. 10 is a cross-sectional view of a main part taken along line AA ′ in FIG. FIG. 10 is a main part cross-sectional view taken along line BB ′ in FIG. It is principal part sectional drawing of the manufacturing process of the semiconductor device for demonstrating the manufacturing process of the semiconductor device of the Example of this invention. It is principal part sectional drawing of the manufacturing process of the semiconductor device for demonstrating the manufacturing process of the semiconductor device of the Example of this invention. It is principal part sectional drawing of the manufacturing process of the semiconductor device for demonstrating the manufacturing process of the semiconductor device of the Example of this invention. It is principal part sectional drawing of the manufacturing process of the semiconductor device for demonstrating the manufacturing process of the semiconductor device of the Example of this invention. It is principal part sectional drawing of the manufacturing process of the semiconductor device for demonstrating the manufacturing process of the semiconductor device of the Example of this invention. It is principal part sectional drawing of the manufacturing process of the semiconductor device for demonstrating the manufacturing process of the semiconductor device of the Example of this invention. It is a principal part top view which shows the positional relationship of the gate electrode of the polycrystalline silicon of the semiconductor chip of the Example of this invention, a source contact part, and a gate contact part. It is principal part sectional drawing of the manufacturing process of the semiconductor device for demonstrating the manufacturing process of the semiconductor device of the Example of this invention. It is principal part sectional drawing of the manufacturing process of the semiconductor device for demonstrating the manufacturing process of the semiconductor device of the Example of this invention. It is principal part sectional drawing of SiC power MISFET of the Example of this invention. It is a principal part top view which shows the positional relationship of the gate electrode of the polycrystalline silicon of the semiconductor chip of the Example of this invention, a source contact part, and a gate contact part. It is a circuit diagram of the power converter device (inverter) of the Example of this invention. It is a circuit diagram of the power converter device (inverter) of the Example of this invention. It is a block diagram of the electric vehicle of the Example of this invention. 1 is a circuit diagram of a boost converter according to an embodiment of the present invention. 1 is a configuration diagram of a railway vehicle according to an embodiment of the present invention. It is a principal part bird's-eye view of the SiC power MISFET structure of the Example of this invention. It is a principal part top view which shows the positional relationship of the gate electrode of the polycrystalline silicon of the semiconductor chip of the Example of this invention, a source contact part, and a gate contact part. It is principal part sectional drawing of the manufacturing process of the semiconductor device for demonstrating the manufacturing process of the semiconductor device of the Example of this invention. It is principal part sectional drawing of the manufacturing process of the semiconductor device for demonstrating the manufacturing process of the semiconductor device of the Example of this invention. It is principal part sectional drawing of the manufacturing process of the semiconductor device for demonstrating the manufacturing process of the semiconductor device of the Example of this invention. It is a principal part bird's-eye view of the SiC power MISFET structure of the Example of this invention. It is principal part sectional drawing of the manufacturing process of the semiconductor device for demonstrating the manufacturing process of the semiconductor device of the Example of this invention. It is principal part sectional drawing of the manufacturing process of the semiconductor device for demonstrating the manufacturing process of the semiconductor device of the Example of this invention. It is principal part sectional drawing of the manufacturing process of the semiconductor device for demonstrating the manufacturing process of the semiconductor device of the Example of this invention. It is principal part sectional drawing of the manufacturing process of the semiconductor device for demonstrating the manufacturing process of the semiconductor device of the Example of this invention. It is principal part sectional drawing of the manufacturing process of the semiconductor device for demonstrating the manufacturing process of the semiconductor device of the Example of this invention.

  In the following embodiments, when necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other, and one is the other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the drawings used in the following embodiments, hatching may be added to make the drawings easy to see even if they are plan views. In all the drawings for explaining the following embodiments, components having the same function are denoted by the same reference numerals in principle, and repeated description thereof is omitted. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  An embodiment of a semiconductor device of the present invention will be described with reference to FIGS. FIG. 1 is a top view of an essential part of a semiconductor chip 1 of this embodiment having a plurality of vertical SiC power MISFET structures 6. FIG. 2 is a bird's-eye view of the main part of the SiC power MISFET structure 6.

  As shown in FIG. 1, a semiconductor chip 1 which is a semiconductor device of the present embodiment includes an active region (SiC) positioned below a source wiring electrode 2 in which a plurality of n-channel SiC power MISFET structures 6 are connected in parallel. A power MISFET formation region, an element formation region) and a peripheral formation region surrounding the active region in plan view. The peripheral formation region includes a plurality of p-type floating field limited rings (FLRs) 3 formed so as to surround the active region in a plan view, and the plurality of p-types in a plan view. An n-type guard ring 4 is formed so as to surround the type FLR 3.

On the surface side of the active region of an n-type silicon carbide (SiC) epitaxial substrate (hereinafter referred to as a SiC epitaxial substrate), a gate electrode of an SiC power MISFET, an n ⁺⁺ type source region, a channel region, and the like are formed. An n ⁺ type drain region of the SiC power MISFET is formed on the back surface side of the epitaxial substrate.

By forming a plurality of p-type FLRs 3 at the periphery of the active region, the maximum electric field portion sequentially moves to the outer p-type FLR 3 when off, and the outermost p-type floating field limiting ring 3 Therefore, the semiconductor chip 1 can have a high breakdown voltage. Although FIG. 1 illustrates an example in which three p-type FLRs 3 are formed, the present invention is not limited to this. The n ⁺⁺ type guard ring 4 has a function of protecting the SiC power MISFET formed in the active region.

  The plurality of SiC power MISFETs 6 formed in the active region have a stripe pattern in plan view, and the gate electrodes of all the SiC power MISFETs are gated by lead wires (gate bus lines) connected to the respective stripe patterns. The wiring electrode 8 is electrically connected.

Further, the plurality of SiC power MISFETs 6 are covered with the source wiring electrodes 2, and the source and body potential fixing layers of the respective SiC power MISFETs 6 are connected to the source wiring electrodes 2. The source wiring electrode 2 is connected to the external wiring through the opening 7 of the insulating film. The gate wiring electrode 8 is formed away from the source wiring electrode 2 and is connected to the gate electrode of each SiC power MISFET 6. The gate wiring electrode 8 is connected to an external wiring through the opening 5. Further, the n ⁺ -type drain region formed on the back side of the n-type SiC epitaxial substrate is electrically connected to a drain wiring electrode (not shown) formed on the entire back surface of the n-type SiC epitaxial substrate. doing.

  Next, the structure of the SiC power MISFET 6 of this embodiment will be described with reference to FIG.

On the ^{n +} -type SiC substrate made of silicon carbide (SiC) (substrate) 101 surface (first main surface) made of, ^{n +} -type low silicon carbide impurity concentration than SiC substrate 101 (SiC) n ^- A type epitaxial layer 102 is formed, and an SiC epitaxial substrate 104 is constituted by an n ⁺ type SiC substrate 101 and an n ⁻ type epitaxial layer 102 including a portion to become a drift layer. The thickness of the n ⁻ type epitaxial layer 102 is, for example, about 5 to 50 μm.

A p-type body layer (well region) 105 is formed in the n ⁻ -type epitaxial layer 102 with a predetermined depth (first depth) from the surface of the n ⁻ -type epitaxial layer 102. . Although not shown in FIG. 2, a p ⁺⁺ type body layer potential fixing region 106 is formed in contact with the p type body layer 105. Further, the p-type body layer 105 has a predetermined depth (third depth) from the surface of the n ⁻ -type epitaxial layer 102, is in contact with the p-type body layer 105, and nitrogen is introduced as an impurity. An n ⁺⁺ type source region 107 is formed. The epitaxial layer 102 between the p-type body layer 105 and the p-type body layer 105 is in contact with the p-type body layer 105 on both sides and has a predetermined depth (fourth) from the surface of the n ⁻ -type epitaxial layer 102. The n-type current diffusion layer 108 is formed with a depth. The current diffusion layer 108 is formed on the drift layer and is electrically connected to the drift layer. Since the fourth depth is shallower than the first depth, a p-type body layer 105 exists between the current diffusion layer 108 and the SiC substrate 101. Since the third depth is shallower than the first depth, p-type body layer 105 exists between source region 107 and SiC substrate 101.

A trench 109 having a predetermined depth (fifth depth) from the surface of the n ⁻ -type epitaxial layer 102 is formed in the p-type body layer 105. Here, the trench 109 extends so as to cover the n ⁺ -type source region 107 and the n-type current diffusion layer 108. The depth (fifth depth) of the trench 109 from the surface of the n ⁻ -type epitaxial layer 102 is shallower than the depth (first depth) of the p-type body layer 105. Since the depth (fifth depth) of the trench 109 is shallower than the depth (first depth) of the p-type body layer 105, the bottom surface of the trench 109 is in contact with the p-type body layer 105. In this embodiment, the trench 109 extends to the current diffusion layer 108 in a range above the region where the p-type body layer 105 exists between the current diffusion layer 108 and the SiC substrate 101. Further, trench 109 extends to source region 107 in a range above the region where p-type body layer 105 exists between source region 107 and SiC substrate 101. Therefore, the bottom surface of the trench 109 is surrounded by the p-type body layer 105. A gate insulating film 110 is formed on the surface of the trench 109, the surface of the p-type body layer 105, and the surface of the epitaxial layer 102 sandwiched between the p-type body layer 105. A gate electrode 111 is formed on the gate insulating film 110 above the p-type body layer 105.

The depth (first depth) of the p-type body layer 105 from the surface of the epitaxial layer 102 is, for example, about 0.5 to 2.0 μm. Further, the depth (third depth) of the n ⁺⁺ type source region 107 from the surface of the epitaxial layer 102 is shallower than the first depth, for example, about 0.1 to 0.6 μm. On the other hand, the depth (fourth depth) of the n ⁺ -type current diffusion layer region 108 from the surface of the epitaxial layer 102 is shallower than the first depth, for example, about 0.1 to 0.7 μm. The depth (fifth depth) of the trench 109 from the surface of the epitaxial layer 102 is shallower than the first depth, for example, about 0.1 to 1.5 μm. In this embodiment, the depth of the trench 109 from the surface of the epitaxial layer 102 (fifth depth) is deeper than the third depth and the fourth depth, but the fifth depth is the third depth and A configuration shallower than the fourth depth may be employed. In either the configuration in which the fifth depth is deeper than the third depth and the fourth depth and the fifth depth is shallower than the third depth and the fourth depth, the bottom surface of the trench 109 is a p-type body layer. Surrounded by 105. When the fifth depth is shallower than the third depth, the source region 107 exists between the bottom surface of the trench 109 in the source region 107 and the p-type body layer 105. When the fifth depth is shallower than the fourth depth, the current diffusion layer region 108 exists between the bottom surface of the trench 109 in the current diffusion layer region 108 and the p-type body layer 105. The length of the trench 109 in the direction parallel to the channel length is, for example, about 1 to 3 μm. The length of the trench 109 in the direction parallel to the channel width (that is, the trench width) is, for example, about 0.1 to 2 μm. The distance (trench interval) between the trench 109 and the trench 109 in the direction parallel to the channel width is, for example, about 0.1 to 2 μm. Although not shown, the depth (second depth) of the p ⁺⁺ type body layer potential fixing region 106 from the surface of the epitaxial layer 102 is, for example, about 0.1 to 0.3 μm.

Note that “−” and “+” are symbols representing the relative impurity concentration of the n-type or p-type conductivity. For example, in the case of the n-type, “n ⁻ ”, “n”, “n ⁺ ” ^. The impurity concentration of the n-type impurity increases in the order of “n ⁺⁺ ”.

A preferable range of the impurity concentration of the n ⁺ -type SiC substrate 101 is, for example, 1 × 10 ¹⁸ to 1 × 10 ²¹ cm ⁻³ , and a preferable range of the impurity concentration of the n ⁻ -type epitaxial layer 102 is, for example, 1 × 10 ¹⁴ to A preferable range of the impurity concentration of 1 × 10 ¹⁷ cm ⁻³ and the p-type body layer 105 is, for example, 1 × 10 ¹⁶ to 1 × 10 ¹⁹ cm ⁻³ . The preferable range of the impurity concentration of the n ⁺⁺ type source region 107 is, for example, 1 × 10 ¹⁹ to 1 × 10 ²¹ cm ⁻³ , and the preferable range of the impurity concentration of the n-type current diffusion region 108 is, for example, 5 × 10 ^{16 to} 5 × 10 ¹⁸ cm ⁻³ . A preferable range of the impurity concentration of the p ⁺⁺ type body layer potential fixing region 106 is, for example, a range of 1 × 10 ¹⁹ to 1 × 10 ²¹ cm ⁻³ .

  The channel region of the SiC power MISFET 6 of this embodiment is the surface of the trench 109 and the surface of the p-type body layer 105 sandwiched between the trenches 109. The JFET region is a region between the p-type body layer 105 and the p-type body layer 105. A gate insulating film 110 is formed on the channel region, and a gate electrode 111 is formed on the gate insulating film 110. However, the gate electrode 111 is not formed in a portion where the p-type body layer 105 is not provided below the JFET region.

  Next, characteristics of the SiC power MISFET 6 of this embodiment will be described with reference to FIG. As shown in FIG. 2, since the side surface of the trench 109 serves as a channel region, the semiconductor device of this example can be expected to have a higher channel mobility than the channel region on the surface of the SiC epitaxial substrate 104. Further, by forming the trench 109, the channel width is increased as compared with a normal DMOS not forming a trench, and a high current density can be expected. Furthermore, according to the present embodiment, since the side surface of the trench 109 becomes the channel region of the silicon carbide semiconductor device, when a 4 ° off Si (0001) plane substrate is used as the SiC substrate 101, the (11-20) plane ( 1-100) plane can be used as the channel plane. Therefore, a higher channel mobility can be expected as compared with the case where the surface of the (0001) plane of SiC substrate 101 is simply used as the channel region.

  Further, in the semiconductor device of this embodiment, since the trench 109 is shallower than the p-type body layer 105, the bottom surface of the trench 109 has the p-type body layer 105, which is compared with a normal trench structure MOSFET structure. The electric field applied to the gate insulating film formed on the trench surface when the withstand voltage is maintained can be greatly relaxed. Furthermore, in this embodiment, since the bottom surface of the trench 109 is surrounded by the p-type body layer 105 as described above, the electric field applied to the gate insulating film can be further reduced. As described above, it is possible to provide a SiC power MOSFET that achieves both high current density equivalent to that of a normal trench type SiC power MOSFET with high channel mobility and wide channel width, and high reliability due to high insulation film reliability. Is possible. Further, the end portion of the gate electrode 111 of this embodiment is formed in the range above the p-type body layer 105. That is, p-type body layer 105 exists between the end of gate electrode 111 and SiC substrate 101. Therefore, the gate electrode 111 is not formed on the JFET region where the p-type body layer 105 does not exist below, and the oxide film electric field on the JFET region at the time of holding the withstand voltage is greatly reduced as compared with the normal DMOS structure. Is possible.

  A method for manufacturing the semiconductor device of this embodiment will be described in the order of steps with reference to FIGS. FIG. 3 is a process diagram illustrating the method for manufacturing the semiconductor device of the present embodiment (processes P1 to P6). FIGS. 4 to 15, 17, and 18 are cross-sectional views of main parts showing an enlarged part of the SiC power MISFET 6 formation region (element formation region) of the semiconductor device of this example. FIG. 16 is a top view of an essential part of a semiconductor chip on which the SiC power MISFET 6 is mounted.

<Process P1>
First, as shown in FIG. 4, an n ⁺ -type 4H—SiC substrate 101 is prepared. An n-type impurity is introduced into the n ⁺ -type SiC substrate 101. The n-type impurity is, for example, nitrogen (N), and the impurity concentration of the n-type impurity is, for example, 1 × 10 ¹⁸ to 1 ×. The range is 10 ²¹ cm ⁻³ . The n ⁺ -type SiC substrate 101 has both a Si surface and a C surface, but the surface of the n ⁺ -type SiC substrate 101 may be either an Si surface or a C surface.

Next, an n ⁻ type epitaxial layer 102 of silicon carbide (SiC) is formed on the surface (first main surface) of the n ⁺ type SiC substrate 101 by an epitaxial growth method. In the n ⁻ type epitaxial layer 102, an n type impurity lower than the impurity concentration of the n ⁺ type SiC substrate 101 is introduced. The impurity concentration of the n ⁻ -type epitaxial layer 102 depends on the element rating of the SiC power MISFET, but is, for example, in a range of 1 × 10 ¹⁴ to 1 × 10 ¹⁷ cm ⁻³ . The thickness of the n ⁻ type epitaxial layer 102 is, for example, 5 to 50 μm. Through the above steps, SiC epitaxial substrate 104 including n ⁺ type SiC substrate 101 and n ⁻ type epitaxial layer 102 is formed.

<Process P2>
Then, ^{n +} -type rear surface of the SiC substrate 101 (second principal surface) from a predetermined depth up to the (sixth depth), ^{n +} -type on the back surface of the SiC substrate 101 of ^{n +} -type drain region 103 Form. The impurity concentration of the n ⁺ -type drain region 103 is, for example, in the range of 1 × 10 ¹⁹ to 1 × 10 ²¹ cm ⁻³ .

Next, as shown in FIG. 5, a mask M <b> 1 is formed on the surface of the n ⁻ type epitaxial layer 102. The thickness of the mask M1 is, for example, about 1.0 to 3.0 μm. The width of the mask M1 in the element formation region is, for example, about 1.0 to 5.0 μm. As the mask material, an inorganic material SiO ₂ film, Si film, SiN film, organic material resist film, or polyimide film can be used.

Next, for example, aluminum atoms (Al) are ion-implanted as p-type impurities into the n ⁻ -type epitaxial layer 102 through the mask M1. Thereby, the p-type body layer 105 is formed in the element formation region of the n ⁻ -type epitaxial layer 102. Although not shown, a p-type FLR 3 is simultaneously formed around the element formation region. The structure of the terminal portion is not limited to this, and may be, for example, a junction termination extension (JTE) structure.

The depth (first depth) of the p-type body layer 105 from the surface of the epitaxial layer 102 is, for example, about 0.5 to 2.0 μm. The impurity concentration of the p-type body layer 105 is, for example, in the range of 1 × 10 ¹⁶ to 1 × 10 ¹⁹ cm ⁻³ .

Next, as shown in FIG. 6, after removing the mask M1, the mask M2 is formed of, for example, a resist film. The thickness of the mask M2 is, for example, about 0.5 to 3 μm. An opening is provided only in a region where the potential fixing region 106 of the p ⁺⁺ type body layer for fixing the potential of the p type body layer 105 in a later step is formed.

Next, for example, aluminum atoms (Al) are ion-implanted as a p-type impurity into the n ⁻ -type epitaxial layer 102 through the mask M2, thereby forming a potential fixing region 106 of the p ⁺⁺ -type body layer. The depth (second depth) of the p ⁺⁺ type body layer potential fixing region 106 from the surface of the epitaxial layer 102 is, for example, about 0.1 to 0.3 μm. The impurity concentration of the p ⁺⁺ type body layer potential fixing region 106 is, for example, in the range of 1 × 10 ¹⁹ to 1 × 10 ²¹ cm ⁻³ .

Next, as shown in FIG. 7, after removing the mask M2, the mask M3 is formed of, for example, a resist film. The thickness of the mask M3 is, for example, about 0.5 to 3 μm. An opening is provided in a region where an n ⁺⁺ type source region 107 is formed in a later step. Although not shown, an opening is also provided in a region where the guard ring 4 is formed on the outer periphery of the FLR 3.

Next, nitrogen atoms (N) are ion-implanted as n-type impurities into the n ⁻ -type epitaxial layer 102 through the mask M3 to form the n ⁺⁺ -type source region 107 in the element formation region. At this time, although not shown, an n ⁺⁺ type guard ring 4 is formed in the peripheral formation region. The depth (third depth) from the surface of the epitaxial layer 102 of the n ⁺⁺ type source region 107 and the n ⁺⁺ type guard ring 4 is, for example, about 0.1 to 0.6 μm. The impurity concentration of the n ⁺⁺ type source region 107 and the n ⁺⁺ type guard ring 4 is, for example, in the range of 1 × 10 ¹⁹ to 1 × 10 ²¹ cm ⁻³ .

Next, as shown in FIG. 8, after removing the mask M3, the mask M4 is formed of, for example, a resist film. The thickness of the mask M4 is, for example, about 0.5 to 3 μm. An opening is provided in a region where the n ⁺ -type current diffusion region 108 is formed in a later step.

Next, nitrogen atoms (N) are ion-implanted as n-type impurities into the n ⁻ -type epitaxial layer 102 through the mask M4 to form an n ⁺ -type current diffusion region 108 in the element formation region. The depth (fourth depth) of the n ⁺ -type current diffusion region 108 from the surface of the epitaxial layer 102 is, for example, about 0.1 to 0.7 μm. The impurity concentration of the n ⁺ -type current diffusion region 108 is, for example, in the range of 5 × 10 ^{16 to} 5 × 10 ¹⁸ cm ⁻³ .

<Process P3>
Next, after removing the mask M4, although not shown, a carbon (C) film is deposited on the front and back surfaces of the SiC epitaxial substrate 104 by, for example, plasma CVD. The thickness of the carbon (C) film is, for example, about 0.03 μm. After covering the front and back surfaces of SiC epitaxial substrate 104 with the carbon (C) film, heat treatment is performed on SiC epitaxial substrate 104 at a temperature of 1500 ° C. or higher for about 2 to 3 minutes. Thereby, each impurity ion-implanted into SiC epitaxial substrate 104 is activated. After the heat treatment, the carbon (C) film is removed by, for example, oxygen plasma treatment.

<Process P4>
Next, as shown in FIGS. 9A to 9C, a mask M5 is formed of a resist film, for example. FIG. 9A is a top view of relevant parts in the main manufacturing process of the semiconductor chip 1. FIG. 9B is a main-portion cross-sectional view taken along line AA ′ in FIG. FIG. 9C is a main-portion cross-sectional view taken along line BB ′ in FIG. The thickness of the mask M5 is, for example, about 0.5 to 3 μm. An opening is provided in a region where the trench 109 is formed in a later step.

  Next, a trench 109 is formed in the p-type body layer 105 using a dry etching process. The depth Z (fifth depth) of the trench 109 is, for example, about 0.1 to 1.5 μm. The length X of the trench 109 in the direction parallel to the channel length direction is, for example, about 1 to 3 μm. The width Y1 that is the length of the trench 109 in the direction orthogonal to the channel length direction is, for example, about 0.1 to 2 μm. An interval Y2 (trench interval) between the trenches 109 in the direction orthogonal to the channel length direction is, for example, about 0.1 to 2 μm.

<Process P5>
Next, as shown in FIG. 10, after removing the mask M <b> 5, a gate insulating film 110 is formed on the first main surface side surface including the inner wall of the trench 109. The gate insulating film 110 is made of, for example, a SiO ₂ film formed by a thermal CVD method. The thickness of the gate insulating film 110 is, for example, about 0.005 to 0.15 μm.

  Next, as shown in FIG. 11, an n-type polycrystalline silicon (Si) film 111 </ b> A is formed on the gate insulating film 110. The thickness of the n-type polycrystalline silicon (Si) film 111A is, for example, about 0.01 to 4 μm.

  Next, as shown in FIG. 12, using the mask M6 (photoresist film), the polycrystalline silicon (Si) film 111A is processed by a dry etching method to form the gate electrode 111. Next, as shown in FIG. At this time, the polycrystalline silicon (Si) film 111A on the JFET region sandwiched between the p-type body layers 105 is removed. Thereby, the end portion of the gate electrode 111 is formed above the p-type body layer 105.

  Next, although illustration is omitted, after removing the mask M6, the gate electrode 111 is light-oxidized. As conditions for light oxidation, for example, dry oxidation is 900 ° C. for about 30 minutes.

<Process P6>
Next, as shown in FIG. 13, an interlayer insulating film 112 is formed on the surface on the first main surface side so as to cover the gate electrode 111 and the gate insulating film 110 by, for example, a plasma CVD method.

Next, as shown in FIG. 14, using the mask M7 (photoresist film), the interlayer insulating film 112 and the gate insulating film 110 are processed by the dry etching method, and a part of the n ⁺⁺ type source region 107 and the p Opening CNT_S reaching ⁺⁺ type body layer potential fixing region 106 is formed.

Next, as shown in FIG. 15, after removing the mask M7, a part of the n ⁺⁺ type source region 107 and the p ⁺⁺ type body layer potential fixing region 106 exposed on the bottom surface of the opening CNT_S, respectively. A metal silicide layer 113 is formed on the surface.

Although illustration is omitted, first, as a first metal film by, for example, sputtering, nickel (for example, nickel) is formed so as to cover the inside (side surface and bottom surface) of the interlayer insulating film 112 and the opening CNT_S on the surface on the first main surface side. Ni) is deposited. The thickness of the first metal film is, for example, about 0.05 μm. Subsequently, by performing a silicidation heat treatment at 600 to 1000 ° C., the first metal film, part of the n ⁺⁺ type source region 107 and the p ⁺⁺ type body layer potential fixing region 106 are formed on the bottom surface of the opening CNT_S. As a metal silicide layer 113, a nickel silicide (NiSi) layer, for example, is exposed on the bottom surface of the opening CNT_S and part of the n ⁺⁺ type source region 107 and the p ⁺⁺ type It is formed on each surface of body layer potential fixing region 106. Subsequently, the unreacted first metal film is removed by a wet etching method. In the wet etching method, for example, sulfuric acid / hydrogen peroxide is used.

  Next, an opening CNT_G117 for gate contact is formed at the end of the element formation region. FIG. 16 shows the positions of the polycrystalline silicon gate electrode 111, the metal silicide film 113 as the source contact portion, and the opening CNT_G117 corresponding to the gate contact portion of the semiconductor chip on which the plurality of SiC power MISFETs are mounted according to the present embodiment. It is a principal part top view which shows a relationship. The formation portion of the opening CNT_G117 is a portion located at the string end of the element formed in a string shape. Although illustration is omitted, the interlayer insulating film 112 is processed using a mask (photoresist film) to form an opening CNT_G 117 reaching the gate electrode 111.

Next, as shown in FIG. 17, the inside of the opening CNT_S reaching the metal silicide film 113 formed on the surface of a part of the n ⁺⁺ type source region 107 and the p ⁺⁺ type body layer potential fixing region 106. And, for example, a titanium (Ti) film and titanium nitride (TiN) as the third metal film 114 on the surface on the first main surface side including the inside of the opening CNT_G117 (not shown) reaching the gate electrode 111. A laminated film composed of a film and an aluminum (Al) film is deposited. The thickness of the aluminum (Al) film is preferably 2.0 μm or more, for example. Subsequently, the third metal film 114 is processed to electrically connect a part of the n ⁺⁺ type source region 107 and the p ⁺⁺ type body layer potential fixing region 106 via the metal silicide layer 113 in the opening CNT_S. The source wiring electrode 2 connected to the gate electrode 111 and the gate wiring electrode 8 electrically connected through the gate electrode 111 and the opening CNT_G117 are formed.

Next, although not shown, an SiO ₂ film or a polyimide film is deposited as a passivation film so as to cover the gate wiring electrode 8 and the source wiring electrode 2.

  Next, although illustration is omitted, the passivation film is processed to form a passivation. At that time, the source electrode opening 7 and the gate electrode opening 5 are formed.

Next, although not shown, a second metal film is deposited on the back surface of the n ⁺ -type SiC substrate 101 by, for example, sputtering. The thickness of the second metal film is, for example, about 0.1 μm.

Next, as shown in FIG. 18, by applying the laser silicidation heat treatment, by reacting an SiC substrate 101 of the second metal film and the ^{n +} -type is formed on the back surface side of the SiC substrate 101 of ^{n +} -type A metal silicide layer 115 is formed so as to cover the n ⁺ -type drain region 103. Subsequently, a drain wiring electrode 116 is formed so as to cover the metal silicide layer 115. The drain wiring electrode 116 is formed by depositing a laminated film of a Ti film, a Ni film, and a gold (Au) film in a total thickness of 0.5 to 1 μm.

  Thereafter, external wirings are electrically connected to the source wiring electrode 2, the gate wiring electrode 8, and the drain wiring electrode 116, respectively. As described above, the semiconductor device of this embodiment can be manufactured.

  The difference between the present embodiment and the first embodiment described above is in the layout. In Example 1, the opening CNT_G117 is formed at the end of the element formation region. In this example, a part of the SiC power MISFET formation region (element formation region) of the silicon carbide semiconductor device of FIG. 19 is shown enlarged. As shown in the cross-sectional view of the main part, the opening CNT_G117 is formed on the element, and the gate wiring electrode formed in the opening CNT_G117 is connected to the gate electrode 111 of polycrystalline silicon.

  As described above, by providing the gate wiring electrode in the opening CNT_G117 on the element, FIG. 20 is a plan view of the main part, and the gate wiring electrode and the source contact portion in the opening CNT_G117 which is the gate contact portion. As shown in the positional relationship between the metal silicide layer 113 in the opening CNT_S and the gate electrode 111 of polycrystalline silicon, the gate electrode 111 can be formed in a string shape and connected to the gate wiring electrode 117 without being routed. it can. In addition to the square gate electrode 111 as shown in FIG. 20, a rectangle, a hexagon, a polygon, a circle, or the like can be selected. Further, the gate electrodes 111 as shown in FIG. 20 can be arranged in a staggered manner in addition to the lattice shape. The manufacturing method of the semiconductor device of this example is the same as that of Example 1, and the process chart of FIG. 3 is common to Example 1 and Example 2.

  Thus, according to this embodiment, the gate electrode 111 is formed in a string shape and connected to the gate wiring electrode in the opening CNT_G117 formed of a metal having a sheet resistance lower than that of polycrystalline silicon. Therefore, the gate resistance is small, and the delay during the switching operation can be suppressed. In addition, the channel width can be further increased when the gate electrode 111 is formed in a square shape rather than in a string shape. Therefore, the current density can be further increased as compared with the first embodiment. Therefore, higher performance than that of the first embodiment can be obtained.

  In this example, a power conversion device including the SiC power MISFET of Example 1 described above or the SiC power MISFET of Example 2 described above will be described. FIG. 21 is a circuit diagram of the power converter (inverter) of the present embodiment.

  As illustrated in FIG. 21, the inverter according to the present embodiment includes a SiC power MISFET 304 that is a switching element and a diode 305 in a power module 302. In each single phase, the SiC power MISFET 304 and the diode 305 are connected in antiparallel between the power supply voltage (Vcc) and the input potential of the load (for example, motor) 301 via the terminals 306 to 310 (upper arm). The SiC power MISFET element 304 and the diode 305 are also connected in antiparallel between the input potential of the load 301 and the ground potential (GND) (lower arm). In other words, the load 301 is provided with two SiC power MISFETs 304 and two diodes 305 in each single phase, and is provided with six switching elements 304 and six diodes 5 in three phases. A control circuit 303 is connected to the gate electrode of each SiC power MISFET 304 via terminals 311 and 312, and the SiC power MISFET 304 is controlled by the control circuit 303. Therefore, the inverter of the present embodiment can drive the load 301 by controlling the current flowing through the SiC power MISFET 304 constituting the power module 302 by the control circuit 303.

  The function of the SiC power MISFET 304 in the power module 302 will be described below. For example, in order to control and drive a motor as the load 301, it is necessary to input a sine wave having a desired voltage to the load 301. The control circuit 303 controls the SiC power MISFET 304 to perform a pulse width modulation operation that dynamically changes the pulse width of the rectangular wave. The output rectangular wave is smoothed by passing through the inductor, and becomes a pseudo desired sine wave. The SiC power MISFET 304 creates a rectangular wave for performing this pulse width modulation operation.

  By using the semiconductor device of the first embodiment or the second embodiment described above for the SiC power MISFET 304, for example, since the on-resistance of the SiC power MISFET 304 is small, the structure such as a heat sink for cooling is reduced, and the power module 302 can be reduced in size and weight, and thus the power converter can be reduced in size and weight. Moreover, since the reliability of the gate insulating film of the SiC power MISFET 304 is high, the life of the power module 302 can be extended.

  Moreover, the power converter device of a present Example can be made into a three-phase motor system. The load 301 shown in FIG. 20 described above is a three-phase motor, and a three-phase motor system is used by using the power conversion device including the semiconductor device described in the first embodiment or the second embodiment described above as a switching element. Can be reduced in size and performance.

  In this example, a power conversion device including the SiC power MISFET of Example 1 described above or the SiC power MISFET of Example 2 described above will be described. FIG. 22 is a circuit diagram showing the power conversion device (inverter) of this embodiment.

  As shown in FIG. 22, the inverter of this embodiment includes a SiC power MISFET 404 as a switching element in a power module 402. In each single phase, SiC power MISFET 404 is connected between the power supply voltage (Vcc) and the input potential of the load (for example, motor) 401 via terminals 405 to 409 (upper arm), and the input potential of load 401 is The SiC power MISFET element 404 is also connected between the ground potential (GND) and the ground potential (GND) (lower arm). That is, in the load 401, two SiC power MISFETs 404 are provided for each single phase, and six switching elements 404 are provided for three phases. A control circuit 403 is connected to the gate electrode of each SiC power MISFET 304 via terminals 410 and 411, and the SiC power MISFET 404 is controlled by the control circuit 403. Therefore, in the inverter of this embodiment, the load 401 can be driven by controlling the current flowing through the SiC power MISFET 404 in the power module 402 by the control circuit 403.

  The function of the SiC power MISFET 404 in the power module 402 will be described below. As one of the functions of the SiC power MISFET, the present embodiment also has a function of generating a rectangular wave for performing a pulse width modulation operation as in the third embodiment. In the present embodiment, the SiC power MISFET 404 also serves as the diode 305 of the third embodiment. For example, when the load 401 includes an inductance like a motor, when the SiC power MISFET 404 is turned OFF, the energy stored in the inductance must be released (return current). In the third embodiment, the diode 305 plays this role. On the other hand, in the present embodiment, since the synchronous rectification drive is used, the SiC power MISFET 404 plays a role of flowing a circulating current. In the synchronous rectification driving of the present embodiment, the gate of the SiC power MISFET 404 is turned ON during the return, and the SiC power MISFET 404 is reversely conducted.

  Therefore, the conduction loss during reflux is determined not by the characteristics of the diode but by the characteristics of the SiC power MISFET 404. Further, when performing synchronous rectification drive, in order to prevent the upper and lower arms from being short-circuited, a non-operation time is required in which both the upper and lower SiC power MISFETs are turned off. During this non-operation time, the built-in PN diode formed by the drift layer and the p-type body layer of the SiC power MISFET 404 is driven. However, the carrier distance of SiC is shorter than that of Si, and the loss during the non-operation time is small. For example, it is equivalent to the case where the diode 305 of the third embodiment is an SiC Schottky barrier diode.

  As described above, in this embodiment, by using the semiconductor device of the first embodiment or the second embodiment described above for the SiC power MISFET 404, for example, the loss during reflux is reduced by the high performance of the SiC power MISFET 404. And higher performance is possible. Further, since the reflux diode is not provided separately from the SiC power MISFET 404, the power module 402 can be further reduced in size.

  Moreover, the power converter device of a present Example can be made into a three-phase motor system. The load 401 shown in FIG. 21 is a three-phase motor, and the power module 402 includes the semiconductor device according to the first embodiment or the second embodiment described above, thereby reducing the size and performance of the three-phase motor system. Can be realized.

  The three-phase motor system described in the third or fourth embodiment can be used for vehicles such as hybrid vehicles, electric vehicles, and fuel cell vehicles. In this embodiment, an automobile equipped with a three-phase motor system will be described with reference to FIGS. FIG. 23 is a schematic diagram showing the configuration of the electric vehicle of this embodiment. FIG. 24 is a circuit diagram of the boost converter of this embodiment.

  As shown in FIG. 23, the electric vehicle of the present embodiment drives a three-phase motor 503 that allows power to be input / output to / from a drive shaft 502 to which the drive wheels 501a and 501b are connected, and the three-phase motor 503. An inverter 504 and a battery 505 are provided. Furthermore, the electric vehicle of this embodiment includes a boost converter 508, a relay 509, and an electronic control unit 510. The boost converter 508 is connected to a power line 506 to which an inverter 504 is connected and a battery 505. It is connected to the power line 507.

  The three-phase motor 503 is a synchronous generator motor including a rotor embedded with permanent magnets and a stator wound with a three-phase coil. As the inverter 504, the inverter described in the third embodiment or the fourth embodiment can be used.

  As shown in FIG. 24, boost converter 508 has a configuration in which a reactor 511 and a smoothing capacitor 112 are connected to inverter 513. For example, the inverter 513 is the same as the inverter described in the fourth embodiment, and the element configuration in the inverter is the same. Also in the present embodiment, the switching element is the SiC power MISFET 514 as in the fourth embodiment, and the synchronous rectification driving is performed.

  The electronic control unit 510 shown in FIG. 23 includes a microprocessor, a storage device, and an input / output port. Receive. Then, a signal for controlling inverter 504, boost converter 508, and relay 509 is output.

  Thus, according to the present embodiment, the power converters of the above-described third embodiment and the above-described fourth embodiment can be used for the inverter 504 and the boost converter 508 that are power converters. Further, the three-phase motor system of the third embodiment or the fourth embodiment described above can be used for a three-phase motor system including the three-phase motor 503 and the inverter 504. Thereby, the energy saving of an electric vehicle, size reduction, weight reduction, and space saving of a power converter device can be achieved.

  In the present embodiment, the electric vehicle has been described. However, the above-described three-phase motor system can be similarly applied to a hybrid vehicle that also uses an engine and a fuel cell vehicle in which the battery 505 is a fuel cell stack.

  The three-phase motor system of Example 3 and Example 4 can be used for a railway vehicle. In this embodiment, a railway vehicle using a three-phase motor system will be described with reference to FIG. FIG. 25 is a circuit diagram including a converter and an inverter of the railway vehicle of the present embodiment.

  As shown in FIG. 25, electric power is supplied to the railway vehicle from an overhead line OW (for example, 25 kV) via a pantograph PG. The voltage is stepped down to 1.5 kV via the transformer 609 and converted from alternating current to direct current by the converter 607. Further, the inverter 602 converts the direct current into the alternating current through the capacitor 608, and the three-phase motor as the load 601 is driven. The element configuration in the converter 607 may be a SiC power MISFET and a diode used together as in the third embodiment, or a SiC power MISFET alone as in the fourth embodiment.

  In this embodiment, the switching element is synchronously rectified and driven as the SiC power MISFET 604 as in the fourth embodiment. In FIG. 25, the control circuit described in the fourth embodiment is omitted. Moreover, in the figure, symbol RT indicates a track, and symbol WH indicates a wheel.

  As described above, according to the present embodiment, the converter 607 can use the power conversion device according to the third or fourth embodiment. Further, the three-phase motor system according to the third embodiment or the fourth embodiment can be used for the three-phase motor system including the load 601, the inverter 602, and the control circuit. As a result, energy saving of the railway vehicle and reduction in floor and weight by downsizing the underfloor parts including the three-phase motor system can be achieved.

  FIG. 26 shows a bird's-eye view of the main part of the SiC power MISFET of this example. The difference between the present embodiment and the first embodiment is that a part of the gate electrode 711 is left on the JFET region as shown in FIG. By leaving a part of the gate electrode 711 on the JFET region, it is not necessary to secure a margin for arrangement between the end of the gate electrode on the JFET region side and the end of the p-type body layer, thereby reducing the cell length. Can do. Therefore, the on-resistance can be further reduced.

  FIG. 27 shows a layout of the SiC power MISFET of this example. In the present embodiment, it is not necessary to connect a gate wiring electrode to the gate electrode 711 of each element as in the second embodiment, and the gate electrode 711 is routed as shown in FIG. A potential can be supplied. In this embodiment, the gate contact opening CNT_G717 is formed at the end of the element formation region. Therefore, the process of this embodiment is easier than that of the second embodiment, and the yield can be improved and the cost can be reduced.

  A method for manufacturing a silicon carbide semiconductor device according to the present embodiment will be described in the order of steps with reference to FIGS. FIGS. 28 to 30 are enlarged cross-sectional views illustrating a part of the SiC power MISFET structure formation region (element formation region) of the silicon carbide semiconductor device.

In the same manner as in Example 1 and Example 2, an n ⁻ type epitaxial layer 702 is formed on the surface (first main surface) of an n ⁺ type SiC substrate (substrate) 701 as shown in FIG. , An SiC epitaxial substrate 704 composed of an n ⁺ type SiC substrate 701 and an n ⁻ type epitaxial layer 702 is formed. The impurity concentration of the n ⁺ -type SiC substrate 701 is, for example, in the range of 1 × 10 ¹⁸ to 1 × 10 ²¹ cm ⁻³ , and the impurity concentration of the n ⁻ -type epitaxial layer 702 is 1 × 10 ¹⁴ to 1 × 10 6. It is in the range of ¹⁷ cm ⁻³ . Subsequently, an n ⁺ -type drain region 703 is formed on the back surface (second main surface) of the n ⁺ -type SiC substrate 701. The impurity concentration of the n ⁺ -type drain region 703 is, for example, in the range of 1 × 10 ¹⁹ to 1 × 10 ²¹ cm ⁻³ .

Next, for example, aluminum atoms (Al) are ion-implanted as p-type impurities into the n ⁻ -type epitaxial layer 702 through the mask (not shown). As a result, a p-type body layer 705 is formed in the element formation region of the n ⁻ -type epitaxial layer 702. Although illustration is omitted, a p-type FLR is formed around the element formation region at the time of ion implantation. The impurity concentration of the p-type body layer 705 is, for example, in the range of 1 × 10 ¹⁶ to 1 × 10 ¹⁹ cm ⁻³ .

Next, a p-type impurity, for example, aluminum atoms (Al) is ion-implanted into the n ⁻ -type epitaxial layer 702 through a mask (not shown). As a result, a potential fixing region 706 of the p ⁺⁺ type body layer is formed in the p type body layer 705. The impurity concentration of the potential fixing region 706 of the p ⁺⁺ type body layer is, for example, in the range of 1 × 10 ¹⁹ to 1 × 10 ²¹ cm ⁻³ .

Next, nitrogen atoms (N) are ion-implanted as n-type impurities into the n ⁻ -type epitaxial layer 702 through the mask to form an n ⁺⁺ -type source region 707 in the element formation region (not shown). . The impurity concentration of the n ⁺⁺ type source region 707 is, for example, in the range of 1 × 10 ¹⁹ to 1 × 10 ²¹ cm ⁻³ .

Next, nitrogen atoms (N) are ion-implanted as an n-type impurity into the n ⁻ -type epitaxial layer 702 through the mask to form an n ⁺ -type current diffusion region 708 in the element formation region (not shown). ). The impurity concentration of the n ⁺ -type current diffusion region 708 is, for example, in the range of 5 × 10 ^{16 to} 5 × 10 ¹⁸ cm ⁻³ .

Next, each ion-implanted impurity is activated (not shown). Next, a trench mask is formed, and a trench 709 is formed in the p-type body layer 705 using a dry etching process (not shown). Next, a gate insulating film 710 is formed on the surface on the first main surface side including the inner wall of the trench 709. The gate insulating film 710 is made of, for example, a SiO ₂ film formed by a thermal CVD method (not shown). The thickness of the gate insulating film 710 is, for example, about 0.005 to 0.15 μm.

  Next, as shown in FIG. 28, an n-type polycrystalline silicon (Si) film 711 </ b> A is formed on the gate insulating film 710. The thickness of the n-type polycrystalline silicon (Si) film 711A is, for example, about 0.01 to 4 μm.

  Next, as shown in FIG. 29, a polycrystalline silicon (Si) film 711A is processed by a dry etching method using a mask M6 '(photoresist film) to form a gate electrode 711. At this time, the polycrystalline silicon (Si) film 711A on the JFET region sandwiched between the p-type body layers 705 remains.

Thereafter, an interlayer insulating film 712 is formed (not shown), and an opening reaching a part of the n ⁺⁺ type source region 707 and the p ⁺⁺ type body layer potential fixing region 706 is formed (not shown). A metal silicide layer 713 is formed on the surface of the part (not shown). Next, an opening 717 for a gate contact is formed (not shown), a source wiring electrode 714 and a gate wiring electrode (not shown) are formed, and a passivation film (not shown) is formed. Next, as shown in FIG. 30, a metal silicide 715 and a drain electrode 716 are formed on the back surface side of the n ⁺ -type SiC substrate 701. Thereafter, external wirings are electrically connected to the source wiring electrode, the gate wiring electrode, and the drain wiring electrode, respectively.

  In this embodiment, since the cell length can be shortened as compared with Embodiment 1 and Embodiment 2, it is possible to further reduce the on-resistance by providing more cells on a semiconductor chip having the same area. In this embodiment, the gate electrode 711 can be routed like a wiring, the process is easy, the yield can be improved, and the cost can be reduced.

FIG. 31 shows a bird's-eye view of the main part of the SiC power MISFET of this example. The difference between the present embodiment and the seventh embodiment is that a thick insulating film 817 is formed on part of the p-type body layer 805 and the n ⁺ -type current diffusion region 808 and on the JFET region as shown in FIG. In the point. In this embodiment, the thick insulating film 817 is covered with the n ⁺ -type current diffusion region 808 in a range that does not affect the on-resistance, so that the on-resistance can be lowered similarly to the seventh embodiment. Further, by forming the thick insulating film 817 between the gate electrode 811 and the JFET region, the withstand voltage can be further increased as compared with the seventh embodiment.

  A method for manufacturing the silicon carbide semiconductor device of the present embodiment will be described in the order of steps with reference to FIGS. 32 to 36 are cross-sectional views of main parts showing a part of the SiC power MISFET structure formation region (element formation region) of the silicon carbide semiconductor device in an enlarged manner.

Similarly to Example 1 and Example 2, an n ⁻ type epitaxial layer 802 is formed on the surface (first main surface) of an n ⁺ type SiC substrate (substrate) 801 as shown in FIG. An SiC epitaxial substrate 804 composed of an n ⁺ type SiC substrate 801 and an n ⁻ type epitaxial layer 802 is formed. The impurity concentration of the n ⁺ -type SiC substrate 801 is, for example, in the range of 1 × 10 ¹⁸ to 1 × 10 ²¹ cm ⁻³ , and the impurity concentration of the n ⁻ -type epitaxial layer 802 is 1 × 10 ¹⁴ to 1 × 10 6. It is in the range of ¹⁷ cm ⁻³ . Subsequently, an n ⁺ type drain region 803 is formed on the back surface (second main surface) of the n ⁺ type SiC substrate 801. The impurity concentration of the n ⁺ -type drain region 803 is, for example, in the range of 1 × 10 ¹⁹ to 1 × 10 ²¹ cm ⁻³ .

Next, for example, aluminum atoms (Al) are ion-implanted as p-type impurities into the n ⁻ -type epitaxial layer 802 through the mask (not shown). Thus, a p-type body layer 805 is formed in the element formation region of the n ⁻ -type epitaxial layer 802. Although not shown, a p-type FLR is formed around the element formation region at the same time. The impurity concentration of the p-type body layer 805 is, for example, in the range of 1 × 10 ¹⁶ to 1 × 10 ¹⁹ cm ⁻³ .

Next, for example, aluminum atoms (Al) are ion-implanted as p-type impurities into the n ⁻ -type epitaxial layer 802 through the mask (not shown). As a result, the potential fixing region 806 of the p ⁺⁺ type body layer is formed in the p type body layer 805. The impurity concentration of the potential fixing region 806 of the p ⁺⁺ type body layer is, for example, in the range of 1 × 10 ¹⁹ to 1 × 10 ²¹ cm ⁻³ .

Next, nitrogen atoms (N) are ion-implanted as n-type impurities into the n ⁻ -type epitaxial layer 802 through the mask to form an n ⁺⁺ -type source region 807 in the element formation region (not shown). . The impurity concentration of the n ⁺⁺ type source region 807 is, for example, in the range of 1 × 10 ¹⁹ to 1 × 10 ²¹ cm ⁻³ .

Next, nitrogen atoms (N) are ion-implanted as an n-type impurity into the n ⁻ -type epitaxial layer 802 through the mask to form an n ⁺ -type current diffusion region 808 in the element formation region (not shown). ). The impurity concentration of the n ⁺ -type current diffusion region 808 is, for example, in the range of 5 × 10 ^{16 to} 5 × 10 ¹⁸ cm ⁻³ .

Next, each ion-implanted impurity is activated (not shown). Next, a trench mask is formed, and a trench 809 is formed in the p-type body layer 805 using a dry etching process (not shown). Next, as shown in FIG. 32, an insulating film 817 thicker than the gate insulating film is formed on the p-type body layer 805, a part on the n ⁺ -type current diffusion region 808, and the JFET region. For example, an oxide film is deposited by plasma CVD to 0.05 to 0.5 μm (not shown), a resist mask is formed, and then the oxide film is partially removed by wet etching, so that it is thicker than the gate insulating film. An insulating film 817 is formed (not shown).

Next, as shown in FIG. 33, a gate insulating film 810 is formed on the surface on the first main surface side including the inner wall of the trench 809. The gate insulating film 810 is made of, for example, a SiO ₂ film formed by a thermal CVD method (not shown). The thickness of the gate insulating film 810 is, for example, about 0.005 to 0.15 μm.

  Next, as shown in FIG. 34, an n-type polycrystalline silicon (Si) film 811 A is formed on the gate insulating film 810. The thickness of the n-type polycrystalline silicon (Si) film 811A is, for example, about 0.01 to 4 μm.

  Next, as shown in FIG. 35, a polycrystalline silicon (Si) film 811A is processed by a dry etching method using a mask M6 ″ (photoresist film) to form a gate electrode 811. At this time, the polycrystalline silicon (Si) film 811A on the JFET region sandwiched between the p-type body layers 805 remains.

Thereafter, an interlayer insulating film 812 is formed (not shown), and an opening reaching a part of the n ⁺⁺ type source region 807 and the p ⁺⁺ type body layer potential fixing region 806 is formed (not shown). A metal silicide layer 813 is formed on the surface of the part (not shown). Next, an opening 817 for a gate contact is formed (not shown), a source wiring electrode 814 and a gate wiring electrode (not shown) are formed, and a passivation film (not shown) is formed. Next, as shown in FIG. 36, a metal silicide 815 and a drain electrode 816 are formed on the back surface side of the n ⁺ -type SiC substrate 801. Thereafter, external wirings are electrically connected to the source wiring electrode, the gate wiring electrode, and the drain wiring electrode, respectively.

In this embodiment, since the insulating film 817 thicker than the gate insulating film is formed on a part of the n ⁺ -type current diffusion region 808 and on the JFET region, a higher withstand voltage can be obtained than in the seventh embodiment. it can.

1: Semiconductor chip, 2: Source wiring electrode (SiC power MISFET forming region, element forming region), 3: p-type floating field limiting ring, 4: n ⁺⁺ type guard ring, 5: gate opening Part: 6: SiC power MISFET structure, 7: source opening, 8: electrode for gate wiring, 101: n ⁺ type SiC substrate (substrate), 102: n ⁻ type epitaxial layer, 103: n ⁺ type drain Region: 104: SiC epitaxial substrate, 105: p-type body layer (well region), 106: p ^++- type body layer potential fixing region, 107: n ^++- type source region, 108: n ⁺ -type current diffusion region 109: trench, 110: gate insulating film, 111: gate electrode.

Claims (15)

A first conductivity type semiconductor substrate having a first impurity concentration;
A back electrode formed on the back side of the semiconductor substrate;
The first region of the first conductivity type having a second impurity concentration lower than the first impurity concentration formed on the semiconductor substrate;
The second region of the first conductivity type having a third impurity concentration;
The third region of the first conductivity type having a fourth impurity concentration higher than the second impurity concentration and lower than the third impurity concentration electrically connected to the first region;
A fourth region of a second conductivity type opposite to the first conductivity type, in contact with the second region and the third region;
The side surface on one end side is in contact with the second region, the side surface on the other end side on the opposite side is in contact with the third region, and the side surface of the intermediate portion located between the second region and the third region, and A bottom surface is in contact with the fourth region, and the trench extends between the second region and the third region and extends in parallel with the main surface of the semiconductor substrate ;
An insulating film formed on the inner wall of the trench;
And a gate electrode formed on the insulating film. In the semiconductor device according to claim 1,
4. The semiconductor device according to claim 1, wherein the fourth region exists between the portion of the third region in contact with the trench and the semiconductor substrate. In the semiconductor device according to claim 1,
The semiconductor device, wherein the fourth region exists between a portion of the second region in contact with the trench and the semiconductor substrate. In the semiconductor device according to claim 1,
The semiconductor device is characterized in that the fourth region exists between an end of the gate electrode and the semiconductor substrate. In the semiconductor device according to claim 1,
A semiconductor device characterized in that the semiconductor substrate is made of silicon carbide.   2. A power conversion device comprising the semiconductor device according to claim 1 as a switching element.   7. A three-phase motor system that converts direct-current power into alternating-current power by the power conversion device according to claim 6 and drives a three-phase motor.   8. An automobile that drives wheels with the three-phase motor system according to claim 7.   A railway vehicle that drives wheels with the three-phase motor system according to claim 7. A first conductivity type semiconductor substrate;
A drain electrode formed on the back side of the semiconductor substrate;
A drift layer of the first conductivity type having a first impurity concentration formed on the semiconductor substrate;
A source region of the first conductivity type having a second impurity concentration;
A current diffusion layer of the first conductivity type having a third impurity concentration higher than the first impurity concentration and lower than the second impurity concentration electrically connected to the drift layer;
A body layer of a second conductivity type opposite to the first conductivity type, in contact with the source region and the current diffusion layer;
A side surface on one end side is in contact with the source region, a side surface on the other end side on the opposite side is in contact with the current diffusion layer, and a side surface and a bottom surface of an intermediate portion located between the source region and the current diffusion layer are A trench that is in contact with the body layer, extends between the source region and the current diffusion layer, and extends in parallel with the main surface of the semiconductor substrate ;
A gate insulating film formed on the inner wall of the trench;
And a gate electrode formed on the gate insulating film. The semiconductor device according to claim 10,
The semiconductor device according to claim 1, wherein the body layer exists between the portion of the current diffusion layer in contact with the trench and the semiconductor substrate. The semiconductor device according to claim 10,
The semiconductor device is characterized in that the body layer exists between a portion of the source region in contact with the trench and the semiconductor substrate. The semiconductor device according to claim 10,
The semiconductor device is characterized in that the body layer exists between an end of the gate electrode and the semiconductor substrate. The semiconductor device according to claim 10,
A semiconductor device characterized in that the semiconductor substrate is made of silicon carbide. Preparing the first conductivity type silicon carbide semiconductor substrate in which the first conductivity type epitaxial layer having the first impurity concentration is formed;
Forming a first region of a second conductivity type opposite to the first conductivity type in the epitaxial layer by ion implantation of a second conductivity type impurity;
Forming a second region of the first conductivity type having a second impurity concentration in the first region by ion implantation of a first conductivity type impurity;
In the epitaxial layer, in a region partially including the first region spaced apart from the second region, a third impurity concentration that is higher than the first impurity concentration and lower than the second impurity concentration. Forming the third region of the first conductivity type by ion implantation of a first conductivity type impurity;
Forming a trench on the first region and extending between the second region and the third region and extending in parallel with the main surface of the silicon carbide semiconductor substrate ;
Forming an insulating film on the inner wall of the trench;
A method of manufacturing a semiconductor device, comprising forming a gate electrode on the insulating film.

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