JP7632084B2 - Semiconductor Device - Google Patents

Description

This disclosure relates to a semiconductor device.

Regarding semiconductor devices including transistors and diodes connected in parallel, a semiconductor device has been proposed in which the characteristics of the body diode built into the transistor are limited in order to prevent degradation due to electrical conduction (for example, Patent Document 1).

JP 2015-198228 A

In conventional semiconductor devices, excessive current flows through the diode when the transistor is turned off, which can prevent a sufficiently high inductive load (L load) avalanche resistance.

The present disclosure aims to provide a semiconductor device that can improve the inductive load avalanche resistance.

The semiconductor device disclosed herein includes a transistor and a Schottky barrier diode connected in parallel to the transistor, the transistor includes a first semiconductor substrate having a first main surface and a gate electrode formed on the first main surface, the gate electrode extending in a first direction along the <1-100> of the first semiconductor substrate, the Schottky barrier diode includes a second semiconductor substrate having a second main surface, the second semiconductor substrate includes a first semiconductor region of a first conductivity type constituting the second main surface and a second semiconductor region of a second conductivity type formed on the second main surface, the second semiconductor region extending in a second direction along the <11-20> of the second semiconductor substrate.

This disclosure makes it possible to improve the inductive load avalanche resistance.

FIG. 1 is a top view showing a semiconductor module according to an embodiment. FIG. 2 is a circuit diagram showing a semiconductor module according to the embodiment. FIG. 3 is a diagram showing a unit cell of the first transistor. FIG. 4 is a cross-sectional view showing the first transistor. FIG. 5 is a diagram showing a unit cell of the first diode. FIG. 6 is a cross-sectional view (part 1) showing the first diode. FIG. 7 is a cross-sectional view (part 2) showing the first diode. FIG. 8 is a diagram showing a unit cell of the second transistor. FIG. 9 is a cross-sectional view showing the second transistor. FIG. 10 is a diagram showing a unit cell of the second diode. FIG. 11 is a cross-sectional view (part 1) showing the second diode. FIG. 12 is a cross-sectional view (part 2) showing the second diode. FIG. 13 is a diagram showing the breakdown characteristics. FIG. 14 is a diagram showing a unit cell of a modified example of the first transistor. FIG. 15 is a diagram showing a unit cell of a modified example of the first diode.

The form for implementing this is explained below.

[Description of the embodiments of the present disclosure]
First, the embodiments of the present disclosure will be listed and described. In the following description, the same or corresponding elements are given the same symbols, and the same description will not be repeated. In the crystallographic description in this specification, individual orientations are represented by [], collective orientations by <>, individual planes by (), and collective planes by {}. In addition, when a crystallographic index is negative, it is usually represented by placing a "-" (bar) above the number, but in this specification, a negative sign is placed before the number.

[1] A semiconductor device according to one aspect of the present disclosure includes a transistor and a Schottky barrier diode connected in parallel to the transistor, the transistor includes a first semiconductor substrate having a first main surface and a gate electrode formed on the first main surface, the gate electrode extending in a first direction along the <1-100> of the first semiconductor substrate, the Schottky barrier diode includes a second semiconductor substrate having a second main surface, the second semiconductor substrate includes a first semiconductor region of a first conductivity type constituting the second main surface and a second semiconductor region of a second conductivity type formed on the second main surface, the second semiconductor region extending in a second direction along the <11-20> of the second semiconductor substrate.

In this semiconductor device, the transistor and Schottky barrier diode transition to the avalanche state at approximately the same applied voltage, suppressing the concentration of avalanche current in the transistor or diode and improving the inductive load avalanche resistance. In this disclosure, extending along a certain direction does not only mean extending strictly parallel to that direction, but also includes extending parallel to a direction tilted within 20° from that direction.

[2] In [1], an angle between the <1-100> of the first semiconductor substrate and the first direction may be a first angle, an angle between the <11-20> of the second semiconductor substrate and the second direction may be a second angle, the first angle may be 10° or less, and the second angle may be 10° or less. In this case, the inductive load avalanche resistance of the transistor and the inductive load avalanche resistance of the Schottky barrier diode may be brought closer to each other, which may suppress concentration of avalanche current in the transistor or diode and improve the inductive load avalanche resistance.

[3] In [1] or [2], the transistor may be multiple, and the multiple transistors may be connected in parallel to the Schottky barrier diode. In this case, a large current may easily flow. The number of transistors may be, for example, two, four, six, or twelve.

[4] In [1] to [3], the Schottky barrier diode may be multiple, and the Schottky barrier diodes may be connected in parallel to the transistor. In this case, it is easy to return the current. The number of the Schottky barrier diodes may be, for example, two, four, six, or twelve. The number of the transistors and the number of the Schottky barrier diodes may be the same or different.

[5] In any one of [1] to [4], the semiconductor device may have an upper arm and a lower arm connected in series to the upper arm, the upper arm including a first combination of the transistor and the Schottky barrier diode, and the lower arm including a second combination of the transistor and the Schottky barrier diode. In this case, the semiconductor device may be used in a power module including an upper arm and a lower arm, and the inductive load avalanche resistance of the power module may be improved.

[6] In [1] to [5], the Schottky barrier diode may have a mark that specifies the crystal orientation of the second semiconductor substrate. In this case, the Schottky barrier diode can be easily mounted on an insulating substrate or the like while taking into account the crystal orientation of the second semiconductor substrate.

[7] In [1] to [6], the first semiconductor substrate and the second semiconductor substrate may be silicon carbide substrates. Silicon carbide has anisotropy in dielectric breakdown strength, but by forming a structure according to the crystal orientation of the substrate, it is easy to improve the inductive load avalanche resistance.

[8] In [1] to [7], the transistor may have a plurality of first unit cells whose longitudinal direction is the first direction, and the Schottky barrier diode may have a plurality of second unit cells whose longitudinal direction is the second direction. In this case, in the transistor, dielectric breakdown occurs in one of the plurality of first unit cells, and in the Schottky barrier diode, dielectric breakdown occurs in one of the plurality of second unit cells, and an avalanche current flows in both the transistor and the Schottky barrier diode.

[9] In [1] to [8], the difference in breakdown voltage between the transistor and the Schottky barrier diode may be 100 V or less. In this case, it is particularly easy for an avalanche current to flow through both the transistor and the Schottky barrier diode.

[10] In [1] to [9], the breakdown voltage of the Schottky barrier diode may be higher than the breakdown voltage of the transistor. In this case, it is easy to reduce the difference between the breakdown voltage of the transistor and the breakdown voltage of the diode.

[11] In [1] to [10], the breakdown voltage of the transistor and the breakdown voltage of the Schottky barrier diode may be 600 V or more. In this case, the improved breakdown voltage makes it easier to use in many applications.

[Details of the embodiment of the present disclosure]
Hereinafter, the embodiments of the present disclosure will be described in detail, but the present embodiment is not limited thereto. In this specification and drawings, components having substantially the same functional configuration may be denoted by the same reference numerals to avoid redundant description. In this specification and drawings, the X1-X2 direction, the Y1-Y2 direction, and the Z1-Z2 direction are defined as mutually orthogonal directions. A plane including the X1-X2 direction and the Y1-Y2 direction is defined as the XY plane, a plane including the Y1-Y2 direction and the Z1-Z2 direction is defined as the YZ plane, and a plane including the Z1-Z2 direction and the X1-X2 direction is defined as the ZX plane. For convenience, the Z1 direction is defined as the upward direction, and the Z2 direction is defined as the downward direction. In addition, in this disclosure, planar view refers to viewing an object from the Z1 side.

This embodiment relates to a semiconductor module. FIG. 1 is a top view showing a semiconductor module according to an embodiment. FIG. 2 is a circuit diagram showing a semiconductor module according to an embodiment.

As shown in FIG. 1, the semiconductor module 100 according to the embodiment mainly includes a heat sink 121, a housing 122, a P terminal 101, an N terminal 102, an O terminal 103, a first conductive pattern 111, a second conductive pattern 112, and a third conductive pattern 113. The semiconductor module 100 further includes a first transistor 200, a second transistor 400, a first diode 300, and a second diode 500.

The heat sink 121 is, for example, a rectangular plate of uniform thickness in a plan view. The material of the heat sink 121 is a metal with high thermal conductivity, such as copper (Cu), a copper alloy, or aluminum (Al). The heat sink 121 is fixed to a cooler or the like using a thermal interface material (TIM) or the like.

The housing 122 is formed, for example, in a frame shape when viewed from above, and the outer shape of the housing 122 is the same as the outer shape of the heat sink 121. The material of the housing 122 is an insulating material such as resin. The housing 122 has a pair of side walls 191 and 192 facing each other, and a pair of end walls 193 and 194 connecting both ends of the side walls 191 and 192. The side walls 191 and 192 are arranged parallel to the ZX plane, and the end walls 193 and 194 are arranged parallel to the YZ plane. The side wall 191 is arranged on the Y1 side of the side wall 192, and the end wall 193 is arranged on the X1 side of the end wall 194.

The P terminal 101 and the N terminal 102 are arranged on the upper surface (surface on the Z1 side) of the end wall portion 193, and the O terminal 103 is arranged on the upper surface (surface on the Z1 side) of the end wall portion 194. For example, the N terminal 102 is arranged on the Y2 side of the P terminal 101. The P terminal 101, the N terminal 102, and the O terminal 103 are each made of a metal plate.

Inside the housing 122, an insulating substrate 123 is disposed on the Z1 side of the heat sink 121. The first conductive pattern 111, the second conductive pattern 112, and the third conductive pattern 113 are provided on the Z1 side surface of the insulating substrate 123. A conductive layer 114 (see Figures 4, 6, 7, 9, 11, and 12) is provided on the Z2 side surface of the insulating substrate 123. The conductive layer 114 is joined to the heat sink 121 by a joining material (not shown) such as solder.

The P terminal 101 is electrically connected to the first conductive pattern 111, the O terminal 103 is electrically connected to the second conductive pattern 112, and the N terminal 102 is electrically connected to the third conductive pattern 113.

The first transistor 200 and the first diode 300 are provided on the first conductive pattern 111. The drain electrode 233 (see FIG. 4) of the first transistor 200 is joined to the first conductive pattern 111 using a bonding material 116 (see FIG. 4) such as solder. The cathode electrode 333 (see FIG. 6 and FIG. 7) of the first diode 300 is joined to the first conductive pattern 111 using a bonding material 117 (see FIG. 6 and FIG. 7) such as solder. The source electrode 232 (see FIG. 4) of the first transistor 200 is connected to the second conductive pattern 112 by a plurality of bonding wires 161. The anode electrode 332 (see FIG. 6 and FIG. 7) of the first diode 300 is connected to the source electrode 232 of the first transistor 200 by a plurality of bonding wires 171.

The second transistor 400 and the second diode 500 are provided on the second conductive pattern 112. The drain electrode 433 (see FIG. 9) of the second transistor 400 is joined to the second conductive pattern 112 using a bonding material 118 (see FIG. 9) such as solder. The cathode electrode 533 (see FIG. 11 and FIG. 12) of the second diode 500 is joined to the second conductive pattern 112 using a bonding material 119 (see FIG. 11 and FIG. 12) such as solder. The source electrode 432 (see FIG. 9) of the second transistor 400 is connected to the third conductive pattern 113 by a plurality of bonding wires 162. The anode electrode 532 (see FIG. 11 and FIG. 12) of the second diode 500 is connected to the source electrode 432 of the second transistor 400 by a plurality of bonding wires 172.

2, the first transistor 200 and the second transistor 400 are connected in series between the P terminal 101 and the N terminal 102, and the O terminal 103 is connected between the first transistor 200 and the second transistor 400. The first diode 300 is connected in parallel to the first transistor 200, and the second diode 500 is connected in parallel to the second transistor 400. An upper arm 181 including the first transistor 200 and the first diode 300 is configured, and a lower arm 182 including the second transistor 400 and the second diode 500 is configured. The combination of the first transistor 200 and the first diode 300 is an example of a first combination, and the combination of the second transistor 400 and the second diode 500 is an example of a second combination.

[First transistor 200]
Next, a detailed description will be given of the first transistor 200. Fig. 3 is a diagram showing a unit cell of the first transistor 200, and Fig. 4 is a cross-sectional view showing the first transistor 200. Fig. 4 corresponds to a cross-sectional view taken along line IV-IV in Fig. 3.

The first transistor 200 mainly has a silicon carbide substrate 210, a gate electrode 231, a source electrode 232, and a drain electrode 233.

The silicon carbide substrate 210 includes a silicon carbide single crystal substrate 206 and a silicon carbide epitaxial layer 207 on the silicon carbide single crystal substrate 206. The silicon carbide substrate 210 has a main surface 210A and a main surface 210B opposite to the main surface 210A. The silicon carbide epitaxial layer 207 constitutes the main surface 210A, and the silicon carbide single crystal substrate 206 constitutes the main surface 210B. The shape of the silicon carbide substrate 210 is, for example, a rectangular parallelepiped. The main surface 210A is a surface perpendicular to the Z1-Z2 direction. <1-100> is a direction parallel to the Y1-Y2 direction. The silicon carbide single crystal substrate 206 and the silicon carbide epitaxial layer 207 are composed of, for example, hexagonal silicon carbide of polytype 4H. Silicon carbide single crystal substrate 206 contains n-type impurities such as nitrogen (N) and has n-type. Silicon carbide substrate 210 is an example of a first semiconductor substrate, and main surface 210A is an example of a first main surface.

The main surface 210A is a surface in which (0001) is tilted in the off direction. For example, the off direction is [11-20]. For example, the main surface 210A is a surface in which (0001) is tilted in the off direction ([11-20]) at an off angle of 8° or less. The off angle may be, for example, 1° or more, or 2° or more. The off angle may be 6° or less, or 4° or less.

[11-20] is an orientation within (0001). However, since the main surface 210A is a surface inclined in the off-direction from (0001), [11-20] is not an orientation within the main surface 210A. The X1 direction corresponds to the orientation of [11-20] projected onto the main surface 210A, and the X2 direction corresponds to the orientation of [-1-120] projected onto the main surface 210A.

The first transistor 200 has an active region 201 and a termination region 202 disposed around the active region 201.

In the active region 201, the silicon carbide epitaxial layer 207 mainly has a drift region 211, a body region 212, a source region 213, a contact region 214, and an electric field relaxation region 215.

The drift region 211 contains n-type impurities such as nitrogen (N) and has n-type conductivity. The drift region 211 constitutes the main surface 210B. The body region 212 is in contact with the drift region 211. The body region 212 contains p-type impurities such as aluminum (Al) and has p-type conductivity. The source region 213 is provided on the body region 212 so as to be separated from the drift region 211 by the body region 212. The source region 213 contains n-type impurities such as nitrogen or phosphorus (P) and has n-type conductivity. The source region 213 constitutes a part of the main surface 210A. The silicon carbide epitaxial layer 207 may have a buffer layer under the drift region 211.

A plurality of gate trenches 220 are provided in the main surface 210A. The plurality of gate trenches 220 extend parallel to the Y1-Y2 direction and are arranged side by side in the X1-X2 direction. The gate trenches 220 are defined by a side surface 221 and a bottom surface 222. The bottom surface 222 is continuous with the side surface 221. The side surface 221 penetrates the source region 213 and the body region 212. The side surface 221 reaches the drift region 211. The bottom surface 222 is located in the drift region 211. The bottom surface 222 is approximately parallel to the main surface 210A. The side surface 221 is composed of the source region 213, the body region 212, and the drift region 211. The bottom surface 222 is composed of the drift region 211.

A gate insulating film 217 is formed in the gate trench 220, contacting the side surface 221 and the bottom surface 222. The gate insulating film 217 contacts the drift region 211 at the bottom surface 222. The gate insulating film 217 contacts the source region 213, the body region 212, and the drift region 211 at the side surface 221.

The gate electrode 231 is provided on the gate insulating film 217. The gate electrode 231 is made of, for example, polysilicon containing conductive impurities. The gate electrode 231 is disposed inside the gate trench 220. The gate electrode 231 faces the source region 213, the body region 212, and the drift region 211. The multiple gate electrodes 231 extend parallel to the Y1-Y2 direction and are disposed side by side in the X1-X2 direction. The multiple gate electrodes 231 extend along the <1-100> direction. The Y1-Y2 direction is an example of the first direction. In this embodiment, the first angle between the <1-100> direction of the silicon carbide substrate 210 and the first direction is 0°.

The contact region 214 is provided between adjacent gate trenches 220 in the X1-X2 direction, away from the side surface 221 of each gate trench 220, penetrating the source region 213, and in contact with the body region 212. The contact region 214 constitutes a part of the main surface 210A. The contact region 214 contains p-type impurities such as aluminum, and has a p-type conductivity.

The electric field relaxation region 215 is provided between adjacent gate trenches 220 in the X1-X2 direction, away from the side surface 221 of each gate trench 220, and extends from the body region 212 toward the main surface 210B. The electric field relaxation region 215 contains p-type impurities such as aluminum and has a p-type conductivity. The electric field relaxation region 215 has a lower end surface 215C, a first side end surface 215A, and a second side end surface 215B. The lower end surface 215C is approximately parallel to the XY plane. The first side end surface 215A and the second side end surface 215B are approximately parallel to the YZ plane. The first side end surface 215A is on the X1 side of the second side end surface 215B. The lower end surface 215C, the first side end surface 215A, and the second side end surface 215B are in contact with the drift region 211.

An interlayer insulating film 235 is provided to cover the gate trench 220 and the gate electrode 231. A contact hole 236 is formed in the interlayer insulating film 235 to expose a part of the source region 213 and the contact region 214.

The source electrode 232 is provided on the interlayer insulating film 235 and contacts the main surface 210A through the contact hole 236. The source electrode 232 is electrically connected to the source region 213 and the contact region 214. The interlayer insulating film 235 electrically insulates the gate electrode 231 and the source electrode 232.

The drain electrode 233 contacts the major surface 210B. The drain electrode 233 is electrically connected to the drift region 211.

The first transistor 200 includes a plurality of first unit cells 203 in the active region 201, which are units of the periodic pattern of the gate trenches 220. The plurality of first unit cells 203 are aligned in the X1-X2 direction with the Y1-Y2 direction as their longitudinal direction. The plurality of first unit cells 203 extend along the <1-100> direction.

The termination region 202 is, for example, a region having a circular planar shape, and constitutes a part of the main surface 210A. The termination region 202 contains p-type impurities such as aluminum, and has a p-type conductivity.

In the first transistor 200, when a voltage is applied between the source electrode 232 and the drain electrode 233, the electric field tends to concentrate in the electric field relaxation region 215 at the first corner 216A where the bottom end surface 215C intersects with the first side end surface 215A and at the second corner 216B where the bottom end surface 215C intersects with the second side end surface 215B.

[First diode 300]
Next, the first diode 300 will be described in detail. The first diode 300 is a Schottky barrier diode having a JBS (Junction Barrier Schottky) structure. FIG. 5 is a diagram showing a unit cell of the first diode 300, and FIGS. 6 and 7 are cross-sectional views showing the first diode 300. FIG. 6 corresponds to a cross-sectional view taken along line VI-VI in FIG. 5. FIG. 7 corresponds to a cross-sectional view taken along line VII-VII in FIG. 5.

The first diode 300 mainly has a silicon carbide substrate 310, an anode electrode 332, and a cathode electrode 333.

The silicon carbide substrate 310 includes a silicon carbide single crystal substrate 306 and a silicon carbide epitaxial layer 307 on the silicon carbide single crystal substrate 306. The silicon carbide substrate 310 has a main surface 310A and a main surface 310B opposite to the main surface 310A. The silicon carbide epitaxial layer 307 constitutes the main surface 310A, and the silicon carbide single crystal substrate 306 constitutes the main surface 310B. The shape of the silicon carbide substrate 310 is, for example, a rectangular parallelepiped. The main surface 310A is a surface perpendicular to the Z1-Z2 direction. <1-100> is a direction parallel to the Y1-Y2 direction. The silicon carbide single crystal substrate 306 and the silicon carbide epitaxial layer 307 are composed of, for example, hexagonal silicon carbide of polytype 4H. Silicon carbide single crystal substrate 306 contains n-type impurities such as nitrogen and has n-type. Silicon carbide substrate 310 is an example of a second semiconductor substrate, and main surface 310A is an example of a second main surface.

The main surface 310A is a surface in which (0001) is tilted in the off direction. For example, the off direction is [11-20]. For example, the main surface 310A is a surface in which (0001) is tilted in the off direction ([11-20]) at an off angle of 8° or less. The off angle may be, for example, 1° or more, or 2° or more. The off angle may be 6° or less, or 4° or less.

[11-20] is an orientation within (0001). However, since the main surface 310A is a surface inclined in the off-direction from (0001), [11-20] is not an orientation within the main surface 310A. The X1 direction corresponds to the orientation of [11-20] projected onto the main surface 310A, and the X2 direction corresponds to the orientation of [-1-120] projected onto the main surface 310A.

The first diode 300 has an active region 301 and a termination region 302 disposed around the active region 301.

In the active region 301, the silicon carbide epitaxial layer 307 mainly has an n-type region 311 and multiple p-type regions 315.

The n-type region 311 contains n-type impurities such as nitrogen and has n-type conductivity. The n-type region 311 constitutes the main surface 310B and constitutes a part of the main surface 310A. The n-type region 311 is an example of a first semiconductor region.

The multiple p-type regions 315 are provided on the main surface 310A. The p-type regions 315 constitute a part of the main surface 310A. The multiple p-type regions 315 extend parallel to the X1-X2 direction and are arranged side by side in the Y1-Y2 direction. The multiple p-type regions 315 extend along <11-20>. The p-type regions 315 contain p-type impurities such as aluminum and have a p-type conductivity. The p-type regions 315 have a lower end surface 315C, a first side end surface 315A, and a second side end surface 315B. The lower end surface 315C is approximately parallel to the XY plane. The first side end surface 315A and the second side end surface 315B are approximately parallel to the ZX plane. The first side end surface 315A is on the Y1 side of the second side end surface 315B. The bottom end surface 315C, the first side end surface 315A, and the second side end surface 315B are in contact with the n-type region 311. The p-type region 315 is an example of a second semiconductor region, and the X1-X2 direction is an example of the second direction. In this embodiment, the second angle between the <11-20> of the silicon carbide substrate 310 and the second direction is 10° or less.

The anode electrode 332 contacts the main surface 310A. The anode electrode 332 is electrically connected to the n-type region 311 and the p-type region 315.

The cathode electrode 333 contacts the main surface 310B. The cathode electrode 333 is electrically connected to the n-type region 311.

The first diode 300 includes a plurality of second unit cells 303 in the active region 301, which are units of the periodic pattern of the p-type region 315. The plurality of second unit cells 303 are aligned in the Y1-Y2 direction with the X1-X2 direction as the longitudinal direction. The plurality of second unit cells 303 extend along the <11-20>.

The termination region 302 is, for example, a region having a circular planar shape, and constitutes a part of the main surface 310A. The termination region 302 contains p-type impurities such as aluminum, and has a p-type conductivity.

A mark 319 specifying the crystal orientation of the silicon carbide substrate 310 may be provided on the portion of the main surface 310A exposed from the anode electrode 332. The mark 319 may directly indicate the crystal orientation. For example, the direction in which [11-20] faces may be indicated using Miller indices or a figure such as a triangle. The crystal orientation of the silicon carbide substrate 310 may also be indirectly indicated by the direction of the product number, etc.

In the first diode 300, when a voltage is applied between the anode electrode 332 and the cathode electrode 333, an electric field tends to concentrate in the first corner 316A where the bottom end surface 315C and the first side end surface 315A of the p-type region 315 intersect, and in the second corner 316B where the bottom end surface 315C and the second side end surface 315B intersect.

[Second transistor 400]
Next, a detailed description will be given of the second transistor 400. Fig. 8 is a diagram showing a unit cell of the second transistor 400, and Fig. 9 is a cross-sectional view showing the second transistor 400. Fig. 9 corresponds to a cross-sectional view taken along line IX-IX in Fig. 8.

The second transistor 400 mainly has a silicon carbide substrate 410, a gate electrode 431, a source electrode 432, and a drain electrode 433.

The silicon carbide substrate 410 includes a silicon carbide single crystal substrate 406 and a silicon carbide epitaxial layer 407 on the silicon carbide single crystal substrate 406. The silicon carbide substrate 410 has a main surface 410A and a main surface 410B opposite to the main surface 410A. The silicon carbide epitaxial layer 407 constitutes the main surface 410A, and the silicon carbide single crystal substrate 406 constitutes the main surface 410B. The shape of the silicon carbide substrate 410 is, for example, a rectangular parallelepiped. The main surface 410A is a surface perpendicular to the Z1-Z2 direction. <1-100> is a direction parallel to the Y1-Y2 direction. The silicon carbide single crystal substrate 406 and the silicon carbide epitaxial layer 407 are composed of, for example, hexagonal silicon carbide of polytype 4H. The silicon carbide single crystal substrate 406 contains n-type impurities such as nitrogen and has n-type. The silicon carbide substrate 410 is an example of a first semiconductor substrate, and the main surface 410A is an example of a first main surface.

The main surface 410A is a surface in which (0001) is tilted in the off direction. For example, the off direction is [11-20]. For example, the main surface 410A is a surface in which (0001) is tilted in the off direction ([11-20]) at an off angle of 8° or less. The off angle may be, for example, 1° or more, or 2° or more. The off angle may be 6° or less, or 4° or less.

[11-20] is an orientation within (0001). However, since the main surface 410A is a surface inclined in the off-direction from (0001), [11-20] is not an orientation within the main surface 410A. The X1 direction corresponds to the orientation of [11-20] projected onto the main surface 410A, and the X2 direction corresponds to the orientation of [-1-120] projected onto the main surface 410A.

The second transistor 400 has an active region 401 and a termination region 402 disposed around the active region 401.

In the active region 401, the silicon carbide epitaxial layer 207 mainly has a drift region 411, a body region 412, a source region 413, a contact region 414, and an electric field relaxation region 415.

The drift region 411 contains n-type impurities such as nitrogen and has n-type conductivity. The drift region 411 constitutes the main surface 410B. The body region 412 is in contact with the drift region 411. The body region 412 contains p-type impurities such as aluminum and has p-type conductivity. The source region 413 is provided on the body region 412 so as to be separated from the drift region 411 by the body region 412. The source region 413 contains n-type impurities such as nitrogen or phosphorus and has n-type conductivity. The source region 413 constitutes a part of the main surface 410A. The silicon carbide epitaxial layer 407 may have a buffer layer under the drift region 411.

A plurality of gate trenches 420 are provided in the main surface 410A. The plurality of gate trenches 420 extend parallel to the Y1-Y2 direction and are arranged side by side in the X1-X2 direction. The gate trench 420 is defined by a side surface 421 and a bottom surface 422. The bottom surface 422 is continuous with the side surface 421. The side surface 421 penetrates the source region 413 and the body region 412. The side surface 421 reaches the drift region 411. The bottom surface 422 is located in the drift region 411. The bottom surface 422 is approximately parallel to the main surface 410A. The side surface 421 is composed of the source region 413, the body region 412, and the drift region 411. The bottom surface 422 is composed of the drift region 411.

A gate insulating film 417 is formed in the gate trench 420, contacting the side surface 421 and the bottom surface 422. The gate insulating film 417 contacts the drift region 411 at the bottom surface 422. The gate insulating film 417 contacts the source region 413, the body region 412, and the drift region 411 at the side surface 421.

The gate electrode 431 is provided on the gate insulating film 417. The gate electrode 431 is made of, for example, polysilicon containing conductive impurities. The gate electrode 431 is disposed inside the gate trench 420. The gate electrode 431 faces the source region 413, the body region 412, and the drift region 411. The multiple gate electrodes 431 extend parallel to the Y1-Y2 direction and are disposed side by side in the X1-X2 direction. The multiple gate electrodes 431 extend along the <1-100> direction. The Y1-Y2 direction is an example of the first direction. In this embodiment, the first angle between the <1-100> direction of the silicon carbide substrate 410 and the first direction is 0°.

The contact region 414 is provided between adjacent gate trenches 420 in the X1-X2 direction, away from the side surface 421 of each gate trench 420, penetrating the source region 413, and in contact with the body region 412. The contact region 414 constitutes a part of the main surface 410A. The contact region 414 contains p-type impurities such as aluminum, and has a p-type conductivity.

The electric field relaxation region 415 is provided between adjacent gate trenches 420 in the X1-X2 direction, away from the side surface 421 of each gate trench 420, and extends from the body region 412 toward the main surface 410B. The electric field relaxation region 415 contains p-type impurities such as aluminum and has a p-type conductivity. The electric field relaxation region 415 has a lower end surface 415C, a first side end surface 415A, and a second side end surface 415B. The lower end surface 415C is approximately parallel to the XY plane. The first side end surface 415A and the second side end surface 415B are approximately parallel to the YZ plane. The first side end surface 415A is on the X1 side of the second side end surface 415B. The lower end surface 415C, the first side end surface 415A, and the second side end surface 415B are in contact with the drift region 411.

An interlayer insulating film 435 is provided to cover the gate trench 420 and the gate electrode 431. A contact hole 436 is formed in the interlayer insulating film 435 to expose a part of the source region 413 and the contact region 414.

The source electrode 432 is provided on the interlayer insulating film 435 and contacts the main surface 410A through a contact hole 436. The source electrode 432 is electrically connected to the source region 413 and the contact region 414. The interlayer insulating film 435 electrically insulates the gate electrode 431 and the source electrode 432.

The drain electrode 433 contacts the major surface 410B. The drain electrode 433 is electrically connected to the drift region 411.

The second transistor 400 includes a plurality of first unit cells 403 in the active region 401, which are units of the periodic pattern of the gate trenches 420. The plurality of first unit cells 403 are aligned in the X1-X2 direction with the Y1-Y2 direction as their longitudinal direction. The plurality of first unit cells 403 extend along the <1-100> direction.

The termination region 402 is, for example, a region having a circular planar shape, and constitutes a part of the main surface 410A. The termination region 402 contains p-type impurities such as aluminum, and has a p-type conductivity.

In the second transistor 400, when a voltage is applied between the source electrode 432 and the drain electrode 433, the electric field tends to concentrate in the electric field relaxation region 415 at the first corner 416A where the bottom end surface 415C intersects with the first side end surface 415A and at the second corner 416B where the bottom end surface 415C intersects with the second side end surface 415B.

[Second Diode 500]
Next, the second diode 500 will be described in detail. The second diode 500 is a Schottky barrier diode having a JBS structure. Fig. 10 is a diagram showing a unit cell of the second diode 500, and Figs. 11 and 12 are cross-sectional views showing the second diode 500. Fig. 11 corresponds to a cross-sectional view taken along line XI-XI in Fig. 10. Fig. 12 corresponds to a cross-sectional view taken along line XII-XII in Fig. 10.

The second diode 500 mainly has a silicon carbide substrate 510, an anode electrode 532, and a cathode electrode 533.

The silicon carbide substrate 510 includes a silicon carbide single crystal substrate 506 and a silicon carbide epitaxial layer 507 on the silicon carbide single crystal substrate 506. The silicon carbide substrate 510 has a main surface 510A and a main surface 510B opposite to the main surface 510A. The silicon carbide epitaxial layer 507 constitutes the main surface 510A, and the silicon carbide single crystal substrate 506 constitutes the main surface 510B. The shape of the silicon carbide substrate 510 is, for example, a rectangular parallelepiped. The main surface 510A is a surface perpendicular to the Z1-Z2 direction. <1-100> is a direction parallel to the Y1-Y2 direction. The silicon carbide single crystal substrate 506 and the silicon carbide epitaxial layer 507 are composed of, for example, hexagonal silicon carbide of polytype 4H. The silicon carbide single crystal substrate 506 contains n-type impurities such as nitrogen and has an n-type. The silicon carbide substrate 510 is an example of a second semiconductor substrate, and the main surface 510A is an example of a second main surface.

The main surface 510A is a surface in which (0001) is tilted in the off direction. For example, the off direction is [11-20]. For example, the main surface 510A is a surface in which (0001) is tilted in the off direction ([11-20]) at an off angle of 8° or less. The off angle may be, for example, 1° or more, or 2° or more. The off angle may be 6° or less, or 4° or less.

[11-20] is an orientation within (0001). However, since the main surface 510A is a surface inclined in the off-direction from (0001), [11-20] is not an orientation within the main surface 510A. The X1 direction corresponds to the orientation of [11-20] projected onto the main surface 510A, and the X2 direction corresponds to the orientation of [-1-120] projected onto the main surface 510A.

The second diode 500 has an active region 501 and a termination region 502 disposed around the active region 501.

In the active region 501, the silicon carbide epitaxial layer 507 mainly has an n-type region 511 and multiple p-type regions 515.

The n-type region 511 contains n-type impurities such as nitrogen and has n-type conductivity. The n-type region 511 constitutes the main surface 510B and constitutes a part of the main surface 510A. The n-type region 511 is an example of a first semiconductor region.

The multiple p-type regions 515 are provided on the main surface 510A. The p-type regions 515 constitute a part of the main surface 510A. The multiple p-type regions 515 extend parallel to the X1-X2 direction and are arranged side by side in the Y1-Y2 direction. The multiple p-type regions 515 extend along <11-20>. The p-type region 515 contains p-type impurities such as aluminum and has a p-type conductivity. The p-type region 515 has a lower end surface 515C, a first side end surface 515A, and a second side end surface 515B. The lower end surface 515C is approximately parallel to the XY plane. The first side end surface 515A and the second side end surface 515B are approximately parallel to the ZX plane. The first side end surface 515A is on the Y1 side of the second side end surface 515B. The bottom end surface 515C, the first side end surface 515A, and the second side end surface 515B are in contact with the n-type region 511. The p-type region 515 is an example of a second semiconductor region. The X1-X2 direction is an example of the second direction. In this embodiment, the second angle between the <11-20> of the silicon carbide substrate 510 and the second direction is 10° or less.

The anode electrode 532 contacts the main surface 510A. The anode electrode 532 is electrically connected to the n-type region 511 and the p-type region 515.

The cathode electrode 533 contacts the main surface 510B. The cathode electrode 533 is electrically connected to the n-type region 511.

The second diode 500 includes a plurality of second unit cells 503 in the active region 501, which are units of the periodic pattern of the p-type region 515. The plurality of second unit cells 503 are aligned in the Y1-Y2 direction with the X1-X2 direction as the longitudinal direction. The plurality of second unit cells 503 extend along the <11-20>.

The termination region 502 is, for example, a region having a circular planar shape, and constitutes a part of the main surface 510A. The termination region 502 contains p-type impurities such as aluminum, and has a p-type conductivity.

A mark 519 for specifying the crystal orientation of the silicon carbide substrate 510 may be provided on the portion of the main surface 510A exposed from the anode electrode 532. The mark 519 may directly indicate the crystal orientation. For example, the direction in which [11-20] faces may be indicated using Miller indices or a figure such as a triangle. The crystal orientation of the silicon carbide substrate 510 may also be indirectly indicated by the direction of the product number, etc.

In the second diode 500, when a voltage is applied between the anode electrode 532 and the cathode electrode 533, an electric field tends to concentrate in the first corner 516A where the lower end surface 515C and the first side end surface 515A of the p-type region 515 intersect, and in the second corner 516B where the lower end surface 515C and the second side end surface 515B intersect.

[Effects of the embodiment]
Here, the effects of the embodiment will be described.

In the upper arm 181, the first transistor 200 and the first diode 300 are connected in parallel to each other. In general, leakage current flows more easily through a Schottky junction than through a pn junction. For this reason, the breakdown voltage of the first diode 300 tends to be lower than the breakdown voltage of the first transistor 200.

In addition, silicon carbide generally has anisotropy in dielectric breakdown strength. For example, if the strength of the electric field is the same, when the electric field is applied to <11-20>, dielectric breakdown is more likely to occur in the former than when the electric field is applied to <1-100>. Therefore, in the first transistor 200, dielectric breakdown is more likely to occur at the pn junction interface between the drift region 211 and the first side end surface 215A and the second side end surface 215B of the electric field relaxation region 215. Furthermore, in the first transistor 200, since <11-20> is non-parallel to the main surface 210A, dielectric breakdown is more likely to occur at the pn junction interface between the drift region 211 and the second side end surface 215B than at the pn junction interface between the drift region 211 and the first side end surface 215A. On the other hand, in the first diode 300, dielectric breakdown is unlikely to occur at the pn junction interface between the n-type region 311 and the first side end surface 315A of the p-type region, and at the pn junction interface between the n-type region 311 and the second side end surface 315B.

As described above, in the first transistor 200, when a voltage is applied between the source electrode 232 and the drain electrode 233, an electric field tends to concentrate at the first corner 216A and the second corner 216B of the electric field relaxation region 215. In addition, the gate electrode 231 and the electric field relaxation region 215 extend parallel to the Y1-Y2 direction (<1-100>), and the first corner 216A and the second corner 216B also extend parallel to the Y1-Y2 direction (<1-100>).

Thus, in the first transistor 200, the first corner portion 216A and the second corner portion 216B are portions where electric field concentration is likely to occur and where dielectric breakdown is likely to occur. The first corner portion 216A and the second corner portion 216B are present over a wide range in the Y1-Y2 direction. Therefore, in the first transistor 200, dielectric breakdown is more likely to occur than in a case where the first corner portion 216A and the second corner portion 216B extend parallel to the X1-X2 direction.

In the first diode 300, when a voltage is applied between the anode electrode 332 and the cathode electrode 333, an electric field tends to concentrate at the first corner 316A and the second corner 316B of the p-type region 315. In addition, the p-type region 315 extends parallel to the X1-X2 direction (perpendicular to the <1-100> direction), and the first corner 316A and the second corner 316B also extend parallel to the X1-X2 direction (perpendicular to the <1-100> direction).

Thus, in the first diode 300, the first corner 316A and the second corner 316B are portions where electric field concentration is likely to occur, but are also portions where dielectric breakdown is unlikely to occur. The first corner 316A and the second corner 316B are present over a wide range in the X1-X2 direction. Therefore, in the first diode 300, dielectric breakdown is unlikely to occur compared to a case where the first corner 316A and the second corner 316B extend parallel to the Y1-Y2 direction.

Therefore, the first transistor 200 is more advantageous than the first diode 300 in terms of breakdown, but from the viewpoint of crystal orientation, the first diode 300 is more advantageous than the first transistor 200. Therefore, in this embodiment, the difference between the breakdown voltage of the first transistor 200 and the breakdown voltage of the first diode 300 can be reduced. Therefore, when the upper arm 181 transitions to an avalanche state due to the turning off of the first transistor 200, etc., breakdown occurs in both the first transistor 200 and the first diode 300, and avalanche current flows in both the first transistor 200 and the first diode 300. As a result, the concentration of the avalanche current in the first transistor 200 or the first diode 300 is suppressed, and the inductive load avalanche resistance of the upper arm 181 can be improved.

In the lower arm 182, the second transistor 400 and the second diode 500 are connected in parallel to each other. As with the upper arm 181, the breakdown voltage of the second diode 500 tends to be lower than the breakdown voltage of the second transistor 400.

In the second transistor 400, the first corner portion 416A and the second corner portion 416B are portions where electric field concentration is likely to occur and where dielectric breakdown is likely to occur, for the same reasons as in the first transistor 200. The first corner portion 416A and the second corner portion 416B are present over a wide range in the Y1-Y2 direction. Therefore, in the second transistor 400, dielectric breakdown is more likely to occur than in a case where the first corner portion 416A and the second corner portion 416B extend parallel to the X1-X2 direction.

In the second diode 500, for the same reason as in the first diode 300, the first corner 516A and the second corner 516B are portions where electric field concentration is likely to occur, but are less susceptible to dielectric breakdown. The first corner 516A and the second corner 516B are present over a wide range in the X1-X2 direction. Therefore, in the second diode 500, dielectric breakdown is less likely to occur compared to a case where the first corner 516A and the second corner 516B extend parallel to the Y1-Y2 direction.

Therefore, the second transistor 400 is more advantageous than the second diode 500 in terms of breakdown, but from the viewpoint of crystal orientation, the second diode 500 is more advantageous than the second transistor 400. Therefore, in this embodiment, the difference between the breakdown voltage of the second transistor 400 and the breakdown voltage of the second diode 500 can be reduced. Therefore, when the lower arm 182 transitions to an avalanche state due to the turning off of the second transistor 400, etc., breakdown occurs in both the second transistor 400 and the second diode 500, and avalanche current flows in both the second transistor 400 and the second diode 500. As a result, the concentration of the avalanche current in the second transistor 400 or the second diode 500 is suppressed, and the inductive load avalanche resistance of the lower arm 182 can be improved.

Since the inductive load avalanche resistance can be improved in both the upper arm 181 and the lower arm 182, the semiconductor module 100 can be used as a power module to improve the inductive load avalanche resistance of the power module.

Since silicon carbide substrates 210, 310, 410, and 510 are used, it is easy to obtain a high breakdown voltage. Also, as mentioned above, silicon carbide has anisotropy in its breakdown strength, but by making the structure according to the crystal orientation of the substrate, it is easy to improve the inductive load avalanche resistance.

When the markers 319, 519 are provided, the first diode 300 and the second diode 500 can be easily mounted on the insulating substrate 123, etc., while taking into account the crystal orientation of the silicon carbide substrates 310, 510. Note that the markers 319, 519 may be provided on the anode electrodes 332, 532 instead of the silicon carbide substrates 310, 510.

In the present disclosure, the first angle does not have to be 0°, but is preferably 10° or less, and more preferably 5° or less. If the first angle deviates too much from 0°, the channel mobility of electrons in the portion of the body region 212, 412 that functions as a channel may decrease.

The second angle does not have to be 0°, but is preferably 10° or less, and more preferably 5° or less. If the second angle deviates too much from 0°, there is a risk of a large leakage current.

Furthermore, when the first angle is 10° or less and the second angle is 10° or less, the inductive load avalanche resistance of the transistor and the inductive load avalanche resistance of the Schottky barrier diode can be brought closer to each other. This makes it easier to suppress the concentration of avalanche current in the transistor or diode and to improve the inductive load avalanche resistance.

Multiple first transistors 200 may be connected in parallel to one first diode 300, and multiple second transistors 400 may be connected in parallel to one second diode 500. In these cases, the current flowing through the upper arm 181 and the lower arm 182 can be increased, respectively.

Multiple first diodes 300 may be connected in parallel to one first transistor 200, and multiple second diodes 500 may be connected in parallel to one second transistor 400. In these cases, it becomes easier to return current in the upper arm 181 and the lower arm 182, respectively.

In addition, a plurality of first transistors 200 and a plurality of first diodes 300 may be connected in parallel to each other, and a plurality of second transistors 400 and a plurality of second diodes 500 may be connected in parallel to each other.

In the present disclosure, a gallium nitride substrate or a gallium oxide substrate may be used as the semiconductor substrate.

The difference in breakdown voltage between the first transistor 200 and the first diode 300 is preferably 100 V or less, more preferably 80 V or less, and even more preferably 60 V or less. The smaller the difference in breakdown voltage, the easier it is for avalanche current to flow through both the first transistor 200 and the first diode 300.

Similarly, the difference in breakdown voltage between the second transistor 400 and the second diode 500 is preferably 100 V or less, more preferably 80 V or less, and even more preferably 60 V or less. This is because the smaller the difference in breakdown voltage, the easier it is for avalanche current to flow through both the second transistor 400 and the second diode 500.

It is preferable that the breakdown voltage of the first diode 300 is higher than the breakdown voltage of the first transistor 200, and the breakdown voltage of the second diode 500 is higher than the breakdown voltage of the second transistor 400. In this case, it is easy to reduce the difference between the breakdown voltage of the first transistor 200 and the breakdown voltage of the first diode 300, and it is easy to reduce the difference between the breakdown voltage of the second transistor 400 and the breakdown voltage of the second diode 500.

The breakdown voltage of the first transistor 200, the breakdown voltage of the first diode 300, the breakdown voltage of the second transistor 400, and the breakdown voltage of the second diode 500 are preferably 600 V or more, more preferably 700 V or more, and even more preferably 800 V or more. The improved breakdown voltage allows for use in many applications.

In the present disclosure, the breakdown voltage refers to the voltage when a current with a current density of 10 mA/ ^cm2 flows in the reverse direction. FIG. 13 is a diagram showing breakdown characteristics. The horizontal axis of FIG. 13 indicates the reverse voltage, and the vertical axis indicates the current density of the reverse current. As shown in FIG. 13, in a transistor and a Schottky barrier diode, the reverse current increases as the reverse voltage increases, and when the reverse voltage exceeds a certain value, the reverse current increases rapidly. A current density of ¹⁰ mA/cm2 roughly corresponds to the voltage when the reverse current increases rapidly.

In the first transistor 200, a plurality of first unit cells having the Y1-Y2 direction as their longitudinal direction may be arranged in the Y1-Y2 direction. FIG. 14 is a diagram showing a unit cell of a modified example of the first transistor 200. In this modified example, a plurality of first unit cells 204 having the Y1-Y2 direction as their longitudinal direction are arranged in the Y1-Y2 direction. In addition, a plurality of groups each made up of a plurality of first unit cells 204 arranged in the Y1-Y2 direction are arranged in the X1-X2 direction.

Similarly, in the second transistor 400, multiple first unit cells having the Y1-Y2 direction as the longitudinal direction may be arranged in the Y1-Y2 direction.

In the first diode 300, a plurality of second unit cells having the X1-X2 direction as their longitudinal direction may be arranged in the X1-X2 direction. FIG. 15 is a diagram showing a unit cell of a modified example of the first diode 300. In this modified example, a plurality of second unit cells 304 having the X1-X2 direction as their longitudinal direction are arranged in the X1-X2 direction. In addition, a plurality of groups each made up of a plurality of second unit cells 304 arranged in the X1-X2 direction are arranged in the Y1-Y2 direction.

Similarly, in the second diode 500, multiple second unit cells with the X1-X2 direction as the longitudinal direction may be arranged in the X1-X2 direction.

Although the embodiments have been described in detail above, the invention is not limited to specific embodiments, and various modifications and variations are possible within the scope of the claims.

100: Semiconductor module 101: P terminal 102: N terminal 103: O terminal 111: First conductive pattern 112: Second conductive pattern 113: Third conductive pattern 114: Conductive layers 116, 117, 118, 119: Bonding material 121: Heat sink 122: Housing 123: Insulating substrate 161, 162, 171, 172: Bonding wire 181: Upper arm 182: Lower arm 191, 192: Side wall portion 193, 194: End wall portion 200: First transistor 201: Active region 202: Termination region 203, 204: First unit cell 206: Silicon carbide single crystal substrate 207: Silicon carbide epitaxial layer 210: Silicon carbide substrate (first semiconductor substrate)
210A: Main surface (first main surface)
210B: Main surface 211: Drift region 212: Body region 213: Source region 214: Contact region 215: Electric field relaxation region 215A: First side end surface 215B: Second side end surface 215C: Lower end surface 216A: First corner portion 216B: Second corner portion 217: Gate insulating film 220: Gate trench 221: Side surface 222: Bottom surface 231: Gate electrode 232: Source electrode 233: Drain electrode 235: Interlayer insulating film 236: Contact hole 300: First diode 301: Active region 302: Termination region 303, 304: Second unit cell 306: Silicon carbide single crystal substrate 307: Silicon carbide epitaxial layer 310: Silicon carbide substrate (second semiconductor substrate)
310A: Main surface (second main surface)
310B: Main surface 311: n-type region (first semiconductor region)
315: p-type region (second semiconductor region)
315A: first side end surface 315B: second side end surface 315C: bottom end surface 316A: first corner portion 316B: second corner portion 319: sign 332: anode electrode 333: cathode electrode 400: second transistor 401: active region 402: termination region 403: first unit cell 406: silicon carbide single crystal substrate 407: silicon carbide epitaxial layer 410: silicon carbide substrate (first semiconductor substrate)
410A: Main surface (first main surface)
410B: Main surface 411: Drift region 412: Body region 413: Source region 414: Contact region 415: Electric field relaxation region 415A: First side end surface 415B: Second side end surface 415C: Lower end surface 416A: First corner portion 416B: Second corner portion 417: Gate insulating film 420: Gate trench 421: Side surface 422: Bottom surface 431: Gate electrode 432: Source electrode 433: Drain electrode 435: Interlayer insulating film 436: Contact hole 500: Second diode 501: Active region 502: Termination region 503: Second unit cell 506: Silicon carbide single crystal substrate 507: Silicon carbide epitaxial layer 510: Silicon carbide substrate (second semiconductor substrate)
510A: Main surface (second main surface)
510B: Main surface 511: n-type region (first semiconductor region)
515: p-type region (second semiconductor region)
515A: first side end surface 515B: second side end surface 515C: bottom end surface 516A: first corner portion 516B: second corner portion 519: mark 532: anode electrode 533: cathode electrode

Claims (12)

A transistor;
a Schottky barrier diode connected in parallel to the transistor;
having
The transistor is
a first semiconductor substrate having a first major surface and a second major surface opposite the first major surface ;
A plurality of gate electrodes;
having
The first semiconductor substrate is
A drift region of a first conductivity type;
a body region of a second conductivity type provided on the drift region;
a source region of the first conductivity type provided on the body region so as to be separated from the drift region;
a plurality of electric field relaxation regions of the second conductivity type connected to the body region and at least a portion of which contacts the drift region;
having
a plurality of gate trenches are formed in the first main surface, the gate trenches having side surfaces penetrating through the source region and the body region to reach the drift region and bottom surfaces continuous with the side surfaces;
at least a portion of the gate electrode is within the gate trench;
the electric field relaxation region is located between adjacent ones of the gate trenches in a top view perpendicular to the first main surface,
the gate electrode and the electric field relief region extend in a first direction along a <1-100> direction of the first semiconductor substrate;
the electric field relaxation region has a first side end surface, a second side end surface opposite to the first side end surface, and a first lower end surface connected to the first side end surface and the second side end surface,
the first side end surface, the second side end surface, and the first lower end surface are in contact with the drift region;
The Schottky barrier diode is
a second semiconductor substrate having a third major surface;
The second semiconductor substrate is
a first semiconductor region of the first conductivity type constituting the third major surface;
a second semiconductor region of the second conductivity type formed on the third major surface;
having
The second semiconductor region extends in a second direction along a <11-20> direction of the second semiconductor substrate ,
the second semiconductor region has a third side end surface, a fourth side end surface opposite to the third side end surface, and a second lower end surface continuous with the third side end surface and the fourth side end surface,
The third end surface, the fourth end surface, and the second bottom end surface are in contact with the first semiconductor region . an angle between a <1-100> plane of the first semiconductor substrate and the first direction is a first angle;
an angle between a <11-20> plane of the second semiconductor substrate and the second direction is a second angle;
the first angle is less than or equal to 10 degrees;
The semiconductor device according to claim 1 , wherein the second angle is equal to or smaller than 10°. The transistor is provided in a plurality of layers.
3. The semiconductor device according to claim 1, wherein a plurality of the transistors are connected in parallel to the Schottky barrier diode. The Schottky barrier diode includes a plurality of the Schottky barrier diodes,
4. The semiconductor device according to claim 1, wherein a plurality of the Schottky barrier diodes are connected in parallel to the transistor. An upper arm;
A lower arm connected in series to the upper arm;
having
the upper arm includes a first combination of the transistor and the Schottky barrier diode;
The semiconductor device according to claim 1 , wherein the lower arm includes a second combination of the transistor and the Schottky barrier diode. The semiconductor device according to any one of claims 1 to 5, wherein the Schottky barrier diode has a mark that identifies the crystal orientation of the second semiconductor substrate. The semiconductor device according to any one of claims 1 to 6, wherein the first semiconductor substrate and the second semiconductor substrate are silicon carbide substrates. the transistor has a plurality of first unit cells whose longitudinal direction is the first direction,
8. The semiconductor device according to claim 1, wherein the Schottky barrier diode includes a plurality of second unit cells each having a longitudinal direction aligned in the second direction. The semiconductor device according to any one of claims 1 to 8, wherein the difference in breakdown voltage between the transistor and the Schottky barrier diode is 100 V or less. The semiconductor device according to any one of claims 1 to 9, wherein the breakdown voltage of the Schottky barrier diode is higher than the breakdown voltage of the transistor. The semiconductor device according to any one of claims 1 to 10, wherein the breakdown voltage of the transistor and the breakdown voltage of the Schottky barrier diode are 600 V or more. The semiconductor device according to claim 1 , wherein the electric field relief region extends from the body region toward the second main surface.

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