JP6473073B2 - Semiconductor device, power module, power conversion device, automobile and railway vehicle - Google Patents

Description

  The present invention relates to a semiconductor device, a power module, a power conversion device, an automobile and a railway vehicle, and more particularly to a structure of a power device using silicon carbide.

  Semiconductor power devices are required to have high breakdown voltage, low on-resistance, and low switching loss, but silicon (Si) power devices, which are currently mainstream, are approaching theoretical performance limits. Since silicon carbide (SiC) has a breakdown electric field strength that is about an order of magnitude higher than that of Si, the element resistance can be reduced by thinning the drift layer holding the breakdown voltage to about 1/10 and increasing the impurity concentration by about 100 times. Theoretically, it can be reduced by 3 digits or more. Further, since the band gap is about three times larger than that of Si, high-temperature operation is possible, and the SiC semiconductor element is expected to have performance exceeding that of the Si semiconductor element.

  Focusing on the above-mentioned advantages of SiC, research and development of Schottky Barrier Diodes (SBD) and the like as rectifier elements are underway. As switching elements, research and development of MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors), junction FETs, or IGBTs (Insulated Gate Bipolar Transistors) are being promoted.

  Non-Patent Document 1 describes that the forward voltage increases as the energization time elapses by energizing the SiC pn junction.

M. Skowronski and S. Ha, “Degradation of hexagonal silicon-carbide-based bipolar devices” Journal of Applied Physics 99, 011101 (2006)

  When BPD (basal plane dislocation) is formed in the epitaxial layer on the SiC substrate, a stacking fault is generated in the epitaxial layer when a current is passed through the region where the BPD is formed. The problem of increasing values arises.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the embodiments disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A semiconductor device according to a typical embodiment improves the distribution of pn current flowing in the peripheral region of an element when the pn junction of the SiC element is energized by the arrangement of the contact region and the silicide layer of the SiC element. is there.

  According to a typical embodiment, since an increase in resistance in the SiC element can be suppressed, the performance of the semiconductor device can be improved. As a result, the performance of a power module, a power converter, a car, and a railway vehicle can be improved.

It is a top view of the semiconductor device which is Embodiment 1 of this invention. It is sectional drawing in the AA line of FIG. 1, BB line, and CC line. It is a top view of the semiconductor device which is Embodiment 1 of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which is Embodiment 1 of this invention. FIG. 5 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 4. FIG. 6 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 5; FIG. 7 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 6; FIG. 8 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 7; FIG. 9 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 8. FIG. 10 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 9; FIG. 11 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 10; FIG. 12 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 11; FIG. 13 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 12; It is a top view of the modification of the semiconductor device which is Embodiment 1 of this invention. It is a top view of the semiconductor device which is Embodiment 2 of this invention. It is a circuit diagram of the power converter device of Embodiment 3 of this invention. It is the schematic which shows the structure of the electric vehicle of Embodiment 4 of this invention. It is a circuit diagram which shows the boost converter of Embodiment 4 of this invention. It is a circuit diagram which shows the converter and inverter in a rail vehicle which are Embodiment 5 of this invention. It is sectional drawing which shows the defect which arises in an epitaxial layer. It is the schematic of an epitaxial layer for demonstrating the defect which arises in an epitaxial layer. It is a top view of the semiconductor device which is a modification. It is a top view of the semiconductor device which is a modification.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. In the embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary. In the drawings describing the embodiments, hatching may be used even in plan views or perspective views for easy understanding of the configuration. Furthermore, in the drawings for describing the embodiments, hatching may be omitted in the cross-sectional view for easy understanding of the configuration.

The symbols “ ⁻ ” and “ ⁺ ” represent the relative concentrations of impurities of n-type or p-type conductivity. For example, in the case of n-type impurities, “n ⁻ ”, “n”, “ The impurity concentration increases in the order of “n ⁺ ”.

(Embodiment 1)
<Configuration of semiconductor device>
Hereinafter, the structure of the semiconductor chip which is the semiconductor device of the present embodiment will be described with reference to FIGS. FIG. 1 is a plan view of a semiconductor chip which is a semiconductor device of the present embodiment. 2 is a cross-sectional view taken along lines AA, BB, and CC in FIG. FIG. 3 is a plan view of a semiconductor chip which is a semiconductor device of the present embodiment, and shows a pad formation layer above the region where a plurality of elements shown in FIG. 1 are formed.

  As shown in FIG. 1, the semiconductor chip 60 has an epitaxial layer 64 including a drift layer formed on the surface side of the semiconductor substrate on the semiconductor substrate. In FIG. 1, the upper surface of the epitaxial layer 64 is mainly shown, and illustration of a gate insulating film, a gate electrode, an interlayer insulating film, a contact plug, a pad, and the like on the epitaxial layer 64 is omitted. FIG. 1 shows only the upper surface of the epitaxial layer 64 and various semiconductor regions and silicide layers formed on the upper surface.

  The left side of FIG. 2 is a cross-sectional view taken along the line AA of FIG. 1 and shows the structure of the termination region 1A at the end of the semiconductor chip 60 (see FIG. 1) including a SiC (silicon carbide) MOSFET. . That is, the cross-sectional view on the left side of FIG. 2 shows a cross section at the peripheral edge of the semiconductor chip 60.

  2 is a cross-sectional view taken along the line BB of FIG. 1 and shows the structure of the element region 1B at the center of the MOSFET formed on the SiC substrate, that is, the semiconductor chip 60 including the SiC MOSFET. ing. That is, the central cross-sectional view of FIG. 2 shows a cross section of a plurality of SiC MOSFETs (hereinafter sometimes simply referred to as MOSFETs) in the active region of the semiconductor chip 60.

  The right side of FIG. 2 is a cross-sectional view taken along the line CC of FIG. 1 and shows the structure of the termination region 1C at the end of the semiconductor chip 60 including a SiC (silicon carbide) MOSFET. That is, the right cross-sectional view of FIG. 2 shows a cross section at the peripheral edge of the semiconductor chip 60.

In FIG. 2, the termination region 1 </ b> A is a cross section along <11-20> that is the off direction of the semiconductor substrate (SiC substrate) that is an n ⁺ -type hexagonal semiconductor substrate. Termination region 1C is a cross section along the <1-100> direction orthogonal to <11-20> of the semiconductor substrate (SiC substrate) in plan view.

  As shown in FIG. 1, the SiC semiconductor device of the present embodiment has a semiconductor chip 60 on which a plurality of MOSFETs having a cell structure are mounted. FIG. 3 shows each pad used for supplying a potential to the gate electrode (not shown) and the source region 81 constituting these MOSFETs.

  As shown in FIG. 3, a gate pad 61 to which a gate voltage is applied from an external control circuit (not shown) is formed on the upper surface of the semiconductor chip 60. The gate pad 61 is electrically connected to a gate electrode 92 (see FIG. 2) that constitutes the MOSFET. The source regions of the plurality of MOSFETs formed on the semiconductor chip 60 are electrically connected in parallel and are connected to the source pad 62. That is, one source pad 62 is electrically connected to a plurality of source regions.

  In the element region (active region) 65 at the center of the semiconductor chip 60 shown in FIG. 1, a plurality of unit cells 70 serving as the minimum unit structure of the MOSFET are arranged. A gate voltage applied to the gate pad 61 shown in FIG. 3 is supplied to the gate electrode (not shown) of each unit cell 70 through the gate pad 61. Note that the position and number of the gate pads 61 shown in FIG. 3 or the shape of the source pads 62 can be various, but this does not affect the effect of the semiconductor device of the present embodiment.

  As shown in FIG. 1, the semiconductor chip 60 has a rectangular shape in plan view. That is, the outer periphery of the semiconductor chip 60 is composed of four sides including two parallel sides and two sides orthogonal to the two sides. In plan view, an element region 65 exists in the central portion of the semiconductor chip 60, and a peripheral region 66 and a termination region 67 exist so as to surround the periphery of the element region 65. That is, in plan view, the element region 65, the peripheral region 66, and the termination region 67 are sequentially arranged from the center of the upper surface of the epitaxial layer 64 on the semiconductor substrate constituting the semiconductor chip 60 toward the end of the upper surface of the epitaxial layer 64. Exists.

  Note that the termination region 67 is a region including the peripheral region 66. The peripheral region 66 is a power feeding unit for supplying a potential to a JTE (Junction Termination Extension) region 85 formed in the termination region 67.

  The peripheral region 66 shown in FIG. 1 constitutes the peripheral portion of the semiconductor chip 60 and has a rectangular annular structure in plan view. In other words, the peripheral region 66 has a frame-like configuration extending along each side of the rectangular semiconductor chip 60. In other words, the layout of the peripheral region 66 in plan view is composed of four sides including two sides parallel to each other and two sides orthogonal to the two sides. Further, since the termination region 67 is a terminal portion of the semiconductor chip 60, similarly to the peripheral region 66, the termination region 67 has an annular structure extending along each side of the rectangular semiconductor chip 60.

  A plurality of unit cells 70 including a well region 80, a source region 81, and a first contact region 82 are arranged in the element region 65, which is a region surrounded by the peripheral region 66. The unit cell 70 is a minimum unit structure of a MOSFET. On the upper surface of the epitaxial layer 64, the plurality of unit cells 70 are separated from each other. In plan view, in each unit cell 70, a source region 81 and a well region 80 are sequentially arranged around the first contact region 82.

  That is, in plan view, the source region 81 is formed so as to surround the outside of the first contact region 82, and the well region 80 is further formed so as to surround the outside of the source region 81. In plan view, the first contact region 82, the source region 81, and the well region 80 all have a rectangular structure.

  The first contact region 82 and the source region 81 are adjacent to each other, and a first silicide is formed on the upper surface of the first contact region 82 and the source region 81 so as to straddle the boundary between the first contact region 82 and the source region 81. A layer 95 is formed. The first silicide layer 95 has a rectangular structure in plan view, and is disposed so as to cover a part of the upper surface of the source region 81 and the upper surface of the first contact region 82. In order to make the configuration of the semiconductor device easy to understand, in FIG. 1, the region where the first silicide layer 95 is formed is hatched.

In plan view, the entire first contact region 82 is located inside the end of the first silicide layer 95. That is, the entire upper surface of the first contact region 82 overlaps the first silicide layer 95 in plan view, and the area of the first silicide layer 95 is larger than the area of the first contact region 82. The area of the first silicide layer 95 is, for example, 5 μm ² .

  Here, the unit cell 70 is shown as having a regular tetragonal structure in plan view, but the present invention is not limited to this, and the shape of the unit cell 70 may be, for example, a rectangle or a polygon. Although only five unit cells 70 are shown in FIG. 1, more unit cells 70 are actually arranged in the element region 65.

  Here, a plurality of unit cells 70 are arranged side by side in a first direction parallel to two parallel sides of the end portion of the semiconductor chip 60, and the columns thus provided are arranged in a direction orthogonal to the first direction. Several are arranged. Further, the unit cells 70 in the columns adjacent in the second direction are alternately arranged with a half cycle shift in the first direction. However, the present invention is not limited to this, and a plurality of unit cells 70 may be arranged at equal pitches in the vertical and horizontal directions. That is, the plurality of unit cells 70 may be arranged in a matrix.

  In the peripheral region 66, an annular second contact region 83 is formed on the upper surface of the epitaxial layer 64, and a second silicide layer 98 is formed on a part of the upper surface of the second contact region 83. That is, the other part of the upper surface of the second contact region 83 does not overlap the second silicide layer 98 in plan view. In the <11-20> direction, the upper surfaces of both ends of the second contact region 83 are exposed from the second silicide layer 98 on the end side and the center side of the semiconductor chip 60.

  In order to make the configuration of the semiconductor device easy to understand, in FIG. 1, the region where the second silicide layer 98 is formed is hatched. The peripheral region 66 here refers to a region overlapping the second contact region 83 in plan view. That is, the layout of the peripheral region 66 is defined by the formation region of the second contact region 83.

  In the semiconductor device of the present embodiment, the second contact region 83 is formed in an annular shape in the peripheral region 66 along each of the four outer peripheral sides of the semiconductor chip 60. On the other hand, the second silicide layer 98 does not have an annular structure, and is formed only immediately above a predetermined extension portion of the rectangular peripheral region 66.

That is, a semiconductor chip including the semiconductor substrate (SiC substrate) which is an n ⁺ -type hexagonal semiconductor substrate has two sides along the <11-20> direction and the <1-100> direction in plan view. It has a rectangular shape with two sides. The second contact region 83 formed in the peripheral region 66 includes a first extension portion E1 and a second extension portion E2 extending along the <11-20> direction, and a first extension portion E1 and a second extension portion E2. It has the 3rd extension part E3 and the 4th extension part E4 which were connected to each edge part of the extension part E2, and extended along the <1-100> direction. That is, the second contact region 83 has a structure in which the first extending portion E1, the second extending portion E2, the third extending portion E3, and the fourth extending portion E4 are connected in an annular shape.

  Among the portions constituting the second contact region 83, the first extending portion E1 and the second extending portion E2 have an angle between the <11-20> direction in the plan view and the <1-100> direction in the plan view. It is a part extending in a direction smaller than the angle between the two. The third extending portion E3 and the fourth extending portion E4 are portions extending in a direction in which the angle formed with the <11-20> direction in plan view is larger than the angle formed with the <1-100> direction in plan view. It is. In other words, the angles formed by the extending directions of the first extending portion E1 and the second extending portion E2 with the <11-20> direction are the respective angles of the third extending portion E3 and the fourth extending portion E4. The extending direction is smaller than the angle formed with the <11-20> direction.

  Here, the <11-20> direction is a direction from the left side to the right side in FIG. 1, and in the <11-20> direction, the third extending portion E3 and the fourth extending portion E4 are sequentially arranged. Has been. Further, the <1-100> direction referred to here is a direction from the lower side to the upper side in FIG. 1, and in the <1-100> direction, the first extending portion E1 and the second extending portion E2 are in order. Has been placed.

  The first extending portion E1 and the second extending portion E2 extending in the same direction are separated from each other with the element region 65 interposed therebetween. That is, the first extending portion E1 and the second extending portion E2 are in a positional relationship parallel to each other. The third extending portion E3 and the fourth extending portion E4 extending in the same direction are separated from each other with the element region 65 interposed therebetween. That is, the 3rd extension part E3 and the 4th extension part E4 have a mutually parallel positional relationship. One end portion in the longitudinal direction of the first extending portion E1 is connected to one end portion of the third extending portion E3, and the other end portion of the first extending portion E1 is connected to the fourth extending portion E4. One end of the second extending portion E2 in the longitudinal direction is connected to the other end of the third extending portion E3, and the other end of the second extending portion E2. Is connected to the other end of the fourth extending portion E4.

  Here, the second silicide layer 98 is formed only on the upper surfaces of the third extending portion E3 and the fourth extending portion E4, and the first extending portion E1 and the second extending portion. The second silicide layer 98 is not formed on each upper surface of E2. That is, the second silicide layer 98 is formed at only two locations in the peripheral region 66, and extends along the <1-100> direction immediately above the third extending portion E3 and the fourth extending portion E4. doing.

  Therefore, in plan view, the area of the second silicide layer 98 formed on the upper surface of the third extending portion E3 or the fourth extending portion E4 is the upper surface of the first extending portion E1 or the second extending portion E2. It is larger than the area of the second silicide layer 98 formed in the above. This is the same even if the second silicide layer 98 is formed on the upper surface of the first extending portion E1 or the second extending portion E2. Although not shown, a contact plug 97 as a connection portion is formed immediately above the region where the second silicide layer 98 is formed. The contact plug 97 is connected to the second silicide layer 98 via the second silicide layer 98. The contact region 83 is electrically connected.

  The termination region 1A in FIG. 2 is a region including the third extending portion E3, and the fourth extending portion E4 has the same structure as that of the termination region 1A. Further, the termination region 1C in FIG. 2 is a region including the first extension portion E1, and the second extension portion E2 has the same structure as the termination region 1C.

As shown in FIG. 2, the semiconductor chip 60 (see FIG. 1) of the present embodiment has a SiC substrate 63 that is an n ⁺ -type hexagonal semiconductor substrate. An epitaxial layer 64 including an n ⁻ type drift layer made of SiC having an impurity concentration lower than that of SiC substrate 63 is formed on SiC substrate 63. SiC substrate 63 and epitaxial layer 64 contain n-type impurities (for example, nitrogen (N) or phosphorus (P)). In the element region 1 </ b> B, a plurality of n-channel MOSFET cell structures are formed on the upper surface of the epitaxial layer 64.

Further, the drain wiring electrode 90 of the MOSFET is formed on the back surface side opposite to the main surface of the semiconductor chip 60 (see FIG. 1). Specifically, a drain region 84 that is an n ⁺ type semiconductor region is formed on the back surface of the SiC substrate 63, and the third silicide layer 100 is formed in contact with the bottom surface of the drain region 84. That is, the back surface of the SiC substrate 63 is covered with the third silicide layer 100. The bottom surface of the third silicide layer 100, that is, the surface opposite to the SiC substrate 63 side is covered with the drain wiring electrode 90.

In the element region 1B, a plurality of well regions 80, which are p-type semiconductor regions, are formed at a predetermined depth from the upper surface of the epitaxial layer 64. The well region 80 is a semiconductor region into which a p-type impurity (for example, aluminum (Al) or boron (B)) is introduced. In each well region 80, a source region 81 that is an n ⁺ type semiconductor region is formed at a predetermined depth from the upper surface of the epitaxial layer 64. The source region 81 is a semiconductor region into which an n-type impurity (for example, nitrogen (N) or phosphorus (P)) is introduced.

In each well region 80, a first contact region 82, which is a p ⁺ type semiconductor region, is formed at a predetermined depth from the upper surface of the epitaxial layer 64. The first contact region 82 is a region provided for fixing the potential of the well region and has substantially the same depth as the source region 81. The first contact region 82 is a semiconductor region into which a p-type impurity (for example, aluminum (Al) or boron (B)) is introduced. The first contact region 82 is disposed so as to be sandwiched from both sides by the adjacent source region 81. The bottom of the first contact region 82 and the bottom and side surfaces of the source region 81 are covered with the well region 80.

  A plurality of unit cells 70 including a well region 80, a source region 81, and a first contact region 82 are formed on the upper surface of the epitaxial layer 64, and the unit cells 70 are separated from each other. A gate electrode 92 is formed on the epitaxial layer 64 between adjacent unit cells 70 via a gate insulating film 91, and the upper surface of the end of the gate insulating film 91, the side walls and the upper surface of the gate electrode 92 are The interlayer insulating film 93 is covered. In the opening 68 between the interlayer insulating films 93 that cover the gate electrodes 92, the first contact region 82 and the source region 81 are not covered with the gate insulating film 91, the gate electrode 92, and the interlayer insulating film 93. That is, the gate insulating film 91, the gate electrode 92, and the interlayer insulating film 93 have the opening 68 reaching the upper surface of the unit cell 70, and the first contact region 82 and the source region 81 are exposed at the bottom of the opening 68. doing.

  A first silicide layer 95 is formed on each surface of the opening 68 of the interlayer insulating film 93 in the element region 1B, that is, a part of the source region 81 exposed at the bottom of the contact hole and the first contact region 82. ing. A contact plug 94, which is a connection portion, is embedded in a part of the source region 81 and the opening 68 on the first silicide layer 95 in contact with the first contact region 82. Each of the plurality of contact plugs 94 embedded in the plurality of openings 68 is integrated with a source wiring electrode 96 formed in the interlayer insulating film 93. The source wiring electrode 96 is electrically connected to the source pad 62 (see FIG. 3). Here, the upper surface of the source wiring electrode 96 exposed from the passivation film 99 described later constitutes the source pad 62.

  A part of the source region 81 and the first contact region 82 are electrically connected to the contact plug 94 through the first silicide layer 95 so as to have ohmic properties. Therefore, a part of the source region 81 and the first contact region 82 are connected to the source pad 62 via the first silicide layer 95, the contact plug 94, and the source wiring electrode 96. Similarly, a contact plug is connected to the gate electrode 92 in a region not shown, and the gate electrode 92 is electrically connected to the gate pad 61 (see FIG. 3) via the contact plug and the gate wiring electrode. .

  In the termination regions 1 </ b> A and 1 </ b> C, the interlayer insulating film 93 and the source wiring electrode 96 are covered with a passivation film 99. On the other hand, the upper surface of the source wiring electrode 96 in the element region 1B is exposed from the passivation film 99. In a part of the element region 1B and not shown, the upper surface of the gate wiring electrode connected to the gate electrode 92 is exposed from the passivation film 99, and the gate pad 61 (see FIG. 3). ).

  The MOSFET formed on the semiconductor chip of this embodiment has at least a gate electrode 92, a source region 81, and a drain region 84. When the MOSFET is operated, a predetermined voltage is applied to the gate electrode 92 to turn on the MOSFET, so that a current flows from a high potential drain to a low potential source. The channel region of the MOSFET is formed in the upper portion of the well region 80 which is a p-type semiconductor region. That is, the current for driving the MOSFET flows from the drain wiring electrode 90, passes through the region in the epitaxial layer 64 near the gate insulating film 91, and in the well region 80 near the upper surface of the epitaxial layer 64. Thus, it flows to the source region 81 through the region directly under the gate electrode 92.

In the termination regions 1A and 1C, a second contact region 83 which is a p ⁺ type semiconductor region is formed at a predetermined depth from the upper surface of the epitaxial layer 64. In the termination regions 1A and 1C, a JTE region 85, which is a p-type semiconductor region, is formed at a predetermined depth from the upper surface of the epitaxial layer 64. The second contact region 83 and the JTE region 85 are semiconductor regions into which a p-type impurity (for example, aluminum (Al) or boron (B)) is introduced. The JTE region 85 is formed deeper than the second contact region 83, and the second contact region 83 is formed in the JTE region 85. That is, the bottom surface and the side wall of the second contact region 83 are covered with the JTE region 85.

  The second contact region 83 is a region formed for fixing the potential of the termination region, and is a region for supplying a potential to the JTE region 85. That is, by applying a potential to the JTE region 85 via the second contact region 83, the electric field concentration in the termination region when applying a reverse voltage can be alleviated and the breakdown voltage of the semiconductor chip can be kept high. Here, a description will be given of a structure in which a JTE region is formed as a termination structure of a semiconductor chip. However, in order to reduce the electric field of the semiconductor chip, the termination structure includes, for example, a p-type semiconductor region that annularly surrounds an element region in plan view. A plurality of FLR (Field Limiting Ring) structures may be used.

  An interlayer insulating film 93 is formed on the epitaxial layers 64 in the termination regions 1A and 1C with an insulating film 89 interposed therebetween. In the termination region 1A, the interlayer insulating film 93 and the insulating film 89 have an opening 69. At the bottom of the opening 69, the upper surface of the second contact region 83 is exposed from the interlayer insulating film 93 and the insulating film 89. . On the other hand, in the termination region 1C, the interlayer insulating film 93 and the insulating film 89 do not have openings, and the upper surfaces of the second contact regions 83 are all covered with the interlayer insulating film 93 and the insulating film 89.

In both cases where the impurity concentration of the second contact region 83 and the impurity concentration of the first contact region 82 are not equal or equal, the impurity concentration of each region is, for example, 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²⁰ cm ⁻³ .

  In the termination region 1 </ b> A, a contact plug 97 as a connection portion is embedded in the opening 69 of the interlayer insulating film 93, and a second silicide layer 98 is formed on the bottom surface of the opening 69. That is, at the bottom of the opening 69, the upper surface of the second contact region 83 and the upper surface of the JTE region 85 are in contact with the contact plug 97 through the second silicide layer 98. The second contact region 83 is electrically connected to the contact plug 97 through the second silicide layer 98 so as to have an ohmic property.

  In contrast, the second silicide layer 98 is not formed on the upper surface of the second contact region 83 in the termination region 1 </ b> C, and the contact plug 97 is not formed immediately above the second contact region 83. On the second contact region 83 in the termination region 1C, a source wiring electrode 96 is formed through an insulating film 89 and an interlayer insulating film 93. In the termination region 1C, the source wiring electrode 96 and the second contact region 83 are not ohmically connected.

  The contact plug 97 is integrated with the source wiring electrode 96 on the interlayer insulating film 93. Further, the contact plugs 94 and 97, the source wiring electrode 96, and the source wiring electrode 96 in the termination region 1C are integrated, and are made of one metal film. Therefore, the second contact region 83 is electrically connected to the source pad 62 (see FIG. 3) via the second silicide layer 98, the contact plug 97, and the source wiring electrode 96.

In the present embodiment, when a potential is supplied to the first contact region 82, a pn current flows through the pn junction of the MOSFET built-in diode (built-in pn diode). In addition, when a potential is supplied to the second contact region 83, a pn current flows through the pn junction of the built-in diode in the termination region 1A. The MOSFET built-in diode here refers to a pn junction between the p-type well region 80 connected to the p ⁺ -type first contact region 82 and the n ⁻ -type epitaxial layer 64, for example. Further, the built-in diode in the termination region 1 ^</ b ^{> A} here is, for example, a pn junction between the p-type JTE region 85 connected to the p ⁺ -type second contact region 83 and the n ⁻ -type epitaxial layer 64. Refers to the part. In the present application, a current flowing through a pn connection in the substrate including the epitaxial layer 64 is referred to as a pn current.

The pn junction portion between the p-type JTE region 85 connected to the p ⁺ -type second contact region 83 in the termination region 1C and the n ⁻ -type epitaxial layer 64 constitutes a built-in diode in the termination region 1C. To do. However, the second silicide layer 98 is not formed on the upper surface of the second contact region 83 in the termination region 1C, and the source wiring electrode 96 and the second contact region 83 are not ohmically connected. Even if the MOSFET in the element region is operated by supplying a potential to the contact region 82 and the second contact region 83, no pn current flows through the built-in diode in the termination region 1C.

<Method for Manufacturing Semiconductor Device>
A method for manufacturing a semiconductor device in this embodiment will be described in the order of steps with reference to FIGS. 4 to 13 are cross-sectional views illustrating the manufacturing process of the semiconductor device of the present embodiment. 4 to 13, the cross section of the termination region 1A, which is the peripheral region of the semiconductor device, is shown on the left side of the figure, the cross section of the element region 1B in which the MOSFET is formed is shown in the center of the figure, The cross section of termination area | region 1C which is a peripheral area | region is shown. The cross sections of the termination regions 1A and 1C and the element region 1B shown in FIGS. 4 to 13 are cross sections at the same positions as described with reference to FIGS.

First, as shown in FIG. 4, an n ⁺ type SiC substrate 63 is prepared. An n-type impurity is introduced into SiC substrate 63 at a relatively high concentration. The n-type impurity is, for example, nitrogen (N), and the impurity concentration of the n-type impurity is, for example, 1 × 10 ¹⁷ to 1 × 10 ¹⁹ cm ⁻³ . The main surface of the SiC substrate 63 is, for example, a {0001} plane.

Next, an epitaxial layer 64 that is an n ^- type semiconductor layer of SiC is formed on the main surface of SiC substrate 63 by epitaxial growth. The epitaxial layer 64 is doped with an n-type impurity lower than the impurity concentration of the SiC substrate 63. The impurity concentration of the epitaxial layer 64 depends on the rated breakdown voltage of the element and is, for example, 1 × 10 ¹⁴ to 1 × 10 ¹⁷ cm ⁻³ . Moreover, the thickness of the epitaxial layer 64 is 3-80 micrometers, for example. A specific thickness of the epitaxial layer 64 is, for example, 30 μm.

Next, as shown in FIG. 5, a mask 10 is formed on the upper surface of the epitaxial layer 64. The mask 10 is a film that exposes a part of the upper surface of each epitaxial layer 64 in the termination regions 1A, 1C. The thickness of the mask 10 is, for example, about 0.5 to 5.0 μm. As a material of the mask 10, for example, SiO ₂ (silicon oxide) or a photoresist is used.

Next, a p-type impurity (for example, aluminum (Al)) is ion-implanted into the epitaxial layer 64 having the mask 10 formed thereon. Thereby, a JTE region 85 which is a p-type semiconductor region is formed on the upper surface of each epitaxial layer 64 of the termination regions 1A and 1C. The depth of the JTE region 85 from the upper surface of the epitaxial layer 64 is, for example, about 0.5 to 2.0 μm. Further, the impurity concentration of the JTE region 85 is, for example, 1 × 10 ^{16 to} 5 × 10 ¹⁹ cm ⁻³ .

Next, as shown in FIG. 6, after removing the mask 10, the mask 11 is formed on the upper surface of the epitaxial layer 64. The mask 11 is a film exposing a plurality of locations on the upper surface of the epitaxial layer 64 in the element region 1B. The thickness of the mask 11 is, for example, about 1.0 to 5.0 μm. For example, SiO ₂ or photoresist is used as the material of the mask 11.

Next, a p-type impurity (for example, aluminum (Al)) is ion-implanted into the epitaxial layer 64 on which the mask 11 is formed. Thereby, a plurality of well regions 80 which are p-type semiconductor regions are formed on the upper surface of the epitaxial layer 64 in the element region 1B. The depth of the well region 80 from the upper surface of the epitaxial layer 64 is, for example, about 0.5 to 2.0 μm. The impurity concentration of the well region 80 is, for example, 1 × 10 ¹⁶ to 1 × 10 ¹⁹ cm ⁻³ .

Next, as shown in FIG. 7, after removing the mask 11, the mask 12 is formed on the upper surface of the epitaxial layer 64. The thickness of the mask 12 is, for example, about 0.5 to 2.0 μm. For example, SiO ₂ or a photoresist is used as the material of the mask 12.

Next, n-type impurities (for example, nitrogen (N)) are ion-implanted into the epitaxial layer 64 having the mask 12 formed thereon. Thereby, a plurality of source regions 81 which are n ⁺ type semiconductor regions are formed on the upper surface of the epitaxial layer 64 in the element region 1B. Each source region 81 is formed in the center of the well region 80 in plan view. The depth of each source region 81 from the upper surface of the epitaxial layer 64 is, for example, about 0.05 to 1.0 μm. Further, the impurity concentration of the source region 81 is, for example, 1 × 10 ¹⁸ to 1 × 10 ²⁰ cm ⁻³ .

Next, as shown in FIG. 8, after removing the mask 12, the mask 13 is formed on the upper surface of the epitaxial layer 64. The thickness of the mask 13 is, for example, about 0.5 to 2.0 μm. For example, SiO ₂ or photoresist is used as the material of the mask 13.

Next, a p-type impurity (for example, aluminum (Al)) is ion-implanted into the epitaxial layer 64 having the mask 13 formed thereon. Thereby, the first contact region 82 is a semiconductor region of p ⁺ -type plurality formed on the upper surface of the epitaxial layer 64 in the element region 1B, termination region 1A, the upper surface of the epitaxial layer 64 of 1C in p ⁺ -type semiconductor region A certain second contact region 83 is formed. Each first contact region 82 is formed at the center of each source region 81 in plan view. The second contact region 83 is formed on the upper surface of the JTE region 85. In plan view, the second contact region 83 has a rectangular annular structure and is formed so as to surround the element region 1B.

The depth of the first contact region 82 and the second contact region 83 from the upper surface of the epitaxial layer 64 is, for example, about 0.05 to 2.0 μm. Further, the impurity concentration of the first contact region 82 and the second contact region 83 is, for example, 1 × 10 ¹⁸ to 1 × 10 ²⁰ cm ⁻³ . Here, the area of the second contact region 83 in plan view is larger than the area of each first contact region 82.

Next, as shown in FIG. 9, after removing the mask 13, a mask 14 serving as a protective film is formed on the upper surface of the epitaxial layer 64. Thereafter, n-type impurities (for example, nitrogen (N)) are ion-implanted into the back surface of the SiC substrate 63. Thereby, a drain region 84 which is an n ⁺ type semiconductor region is formed on the back surface of the SiC substrate 63. The depth of the drain region 84 from the back surface of the SiC substrate 63 is, for example, about 0.05 to 2.0 μm. The impurity concentration of the drain region 84 is 1 × 10 ¹⁹ to 1 × 10 ²¹ cm ⁻³ .

  Next, although not shown in the figure, the carbon (C) film is removed by using, for example, a plasma CVD (Chemical Vapor Deposition) method so that all masks are removed and the upper surface of the epitaxial layer 64 and the back surface of the SiC substrate 63 are in contact with each other. To deposit. The thickness of the carbon (C) film is, for example, about 0.03 to 0.05 μm. As described above, the upper surface of the SiC epitaxial layer 64 and the back surface of the SiC substrate 63 are covered with the carbon (C) film, and then heat treatment is performed at a temperature of 1500 ° C. or more for about 2 to 3 minutes. Thereby, each impurity ion-implanted into the upper surface of SiC epitaxial layer 64 and the back surface of SiC substrate 63 is activated. Thereafter, the carbon (C) film is removed by, for example, plasma processing.

  Next, as shown in FIG. 10, an insulating film 89 and an n-type polycrystalline Si film are sequentially formed on the upper surface of the epitaxial layer 64, and then a mask 15 is formed on the polycrystalline Si film. The insulating film 89 and the polycrystalline Si film are formed by, for example, a CVD method. The mask 15 is formed between adjacent first contact regions 82 on the upper surface of the epitaxial layer 64. Subsequently, the polycrystalline Si film is processed by a dry etching method using the mask 15 to form a gate electrode 92 made of the polycrystalline Si film. The thickness of the insulating film 89 is, for example, about 0.05 to 0.15 μm. The thickness of the gate electrode 92 is, for example, about 0.2 to 0.5 μm.

  Next, as shown in FIG. 11, after removing the mask 15, an interlayer insulating film 93 is formed on the upper surface of the epitaxial layer 64 by, for example, a plasma CVD method so as to cover the gate electrode 92 and the insulating film 89. Thereafter, the upper surface of the epitaxial layer 64 is exposed by processing the interlayer insulating film 93 and the insulating film 89 by a dry etching method using the mask 16.

  Thereby, the gate insulating film 91 made of the insulating film 89 is formed immediately below the gate electrode 92 and the interlayer insulating film 93 in the element region 1B. Further, by the etching process, an opening 68 is formed in the interlayer insulating film 93 in the element region 1B so that a part of the source region 81 and the upper surface of each of the first contact regions 82 are exposed in the interlayer insulating film 93. An opening 69 is formed in the interlayer insulating film 93 in the region 1A so that a part of the upper surface of the second contact region 83 is exposed. No opening is formed in the termination region 1 </ b> C, and the second contact region 83 is not exposed from the interlayer insulating film 93.

  Thus, a plurality of unit cells 70 which are the minimum unit structure of the MOSFET are formed. Each of the plurality of unit cells 70 has a well region 80, a source region 81, and a first contact region 82 that are adjacent to each other, and a gate electrode 92 that is formed immediately above the well region 80 via a gate insulating film 91. doing.

  Next, as shown in FIG. 12, after the mask 16 is removed, a first silicide layer 95 and a second silicide layer are formed on the bottom of the opening 68 in the element region 1B and the bottom of the opening 69 in the termination region 1A, respectively. Layer 98 is formed.

  When forming the first silicide layer 95 and the second silicide layer 98, first, a first metal (for example, nickel (Ni)) film is deposited by, eg, sputtering so as to cover the exposed epitaxial layer 64. To do. The thickness of the first metal film is, for example, about 0.05 μm. Subsequently, by performing a silicidation heat treatment at 600 to 1000 ° C., the first metal film and the epitaxial layer 64 are reacted at the bottom surface of the opening 68 in the element region 1B and the bottom surface of the opening 69 in the termination region 1A. For example, a first silicide layer 95 and a second silicide layer 98 made of nickel silicide (NiSi) are formed.

  Here, since the upper surface of the second contact region 83 in the termination region 1 </ b> C is not exposed, the second silicide layer 98 is not formed on the upper surface of the second contact region 83.

  Next, as shown in FIG. 13, the inside of each of the opening 68 reaching the first silicide layer 95, the opening 69 reaching the second silicide layer 98, and the opening (not shown) reaching the gate electrode 92 is embedded. As described above, a second metal (for example, titanium (Ti)) film, a titanium nitride (TiN) film, and an aluminum (Al) film are sequentially stacked on the interlayer insulating film 93. The thickness of the aluminum (Al) film is preferably 1.0 μm or more, for example. Subsequently, by processing the laminated film made of the second metal film, the titanium nitride film and the aluminum film, contact plugs 94 and 97 made of the laminated film, source wiring electrodes 96 and gate wiring electrodes (not shown). ).

  The source wiring electrode 96 or the gate wiring electrode is made of the laminated film on the interlayer insulating film 93, the contact plug 94 is made of the laminated film in the opening 68, and the contact plug 97 is made of the laminated film in the opening 69. Consists of. The source wiring electrode 96 is electrically connected to the first contact region 82 and the second contact region 83 through the first silicide layer 95 and the second silicide layer 98 so as to have ohmic properties. A gate wiring electrode (not shown) is electrically connected to the gate electrode 92.

Next, an insulating film made of a SiO ₂ film or a polyimide film is formed so as to cover the gate wiring electrode and the source wiring electrode 96, and the passivation film 99 is formed by processing the insulating film. Here, the passivation film 99 covers the termination regions 1A and 1C and opens in the element region 1B.

  Next, a third metal film is formed on the back surface of the SiC substrate 63 by, for example, a sputtering method and subjected to a laser silicidation heat treatment, whereby the third metal film and the SiC substrate 63 are reacted to form a third silicide layer. 100 is formed. The third silicide layer 100 is in contact with the lower surface of the drain region 84. The thickness of the third metal film is, for example, about 0.1 μm. Subsequently, a drain wiring electrode 90 is formed so as to cover the bottom surface of the third silicide layer 100. The drain wiring electrode 90 is composed of a 0.5 to 1 μm laminated film formed by laminating a titanium (Ti) film, a nickel (Ni) film, and a gold (Au) film in this order from the third silicide layer 100 side. .

  Thereafter, the SiC substrate 63 is cut into pieces by a dicing process, thereby obtaining a plurality of semiconductor chips. Thus, the semiconductor chip 60 of the present embodiment including the SiC MOSFET shown in FIGS. 1, 2, and 3 is completed.

<Effects of the present embodiment>
Next, the effect of the semiconductor device according to the first embodiment will be described with reference to FIGS.

  FIG. 20 is a cross-sectional view showing various defects generated in the epitaxial layer. FIG. 20 shows a cross section of the semiconductor substrate and the epitaxial layer thereon. In FIG. 20, hatching is omitted for easy understanding of the structure of defects generated in the substrate or the like.

  FIG. 21 is a schematic view of an epitaxial layer on a semiconductor substrate for explaining Shockley type stacking faults occurring in the epitaxial layer on the semiconductor substrate. The right side of FIG. 21 shows a plan view of Shockley type stacking faults occurring in the epitaxial layer. A schematic perspective view of the SiC semiconductor substrate (wafer) is shown on the left side of FIG. 21, and a rectangular portion of a part of the semiconductor substrate is shown in the center. An ellipse shown on the left side of FIG. 21 is an epitaxial layer, and a semiconductor substrate thereunder is not shown. 22 and 23 are plan views of a semiconductor device shown as a comparative example.

Line defects present in 4H-SiC crystals used for device fabrication include basal plane dislocation (BPD), which is the nucleus of stacking fault growth, and threading screw dislocation (TSD: Threading). There are Screw Dislocation) and Threading Edge Dislocation (TED). Here, the state of propagation in the epitaxial growth of the line defects contained in the substrate is shown in FIG. In FIG. 20, BPD is indicated by a solid line, TSD is indicated by a broken line, and TED is indicated by a dotted line. FIG. 20 shows a p ⁺ type semiconductor region 88 formed on the upper surface of the epitaxial layer 64.

  There are two types of BPDs. That is, there are BPD originally present in the substrate and BPD produced by a semiconductor device manufacturing process (p-type impurity implantation process). As shown by the solid line in FIG. 20, many BPDs originally present in the substrate exist in the SiC substrate 63, and most of them are converted to TED and propagate to the epitaxial layer 64 during epitaxial growth. A part of the BPD can propagate into the epitaxial layer 64.

  In a semiconductor device in which an epitaxial layer is formed on a SiC semiconductor substrate, as a method for epitaxial growth of SiC, the crystal axis is several degrees (for example, 4 degrees or 8 degrees) from the {0001} basal plane in the <11-20> direction. This is because step flow growth is used on an inclined surface. Therefore, the BPD that exists in the SiC crystal and becomes the nucleus of the stacking fault growth propagates in an oblique direction inclined several degrees from the main surface of the SiC substrate 63 in the epitaxially grown epitaxial layer (drift layer).

  TED and TSD are dislocations propagating in a direction perpendicular to the main surface of SiC substrate 63, and hardly cause an increase in element resistance and forward voltage of the semiconductor device. Further, TED and TSD are dislocations that do not expand to stacking faults. Therefore, TED and TSD have little adverse effect on the characteristics of the semiconductor device as compared with BPD.

Of the two types of BPDs, BPD produced by a semiconductor device manufacturing process (p-type impurity implantation process) occurs, for example, in the following cases. That is, as shown in FIG. 20, p-type impurities are implanted into the upper surface of the epitaxial layer 64, and a p ⁺ -type semiconductor region 88 having a high impurity concentration, for example, about 1 × 10 ²⁰ cm ⁻³ is formed on the upper surface of the epitaxial layer 64. In this case, BPD is generated at the end of the p ⁺ type semiconductor region 88 due to the implantation step. The BPD is formed in the vicinity of the interface between the p ⁺ type semiconductor region 88 that is a region where p-type impurities are implanted and the epitaxial layer 64 where no p-type impurities are implanted.

The BPD is likely to occur when a p-type impurity is implanted into the substrate surface and the impurity concentration is high. On the other hand, when the concentration of the implanted p-type impurity is, for example, less than 1 × 10 ¹⁸ cm ⁻³ , BPD hardly occurs. BPD is likely to occur when the area of the region into which the p-type impurity is implanted is large. Therefore, for example, when a high-concentration and large-area p ⁺ -type semiconductor region 88 is formed as a contact region for power supply in the termination region of a semiconductor chip, BPD is likely to occur.

Next, the shape of stacking faults grown in the BPD and epitaxial layer 64 created in the semiconductor device manufacturing process (p-type impurity implantation process) will be described with reference to FIG. As shown in FIG. 21, the BPD formed in the vicinity of the interface between the p ⁺ type semiconductor region 88 and the epitaxial layer 64 is generated from the vertex N1 on the epitaxial layer surface side as a base point, and the Shockley partial dislocation having the Si core There are two types: SIT and Shockley-type partial dislocation CT having a C core. That is, the Shockley partial dislocation SIT having the Si core and the Shockley partial dislocation CT having the C core are both BPDs.

  Here, when electrons and holes injected by energization of the pn junction in the epitaxial layer 64 are recombined in the BPD, the released energy causes the Shockley type partial dislocation SIT having the Si core to be converted into the Shockley type. Move in the direction of spreading stacking faults. A plane defect called a Shockley type stacking fault occurs at a location between the two Shockley type partial dislocations.

  As shown in FIG. 21, Shockley type stacking fault SD penetrates the drift layer from the upper surface of epitaxial layer 64 and reaches the bottom surface of epitaxial layer 64, that is, the surface of epitaxial layer 64 on the SiC substrate side. Here, in order to make the figure easy to understand, the Shockley type stacking fault SD which is a surface defect is hatched.

  As shown in the plan view on the right side of FIG. 21, the angle formed between the Shockley partial dislocation SIT having the Si core and the Shockley partial dislocation CT having the C core is 120 degrees in plan view. The Shockley-type stacking fault SD is formed in the shape of a solid isosceles triangle shown in the plan view on the right side of FIG. Here, the case where the base point of the BPD is the vertex N1 has been described, but the vertex N2 can also be a base point for occurrence of stacking faults.

When a built-in diode is formed in the termination region, when a forward current (pn current) is passed through the built-in diode, for example, the apex N1 or N2 at the end of the p ⁺ type semiconductor region 88 (see FIG. 20) is used as a base point. Holes recombine in the generated BPD, and the recombination energy causes a shift in crystals in the substrate. Due to this crystal shift, a Shockley-type stacking fault SD is generated in the substrate.

  The BPD and the Shockley type stacking fault SD generated on the upper surface of the epitaxial layer 64 in this way grow in an oblique direction from the upper surface of the epitaxial layer 64 toward the substrate side by continuing to pass a pn current. The angle at which the BPD and Shockley stacking fault SD extend with respect to the upper surface of the epitaxial layer 64, that is, the off-angle θ (see FIG. 20) is, for example, 4 degrees or 8 degrees. The BPD and the Shockley type stacking fault SD continue to grow until the vertex N3 which is a part of them reaches the main surface of the substrate.

  FIG. 22 is a plan view showing a state in which Shockley-type stacking fault SD grows as a comparative example. Here, an annular second silicide layer 98 a is formed along the peripheral region 66 of the semiconductor chip 60. In FIG. 22, when the BPD nucleus (the apex N1 as the base point) is formed in the second contact region 83 formed in the termination region 67 of the semiconductor chip 60, the BPD and the Shockley-type stacking fault SD are formed from the nucleus. The state of growth is shown in three stages in order from the left.

  As shown in FIG. 22, when a pn current is passed through the second contact region 83 in a state where BPD is generated at the vertex N1 that is the end portion of the second contact region 83, BPD and Shockley type stacking fault SD are generated from the vertex N1. Gradually increases. Thereby, in the epitaxial layer 64, BPD generated on the upper surface of the epitaxial layer 64 propagates linearly in an oblique direction toward the bottom surface of the epitaxial layer 64, and Shockley-type stacking fault SD is formed on the bottom surface of the epitaxial layer 64. It spreads in an oblique direction.

  In FIG. 23, as a comparative example, when the annular second silicide layer 98a is formed along the peripheral region 66 of the semiconductor chip 60, Shockley type stacking faults SD1 to SD4 formed in the epitaxial layer 64 are shown. An example of In the semiconductor device of the comparative example shown in FIG. 23, a second silicide layer 98a having a rectangular annular structure is formed immediately above the second contact region 83 having a rectangular annular structure. That is, the second silicide layer 98a is formed on the upper surface of each of the first extension part E1, the second extension part E2, the third extension part E3, and the fourth extension part E4 constituting the second contact region 83. ing.

  Here, when the second contact region 83 is formed, a BPD is formed at the end of the second contact region 83, and thereafter, a potential is supplied to the second contact region 83 via the second silicide layer 98a so that the epitaxial layer 64 has an internal potential. The stacking faults SD <b> 1 to SD <b> 4 are grown by passing a pn current through. The stacking fault SD1 is a defect grown from the first extending portion E1 of the second contact region 83 as a base point. Similarly, the stacking faults SD2, SD3, and SD4 are defects that have grown from the second extending portion E2, the third extending portion E3, and the fourth extending portion E4 of the second contact region 83 as base points.

  In plan view, any stacking fault SD1 to SD4 grows in the direction opposite to the <11-20> direction from the base point, that is, in the <-1-120> direction. Therefore, the stacking fault SD3 grown from the third extending portion E3 located on the end side of the semiconductor chip 60 with respect to the element region 65 in the <-1-120> direction does not overlap with the element region 65 in plan view.

  Further, a part of the stacking fault SD4 grown from the fourth extending portion E4 located on the end side of the semiconductor chip 60 with respect to the element region 65 in the <11-20> direction overlaps the element region 65 in plan view. Here, for example, when the off-angle θ (see FIG. 20) is 4 degrees and the film thickness of the epitaxial layer 64 is 30 μm, the maximum width L1 of the Shockley-type stacking fault in the <11-20> direction ( 22) is 430 μm. Since 430 μm is extremely small with respect to the width of the semiconductor chip, the area where the stacking fault SD4 and the element region 65 overlap is very small in plan view.

  When the off angle θ is 4 degrees and the thickness of the epitaxial layer 64 is 30 μm, the maximum width L2 (see FIG. 22) of the Shockley-type stacking fault in the <1-100> direction is 1486 μm. Become. For this reason, the stacking faults SD1 and SD2 formed using the BPD generated in the first extending portion E1 or the second extending portion E2 as a base point are formed so as to largely overlap the element region 65 in plan view. The following problems occur in the semiconductor device of the comparative example having such stacking faults SD1 and SD2.

  Since the SiC power element is a vertical element in which current flows from the drift layer surface to the back surface, the current path is substantially perpendicular to the {0001} basal plane. The Shockley-type stacking fault SD shown in FIG. 21 behaves like a quantum well in the <0001> direction and functions as an electron trap. Therefore, the Shockley type stacking fault SD has a higher resistance than a normal region. Therefore, since the current flows avoiding the Shockley-type stacking fault SD, the current density increases by decreasing the area through which the current flows, and the element resistance (substrate resistance) and the forward voltage (ON voltage) with the passage of energization time. Will increase.

  In other words, stacking faults increase with energization time by passing a pn current through the BPD generated on the upper surface of the substrate in the manufacturing process. In this case, when a pn current is passed, carriers flowing in the substrate are captured by the stacking fault, so that the element resistance increases. That is, the stacking faults SD1 and SD2 (see FIG. 23) caused by the BPD generated in the termination region reach the center of the semiconductor chip and spread, so that the device resistance of the MOSFET in the device region increases. That is, as the energization time elapses, the MOSFET also has a problem that the resistance between the source and drain and the resistance of the built-in diode increase.

  However, in a pn diode or IGBT for high withstand voltage, it is necessary to energize the pn junction to reduce conduction loss. Further, in the all SiC power module in which the transistor and the diode are made into SiC, when the diode-less operation is performed for the purpose of reducing the size and weight of the device, it is necessary to energize the pn junction of the built-in diode of the MOSFET. An increase in element resistance of the SiC element becomes a problem.

  Here, the diode-less means that the built-in diode plays the role of a diode (for example, a Schottky barrier diode) connected in reverse parallel to the transistor in the inverter, for example. This eliminates the need to mount a diode on a chip including the transistor, and eliminates the need to prepare a chip on which a diode is mounted separately from the chip including the transistor, thereby reducing the size and weight of the device. It becomes.

  If the element resistance increases, the voltage required when a current of a predetermined value flows through the semiconductor device increases. That is, an increase in element resistance leads to hindering power saving of the semiconductor device. Further, the increase in the element resistance (substrate resistance) becomes more noticeable as a larger current flows through the pn junction in the SiC semiconductor substrate, so that the element resistance increases as the energization time of the semiconductor device elapses. That is, energization deterioration occurs. Therefore, there arises a problem that the characteristics of the semiconductor device cannot be maintained for a long time.

  On the other hand, in the present embodiment, as shown in FIG. 1, the region where the second silicide layer 98 is formed is limited to the upper surface of the third extending portion E3 and the upper surface of the fourth extending portion E4. As a result, even if the BPD is formed at the end of the second contact region 83 in the manufacturing process of the semiconductor device, the current flows through the second contact region 83 in the peripheral region 66 in the third extending portion E3 and the fourth extension region E3. Since only the extending portion E4 is provided, it is possible to prevent the stacking faults SD1 and SD2 (see FIG. 23) from being formed using the first extending portion E1 and the second extending portion E2 as a base point.

  That is, only the third extending portion E3 and the fourth extending portion E4 are connected to the second contact region 83 in ohmic contact with the contact plug 97 (see FIG. 2). Even if a pn current is passed through the second contact region 83, almost no current flows through the first extending portion E1 and the second extending portion E2. Therefore, since it is possible to prevent the stacking faults SD1 and SD2 (see FIG. 23) that greatly grow toward the element region 65 from being formed, it is possible to prevent an increase in the element resistance of the MOSFET.

  Note that the stacking fault SD3 (see FIG. 23) generated by energizing the third extending portion E3 does not overlap the element region 65, and therefore does not cause an increase in element resistance. In addition, since the region where the stacking fault SD4 (see FIG. 23) generated by energizing the fourth extending portion E4 overlaps the element region 65 is small, in the semiconductor device of the present embodiment, an increase in element resistance can be ignored. Can be suppressed.

<Modification>
Hereinafter, a modification of the semiconductor device of this embodiment will be described with reference to FIG. FIG. 14 is a plan view of a semiconductor chip which is a modification of the semiconductor device of the present embodiment.

  As shown in FIG. 14, the second contact region 83, the JTE region 85, the peripheral region 66, and the termination region 67 have a circular annular structure in plan view. Here, the second silicide layer 98 is also formed along the circular annular structure. However, the second silicide layer 98 is formed only immediately above each of the third extending portion E3 and the fourth extending portion E4 extending in a direction having a small angle with the <1-100> direction, and < It is not formed immediately above each of the first extending portion E1 and the second extending portion E2 extending in a direction having a small angle with the 11-20> direction. Although not shown, the contact plug 97 electrically connected to the second contact region 83 via the second silicide layer 98 also has the same layout as the second silicide layer 98 in plan view.

  Other structures are the same as those of the semiconductor chip described with reference to FIGS. Even with the planar layout as in this modification, the same effect as that of the semiconductor device described with reference to FIGS. 1 to 3 can be obtained.

(Embodiment 2)
In the second embodiment, as shown in FIG. 15, the formation of the second silicide layer 98 only on the upper surface of the third extending portion E3 of the rectangular second contact region 83 will be described. FIG. 15 is a plan view of a semiconductor chip which is the semiconductor device of the present embodiment.

  As shown in FIG. 15, the second silicide layer 98 is not formed on the upper surfaces of the first extension part E1 and the second extension part E2 of the second contact region 83, as in the above embodiment. Thereby, the same effect as the first embodiment can be obtained.

  In addition, in the present embodiment, the second silicide layer 98 is not formed on the upper surface of the fourth extending portion E4. That is, in the semiconductor chip 60 having the third extension portion E3 and the fourth extension portion E4 that are arranged in the <11-20> direction among the four extension portions constituting the second contact region 83, the third extension The second silicide layer 98 and the contact plug 97 (see FIG. 2) are formed on the upper surface of the existing portion E3, and the second silicide layer 98 and the contact plug 97 are not formed on the upper surface of the fourth extending portion E4. Accordingly, the cross-sectional view of the termination region 67 including the fourth extending portion E4 has the same structure as the termination region 1C shown in FIG.

  Thereby, it is possible to prevent the occurrence of the stacking fault SD4 that grows with the BPD formed in the fourth extending portion E4 shown in FIG. 23 as the base point. That is, it is possible to prevent a stacking fault that can overlap with the element region 65 of FIG. Thereby, an increase in element resistance due to prevention of stacking faults can be effectively prevented as compared with the semiconductor device described in the first embodiment.

  Such a structure can also be applied to the case where the termination region 67 and the like are circular as in the modification described with reference to FIG. Further, the second silicide layer 98 is not formed on the upper surfaces of the first extending portion E1, the second extending portion E2, and the third extending portion E3 in FIG. 15, but only on the upper surface of the fourth extending portion E4. Even if the silicide layer is formed, the occurrence of stacking faults can be suppressed as compared with the comparative example described with reference to FIGS.

(Embodiment 3)
In the third embodiment, a power conversion device including the SiC power element of the first embodiment will be described. FIG. 16 is a circuit diagram of the power conversion device (inverter) of the present embodiment. As shown in FIG. 16, the inverter according to the present embodiment includes a plurality of SiC power MISFETs (Metal Insulator Semiconductor FETs) 404 that are switching elements in a power module 402. In each single phase, SiC power MISFET 404 is connected between power supply voltage Vcc and the input potential of load (for example, motor) 401 via terminals 405 to 409, and SiC power MISFET 404 constitutes the upper arm. . Further, the SiC power MISFET 404 is also connected between the input potential of the load 401 and the ground potential GND, and the SiC power MISFET 404 constitutes the lower arm. That is, in the load 401, two SiC power MISFETs 404 are provided for each single phase, and six switching elements (SiC power MISFETs 404) are provided for three phases.

  The power supply voltage Vcc is connected to the drain electrode of each single-layer SiC power MISFET 404 via a terminal 405, and the ground potential GND is connected to the source electrode of each single-layer SiC power MISFET 404 via a terminal 409. Has been. Further, the load 401 is connected to the source electrode of each single-layer SiC power MISFET 404 of each single-layer upper arm via each of the terminals 406 to 408, and each single-layer is connected via each of the terminals 406 to 408. The lower arm is connected to the drain electrode of each single-layer SiC power MISFET 404.

  A control circuit 403 is connected to the gate electrode of each SiC power MISFET 404 via terminals 410 and 411, and the SiC power MISFET 404 is controlled by the control circuit 403. Therefore, the inverter of this embodiment can drive the load 401 by controlling the current flowing through the SiC power MISFET 404 constituting the power module 402 by the control circuit 403.

The SiC power MISFET 404 uses a MOSFET formed on the semiconductor chip 60 (see FIG. 1) described in the first embodiment. As shown in FIG. 16, a built-in pn diode included in the MOSFET is formed in the SiC power MISFET 404. The built-in pn diode is, for example, a pn junction between the p-type well region 80 connected to the p ⁺ -type first contact region 82 and the n ⁻ -type epitaxial layer 64 shown in FIG. It refers to a pn junction portion between the p-type JTE region 85 connected to the p ⁺ -type second contact region 83 and the n ⁻ -type epitaxial layer 64.

  That is, the anode of the built-in pn diode is connected to the source electrode of the MOSFET, and the cathode is connected to the drain electrode of the MOSFET. Therefore, in each single layer shown in FIG. 16, the built-in pn diode is connected in antiparallel to the MOSFET. The function of the built-in pn diode at this time will be described below.

  The built-in pn diode is not necessary when the load 401 is a pure resistor that does not include an inductance because there is no energy to circulate. However, when a circuit including an inductance such as a motor (electric motor) is connected to the load 401, there is a mode in which a load current flows in a direction opposite to that of a MOSFET that is an ON switching element. At this time, since the MOSFET alone does not have a function of allowing a load current flowing in the reverse direction to flow, it is necessary to connect a built-in pn diode in reverse parallel to the MOSFET.

  That is, in the power module 402, for example, when the load 401 includes an inductance such as a motor, the energy stored in the inductance must be released when the MOSFET is turned off. However, the MOSFET alone cannot flow a reverse current for releasing the energy stored in the inductance. Therefore, in order to recirculate the electric energy stored in the inductance, a built-in pn diode is connected to the MOSFET in the reverse direction. That is, the built-in pn diode has a function of flowing a reverse current to release the electrical energy stored in the inductance.

  When the power module 402 is configured by a MOSFET and a diode, it is conceivable to connect a semiconductor chip provided with a diode to a semiconductor chip provided with a MOSFET. However, in this case, since it is necessary to provide a semiconductor chip including a diode in addition to the semiconductor chip including a MOSFET, there is a problem that the power module 402 and the inverter are increased in size. Even when a semiconductor chip including a diode is not prepared separately, and a Schottky barrier diode or the like connected to the MOSFET is mixedly mounted on the semiconductor chip on which the MOSFET is formed, there is a problem that the power module 402 and the inverter are increased in size. Arise. Also, preparing a diode as described above without using a diode-less device increases the manufacturing cost of the semiconductor device.

  In contrast, in the present embodiment, in the power module 402, the semiconductor chip that is the semiconductor device described in the first embodiment is used for the MOSFET and the built-in pn diode. That is, the MOSFET shown in FIG. 2 and the built-in pn diode connected in reverse parallel thereto are provided on one semiconductor chip. In a semiconductor chip including a BPD, there is a problem that energization deterioration occurs when a pn current is passed through a built-in pn diode. However, the semiconductor device described in the first embodiment has a problem in that a pn current is passed through the built-in diode and the peripheral region. An increase in the resistance value can be suppressed.

  Thus, in the power module 402 and the inverter that use the semiconductor device of the first embodiment for a MOSFET, it is possible to energize and use the pn junction of the MOSFET's built-in pn diode. Can be used. Thereby, an unnecessary diode element can be removed. That is, since the built-in diode of the MOSFET constituting the semiconductor chip which is the semiconductor device described in the first embodiment can be used as the built-in pn diode shown in FIG. 16, another diode is attached to the semiconductor chip including the MOSFET. No need to connect. Thereby, about the power converter device which consists of an inverter containing the power module 402, size reduction, weight reduction, and cost reduction can be implement | achieved, preventing the high resistance by energization deterioration.

  The power converter can be used for a three-phase motor system. The load 401 shown in FIG. 16 is a three-phase motor, and the three-phase motor system can be reduced in size by using the power conversion device including the semiconductor device shown in the first embodiment for the inverter. .

(Embodiment 4)
The three-phase motor system described in the third embodiment can be used for vehicles such as hybrid vehicles, electric vehicles, and fuel cell vehicles. In the present embodiment, an automobile equipped with a three-phase motor system will be described with reference to FIGS. FIG. 17 is a schematic diagram showing the configuration of the electric vehicle of the present embodiment. FIG. 18 is a circuit diagram of the boost converter according to the present embodiment.

  As shown in FIG. 17, the electric vehicle according to the present embodiment includes a three-phase motor 503 that can input and output power to a drive shaft 502 to which drive wheels (wheels) 501a and 501b are connected, An inverter 504 for driving the three-phase motor 503 and a battery 505 are provided. Furthermore, the electric vehicle of the present embodiment includes a boost converter 508, a relay 509, and an electronic control unit 510. The boost converter 508 is connected to a power line 506 to which an inverter 504 is connected and a battery 505. It is connected to the power line 507. The three-phase motor 503 is a synchronous generator motor including a rotor embedded with permanent magnets and a stator wound with a three-phase coil. As the inverter 504, the inverter described in Embodiment 3 is used.

  As shown in FIG. 18, boost converter 508 has a configuration in which a reactor 511 and a smoothing capacitor 512 are connected to inverter 513. For example, the inverter 513 is the same as the inverter described in the third embodiment, and the element configuration in the inverter is the same. Again, as in the third embodiment, the switching element is the SiC power MISFET 514 and is driven by synchronous rectification. In the electric vehicle according to the present embodiment, the output is supplied to the three-phase motor 503 using the inverter 504 that is a power conversion device and the boost converter 508 that is a power conversion device, so that driving wheels (wheels) are driven by the three-phase motor 503. 501a and 501b are driven.

  The electronic control unit 510 shown in FIG. 17 includes a microprocessor, a storage device, and an input / output port. A signal from a sensor that detects the rotor position of the three-phase motor 503, a charge / discharge value of the battery 505, and the like. Receive. Electronic control unit 510 outputs a signal for controlling inverter 504, boost converter 508, and relay 509.

  According to the present embodiment, the power conversion device of the third embodiment can be used for inverter 504 and boost converter 508 which are power conversion devices. Further, the three-phase motor system of the third embodiment can be used for a three-phase motor system including the three-phase motor 503, the inverter 504, and the like. As a result, it is possible to reduce the size, weight and cost of the electric vehicle by reducing the volume of the drive system occupying the electric vehicle while preventing the deterioration of energization of the inverter 504 and the boost converter 508 of the electric vehicle. .

  In the present embodiment, the electric vehicle has been described. However, the above-described three-phase motor system can be similarly applied to a hybrid vehicle that also uses an engine and a fuel cell vehicle in which the battery 505 is a fuel cell stack. .

(Embodiment 5)
The three-phase motor system of the third embodiment can be used for a railway vehicle. In the present embodiment, a railway vehicle using a three-phase motor system will be described with reference to FIG. FIG. 19 is a circuit diagram including a converter and an inverter of the railway vehicle of the present embodiment.

  As shown in FIG. 19, electric power of, for example, 25 kV is supplied to the railway vehicle from the overhead line OW via the pantograph PG. The voltage is stepped down to 1.5 kV via the transformer 609 and converted from alternating current to direct current by the converter 607. Further, the inverter 602 converts the direct current into the alternating current through the capacitor 608, and the three-phase motor as the load 601 is driven. In the present embodiment, the switching element is synchronously rectified and driven as the SiC power MISFET 604 as in the third embodiment. In FIG. 19, the control circuit described in the third embodiment is not shown. The overhead line OW is electrically connected to the line RT via the pantograph PG, the transformer 609, and the wheels WH.

  According to the present embodiment, the power conversion device of the third embodiment can be used for converter 607. That is, the wheel WH of a railway vehicle can be driven by supplying electric power from the power converter to the load 601. Further, the three-phase motor system of the third embodiment can be used for the three-phase motor system including the load 601, the inverter 602, and the control circuit. Thereby, size reduction, weight reduction, and cost reduction of a railway vehicle are realizable, preventing the energization deterioration of the inverter 602 and the converter 607 of a railway vehicle.

  As mentioned above, the invention made by the present inventors has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. is there.

64 Epitaxial layer 65 Device region (active region)
67 termination region 83 second contact region 85 JTE region 98 second silicide layer E1 first extension portion E2 second extension portion E3 third extension portion E4 fourth extension portion

Claims (11)

An n-type substrate which is a hexagonal semiconductor substrate containing silicon carbide;
A semiconductor layer including an n-type drift layer formed on the substrate;
In a termination region surrounding the element region, a p-type first semiconductor region formed on the upper surface of the semiconductor layer;
A silicide layer formed on an upper surface of the first semiconductor region;
A contact plug connected to the first semiconductor region via the silicide layer;
Have
In plan view, the first semiconductor region includes a first extension portion extending in a first direction, a second extension portion extending in a second direction, a third extension portion extending in a third direction, and Having an annular structure connecting the fourth extending portions extending in the fourth direction;
The angle formed by the first direction and the second direction with the <11-20> direction of the substrate is smaller than the angle formed by the third direction and the fourth direction with the <11-20> direction of the substrate.
In plan view, the area of the silicide layer formed on the upper surface of the third extending portion is larger than the area of the silicide layer formed on the upper surface of the first extending portion and the upper surface of the second extending portion. Large semiconductor device. The semiconductor device according to claim 1,
The semiconductor device, wherein the third extending portion, the element region, and the fourth extending portion are arranged in order in the <11-20> direction of the substrate. The semiconductor device according to claim 2,
In plan view, the area of the silicide layer formed on the upper surface of the third extending portion is larger than the area of the silicide layer formed on the upper surface of the fourth extending portion. The semiconductor substrate according to claim 2,
In plan view, the area of the silicide layer formed on the upper surface of the fourth extending portion is larger than the area of the silicide layer formed on the upper surface of the first extending portion and the upper surface of the second extending portion. Large semiconductor device. The semiconductor device according to claim 1,
The semiconductor device, wherein the first semiconductor region and the substrate constitute a first pn diode. The semiconductor device according to claim 1,
An n-type source region formed on the upper surface of the semiconductor layer in the element region;
A gate electrode formed on the semiconductor layer in the element region via an insulating film;
A p-type second semiconductor region formed on an upper surface of the semiconductor layer in the element region;
Further comprising
The source region and the second semiconductor region are electrically connected via a conductor formed on the second semiconductor region,
The substrate, the source region and the gate electrode constitute a field effect transistor,
The semiconductor device, wherein the second semiconductor region and the substrate constitute a second pn diode. The semiconductor device according to claim 1,
The semiconductor device, wherein the concentration of the p-type impurity in the first semiconductor region is 1 × 10 ¹⁸ to 1 × 10 ²⁰ cm ⁻³ .   A power module comprising the semiconductor device according to claim 1. A power module comprising the semiconductor device according to claim 1;
A control circuit for controlling the semiconductor device in the power module;
A power converter. A power conversion device using the semiconductor device according to claim 1;
An electric motor that drives a wheel by receiving power supply from the power converter;
An automobile equipped with. A power conversion device using the semiconductor device according to claim 1;
An electric motor that drives a wheel by receiving power supply from the power converter;
A railway vehicle comprising:

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