JP5687128B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device using a wide bandgap semiconductor.

  Semiconductor devices, especially field effect transistors (MOSFETs) having a metal / oxide / semiconductor junction structure (MOS), are required to have low loss from the viewpoint of power electronics applications and energy saving of mounted equipment. In particular, there is a demand for reduction in loss (on loss) during energization, that is, reduction in on-resistance.

  One solution is to reduce channel resistance and JFET (junction FET) resistance.

  In Patent Document 1, an impurity diffusion layer formed by introducing an impurity of a first conductivity type different from a well is provided between adjacent wells (JFET region), thereby reducing the JFET region and miniaturizing the element. However, a method for reducing the on-resistance of the device by reducing the resistance of the JFET region rather than increasing it is disclosed.

  Further, first and second impurity diffusion layers formed simultaneously by ion implantation using the same mask are formed in order to suppress variations in device characteristics due to variations in channel length in a unit cell which is a unit structure of the MOSFET. Thus, a method for determining the channel length according to the separation distance is disclosed.

JP 2006-303324 A

  However, in the plan view of the first and second impurity diffusion layers shown in FIG. 2 of Patent Document 1, the corner portions thereof are at right angles, and the channel length viewed from the JFET region side, that is, the first and second impurities. Since the separation distance of the diffusion layer is not constant in all parts, the ON current does not flow uniformly in all parts in the unit cell, and there is a possibility that the reliability of the semiconductor device is impaired due to current concentration particularly in the corner part. There was a problem that there was.

  The present invention has been made to solve the above-described problems, and provides a semiconductor device with improved reliability by realizing a uniform on-current distribution in a unit cell, as well as a controlled fine structure. An object of the present invention is to provide a semiconductor device capable of realizing a channel length and achieving a low channel resistance, and a manufacturing method thereof.

The semiconductor device according to the present invention includes a first conductive type semiconductor substrate, a first conductive type semiconductor layer disposed on the semiconductor substrate, and a plurality of selectively disposed on an upper layer portion of the semiconductor layer. A second conductivity type well region, a first conductivity type source region selectively disposed within the surface of the well region, and surrounding the source region in contact with an edge of the source region. In addition, the first conductivity type extension region disposed in the surface of the well region and the first conductivity type of the first conductivity type disposed so as to extend between the edge portions on the upper surface side of the well regions adjacent to each other. A channel length of a channel region is defined by a distance between the extension region and the semiconductor region, and the extension region is a circle having a first radius of curvature in a planar view shape. No arc The semiconductor region, in its plan view shape, to name a circular arc shape having a second radius of curvature corner portion is also the first radius of curvature and the center, the well region, in its plan view shape, a corner part is an arc shape having a third radius of curvature, said third radius of curvature, Ru small radius of curvature der than the first and second radii of curvature.

  According to the aspect of the semiconductor device of the present invention, the channel length of the entire channel region is uniform with the channel length determined by the difference between the second radius of curvature and the first radius of curvature. The current distribution during operation is constant, and the reliability is increased.

1 is a top view of a silicon carbide semiconductor device according to the present invention. It is a top view which shows typically each impurity region formed in the main surface of the semiconductor substrate of the silicon carbide semiconductor device which concerns on this invention. It is a fragmentary sectional view of the silicon carbide semiconductor device concerning the present invention. It is a fragmentary sectional view of the silicon carbide semiconductor device concerning the present invention. It is a top view of the unit cell of the silicon carbide semiconductor device of Embodiment 1 which concerns on this invention. It is a top view of the unit cell of the silicon carbide semiconductor device of Embodiment 1 which concerns on this invention. It is a top view of the unit cell of the silicon carbide semiconductor device of Embodiment 1 which concerns on this invention. It is sectional drawing explaining the manufacturing process of the silicon carbide semiconductor device of Embodiment 1 which concerns on this invention. It is sectional drawing explaining the manufacturing process of the silicon carbide semiconductor device of Embodiment 1 which concerns on this invention. It is sectional drawing explaining the manufacturing process of the silicon carbide semiconductor device of Embodiment 1 which concerns on this invention. It is sectional drawing explaining the manufacturing process of the silicon carbide semiconductor device of Embodiment 1 which concerns on this invention. It is sectional drawing explaining the manufacturing process of the silicon carbide semiconductor device of Embodiment 1 which concerns on this invention. It is sectional drawing explaining the manufacturing process of the silicon carbide semiconductor device of Embodiment 1 which concerns on this invention. It is sectional drawing explaining the manufacturing process of the silicon carbide semiconductor device of Embodiment 1 which concerns on this invention. It is sectional drawing explaining the manufacturing process of the silicon carbide semiconductor device of Embodiment 1 which concerns on this invention. It is sectional drawing explaining the manufacturing process of the silicon carbide semiconductor device of Embodiment 1 which concerns on this invention. It is sectional drawing explaining the manufacturing process of the silicon carbide semiconductor device of Embodiment 1 which concerns on this invention. It is sectional drawing explaining the manufacturing process of the silicon carbide semiconductor device of Embodiment 1 which concerns on this invention. It is sectional drawing explaining the manufacturing process of the silicon carbide semiconductor device of Embodiment 1 which concerns on this invention. It is sectional drawing explaining the manufacturing process of the silicon carbide semiconductor device of Embodiment 1 which concerns on this invention. It is sectional drawing explaining the manufacturing process of the silicon carbide semiconductor device of Embodiment 1 which concerns on this invention. It is sectional drawing explaining the manufacturing process of the silicon carbide semiconductor device of Embodiment 1 which concerns on this invention. It is a figure which shows the shape of one corner part of the impurity region in the planar view of the unit cell of the conventional silicon carbide semiconductor device. It is a figure which shows the shape of one corner part of the impurity region in the planar view of the unit cell of the conventional silicon carbide semiconductor device. It is a figure which shows the shape of one corner part of the impurity region in the planar view of the unit cell of the silicon carbide semiconductor device of Embodiment 1 which concerns on this invention. It is a figure which shows the numerical calculation result in the silicon carbide semiconductor device of Embodiment 1 which concerns on this invention. It is a figure which shows the numerical calculation result in the silicon carbide semiconductor device of Embodiment 1 which concerns on this invention. It is a figure which shows the example of the implantation mask obtained with the manufacturing method of the silicon carbide semiconductor device of Embodiment 1 which concerns on this invention. It is a figure which shows the example of the implantation mask obtained with the manufacturing method of the silicon carbide semiconductor device of Embodiment 1 which concerns on this invention. It is a figure which shows the example of the implantation mask obtained with the manufacturing method of the silicon carbide semiconductor device of Embodiment 1 which concerns on this invention. It is a figure which shows the example of the implantation mask obtained with the manufacturing method of the silicon carbide semiconductor device of Embodiment 1 which concerns on this invention. It is a figure which shows the example of the implantation mask obtained with the manufacturing method of the silicon carbide semiconductor device of Embodiment 1 which concerns on this invention. It is a top view which shows arrangement | positioning of the unit cell of the silicon carbide semiconductor device of Embodiment 1 which concerns on this invention. It is a top view which shows arrangement | positioning of the unit cell of the silicon carbide semiconductor device of Embodiment 1 which concerns on this invention. It is a figure which shows the shape of one corner part of the impurity region in the planar view of the unit cell of the silicon carbide semiconductor device of Embodiment 1 which concerns on this invention. It is sectional drawing which shows the structure of the silicon carbide semiconductor device of Embodiment 2 which concerns on this invention. It is sectional drawing explaining the manufacturing process of the silicon carbide semiconductor device of Embodiment 2 which concerns on this invention. It is sectional drawing explaining the manufacturing process of the silicon carbide semiconductor device of Embodiment 2 which concerns on this invention. It is sectional drawing explaining the manufacturing process of the silicon carbide semiconductor device of Embodiment 2 which concerns on this invention. It is a figure which shows the shape of one corner part of the impurity region in the planar view of the unit cell of the silicon carbide semiconductor device of Embodiment 2 which concerns on this invention. It is a top view which shows arrangement | positioning of the unit cell of the silicon carbide semiconductor device of Embodiment 2 which concerns on this invention. It is sectional drawing which shows the structure of the silicon carbide semiconductor device of Embodiment 3 which concerns on this invention. It is sectional drawing explaining the manufacturing process of the silicon carbide semiconductor device of Embodiment 3 which concerns on this invention. It is sectional drawing explaining the manufacturing process of the silicon carbide semiconductor device of Embodiment 3 which concerns on this invention. It is a top view which shows arrangement | positioning of the unit cell of the silicon carbide semiconductor device of Embodiment 3 which concerns on this invention. It is sectional drawing which shows the structure of the silicon carbide semiconductor device of Embodiment 4 which concerns on this invention. It is sectional drawing explaining the manufacturing process of the silicon carbide semiconductor device of Embodiment 4 which concerns on this invention. It is sectional drawing explaining the manufacturing process of the silicon carbide semiconductor device of Embodiment 4 which concerns on this invention. It is sectional drawing explaining the manufacturing process of the silicon carbide semiconductor device of Embodiment 4 which concerns on this invention. It is sectional drawing which shows the structure of the silicon carbide semiconductor device of Embodiment 5 which concerns on this invention. It is sectional drawing explaining the manufacturing process of the silicon carbide semiconductor device of Embodiment 5 which concerns on this invention.

<Introduction>
The term “MOS” has been used in the past for metal / oxide / semiconductor junctions, and is taken from the acronym Metal-Oxide-Semiconductor. However, in particular, in a field effect transistor having a MOS structure (hereinafter, simply referred to as “MOS transistor”), materials for a gate insulating film and a gate electrode have been improved from the viewpoint of recent integration and improvement of a manufacturing process.

  For example, in a MOS transistor, polycrystalline silicon has been adopted instead of metal as a material of a gate electrode mainly from the viewpoint of forming a source / drain in a self-aligned manner. From the viewpoint of improving electrical characteristics, a material having a high dielectric constant is adopted as a material for the gate insulating film, but the material is not necessarily limited to an oxide.

  Therefore, the term “MOS” is not necessarily limited to the metal / oxide / semiconductor stacked structure, and is not presumed in this specification. That is, in view of the common general knowledge, “MOS” is not only an abbreviation derived from the word source, but also has a meaning including widely a laminated structure of a conductor / insulator / semiconductor.

  Further, in the following description, regarding the conductivity type of impurities, the n-type is generally defined as “first conductivity type” and the p-type is defined as “second conductivity type”, but the opposite definition may be used.

<Embodiment 1>
<Device configuration>
FIG. 1 shows a silicon carbide (SiC) semiconductor device according to the first embodiment of the present invention, more specifically, a top surface of a field effect transistor (silicon carbide MOS transistor) 1000 having a MOS structure formed on a SiC substrate. It is a top view which shows a structure typically.

  As shown in FIG. 1, silicon carbide MOS transistor 1000 has a source pad 41 provided at the center of the main surface of chip 5 having a rectangular outer shape, and a gate wiring 44 provided so as to surround the outside of source pad 41. It has been.

  The source pad 41 has a rectangular shape in which the central part of one side is recessed inward, and a gate pad 45 extending from the surrounding gate wiring 44 is provided so as to enter the recessed part inside the source pad 41. It has been.

  The gate pad 45 is a portion to which a gate voltage is applied from an external control circuit (not shown). The gate voltage applied thereto is a gate of a unit cell which is a minimum unit structure of a MOS transistor through a gate wiring 44. It is supplied to an electrode (not shown).

  The source pad 41 is provided on an active region where a plurality of unit cells are arranged, and a source electrode (not shown) of each unit cell is connected in parallel.

  Below the source pad 41, a termination well region 27 is provided at the edge of the active region AR where the unit cell is formed, and a termination low resistance region 28 formed so as to surround the termination well region 27, A JTE (Junction Termination Extension) region 50 formed so as to surround the resistance region 28 and a field stop region 13 formed so as to surround the JTE region 50 apart from the JTE region 50 are provided. This will be explained later.

  Note that in ordinary products, electrodes for temperature sensors and current sensors are often formed together, but the presence or absence of these electrodes is not related to the configuration and effects of the present invention. And illustration is abbreviate | omitted.

  Further, the position and number of the gate pads 45, the shape of the gate wiring 44 and the shape and number of the source pads 41 may have various cases depending on the MOS transistor, but these are also the same as the current sensor electrodes described above. Since the relationship with the configuration and effect of the present invention is small, description and illustration are omitted.

  FIG. 2 is a plan view schematically showing each impurity region formed in the main surface of the semiconductor substrate of silicon carbide MOS transistor 1000. Source pad 41, gate wiring 44 and gate pad 45 shown in FIG. The structure below is shown.

  A second conductivity type termination well region 27 is provided at an edge of the active region AR where a plurality of unit cells UC are arranged, and a second conductivity type termination low resistance region 28 is provided so as to surround the termination well region 27. The second conductivity type JTE region 50 is provided so as to surround the terminal low resistance region 28, and the first conductivity type field stop region 13 is provided so as to surround the JTE region 50 apart from the JTE region 50. It has been.

  The unit cells UC have a square outer shape, and are arranged so that the center positions of the unit cells UC are staggered with a half-cycle shift from the center positions of the unit cells UC in the adjacent arrays. Yes.

  Note that the above is an example, and the outer shape of the unit cell UC is not limited to a square, but may be a rectangle or a hexagon, and the arrangement period may be the same in both the vertical and horizontal directions.

  Next, a cross-sectional configuration taken along line AA shown in FIG. 1 will be described using the cross-sectional view shown in FIG. As shown in FIG. 3, silicon carbide MOS transistor 1000 includes a first conductivity type drift layer 2 formed on a main surface of semiconductor substrate 1 which is a silicon carbide substrate containing a first conductivity type impurity, and a semiconductor substrate. 1 is provided with an ohmic electrode 42 and a drain electrode 43 formed on the ohmic electrode 42, which are formed on the back surface side (the side opposite to the main surface side on which the source pad 41 is provided).

  In addition, in the upper layer portion of the drift layer 2, a plurality of well regions 20 of a second conductivity type that are selectively formed and the same depth as the well regions 20 and defining the edge of the active region AR are defined. A two-conductivity type termination well region 27, a JTE region 50 connected to the end face of the termination well region 27 and surrounding the termination well region 27, and a field stop region 13 spaced from the JTE region 50 and surrounding the JTE region 50 are provided. It has been.

  In the surface of the well region 20, a first conductivity type source region 12 and a second conductivity type well contact region 21 that penetrates the source region 12 from the upper surface side of the central portion of the source region 12 and reaches the well region 20. And a source extension region 10 which is connected to the end face of the source region 12 and forms a part of the MOS structure.

  Also in the surface of the termination well region 27, the source region 12, the well contact region 21 that reaches the termination well region 27 through the source region 12 from the center upper surface side of the source region 12, and the end surface of the source region 12 are connected. The source extension region 10 is provided only at the edge of the termination well region 27 on the side facing the well region 20, and most of the surface of the termination well region 27 is disposed on the edge of the termination well region 27. The terminal conductive low resistance region 28 of the second conductivity type is provided, and the JTE region 50 is also connected to the end face of the terminal low resistance region 28.

  A first conductivity type JFET extension region 11 extends from an upper surface side edge of the well region 20 to an upper surface side edge of the termination well region 27. The JFET extension region 11 includes the JFET extension region 11 and the source extension. The inside of the well region 20 and the termination well region 27 between the region 10 is defined as a channel region.

  Here, the JFET region is a region between adjacent wells. By implanting a relatively high concentration of the first conductivity type impurity into the JFET region, the channel region can be transferred to the silicon carbide substrate 1 in the ON state. Therefore, the resistance value of the current path formed in the direction can be reduced, and the on-resistance of the entire vertical MOSFET can be reduced.

  On the main surface of the drift layer 2, the well region 20 and the termination well region 27 between the JFET extension region 11 and the source extension region 10, a part of the termination well region 27, and the edge of the source region 12 And a gate insulating film 30 formed so as to cover the source extension region 10 and the JFET extension region 11, and a field oxide film 31 formed on the drift layer 2 where the gate insulating film 30 is not formed. ing.

  A gate electrode 35 is formed on the gate insulating film 30 located on the channel region and the source extension region 10 from the JFET extension region 11, and an interlayer insulating film 32 is formed so as to cover the gate electrode 35. .

  The gate electrode 35 is also formed at a portion where the gate insulating film 30 and the field oxide film 31 are connected, and is also formed on the field oxide film 31 on the terminal low resistance region 28. Is also covered with an interlayer insulating film 32.

  A gate contact hole GC is provided so as to penetrate the interlayer insulating film 32 and reach the gate electrode 35 above the terminal low resistance region 28, and a gate wiring 44 is formed so as to fill the gate contact hole GC.

  A well contact hole WC is provided so as to reach the ohmic electrode 40 formed on the terminal low resistance region 28 through the interlayer insulating film 32 and the field oxide film 31, and penetrate through the interlayer insulating film 32. Source contact hole SC is provided so as to reach ohmic electrode 40 formed on well contact region 21 and source region 12, and source pad 41 is formed so as to fill well contact hole WC and source contact hole SC. Yes. With such a configuration, the source pad 41 is a source electrode connected to the source region 12 and also a member for electrically connecting the source region 12 and the termination well region 27.

  Next, a cross-sectional configuration taken along line BB shown in FIG. 1 will be described with reference to a cross-sectional view shown in FIG. In FIG. 4, one unit cell UC is surrounded by a broken line. As shown in FIG. 4, the unit cell UC has a source region 12 formed in the surface of one well region 20, and penetrates through the source region 12 from the upper surface side of the central portion of the source region 12. A well contact region 21 reaching the end of the source region 12 and a source extension region 10 connected to the end face of the source region 12 and forming a part of the MOS structure.

  A JFET extension region 11 extends between edge portions on the upper surface side of adjacent well regions 20, and the JFET extension region 11 is located inside the well region 20 between the JFET extension region 11 and the source extension region 10. Is defined as the channel region.

  The source region 12 is electrically connected to the source pad 41 that is a source electrode via the ohmic electrode 40.

  Here, the cross-sectional shape of the well region 20 has a trapezoidal shape in which the bottom surface side is wide and the top surface side is narrow. The region where the minimum width is defined by the distance between them is the JFET region 7, and the JFET region 7 surrounds the well region 20.

  Next, the planar configuration taken along line CC shown in FIG. 4 will be described with reference to the plan view shown in FIG. As shown in FIG. 5, an interlayer insulating film 32 surrounds the ohmic electrode 40 having a substantially rectangular outer shape, and the outer periphery thereof is surrounded by the gate electrode 35.

  Next, a planar configuration taken along line DD shown in FIG. 4 will be described using the plan view shown in FIG. As shown in FIG. 6, the source region 12 surrounds the periphery of the well contact region 21 having a substantially rectangular outer shape, and the source extension region 10 and the JFET extension region 11 surround the source region 12. And the inside of the well region 20 between the JFET extension region 11 becomes a channel region, and the length indicated by L1 in the drawing corresponds to the channel length.

  Next, the planar configuration taken along line EE shown in FIG. 4 will be described using the plan view shown in FIG. As shown in FIG. 7, the source region 12 surrounds the well contact region 21 whose outer shape is substantially square, the well region 20 surrounds the source region 12, and the JFET region 7 surrounds the well region 20. It is out. As shown in FIG. 4, the JFET region 7 exists so as to extend between adjacent unit cells UC. Therefore, when the width is L2, in one unit cell UC, the length is half of L2. (L2 / 2).

  One of the features of the present invention is that the corners of the source extension region 10 and the JFET extension region 11 are centered using a mask having a radius of curvature at the corner larger than the radius of curvature generated in the photoengraving process. Are equal to the radii of curvature of the radii r1 and r2, and satisfy the relationship r2-r1 = L1 (channel length), so that the channel length in the unit cell UC is equal to that of the channel region including the corner portion. Constant in all parts. As a result, a uniform on-current distribution can be realized in the unit cell UC, and the reliability of the MOS transistor 1000 can be improved.

<Manufacturing method>
Next, a method for manufacturing silicon carbide MOS transistor 1000 of the first embodiment will be described with reference to FIGS. Note that the cross-sectional views shown in FIGS. 8 to 22 do not include the structure of the element termination portion, and for example, an arbitrary position in the region where the unit cell UC is disposed, such as the position along the line BB in FIG. FIG. 3 is a cross-sectional view of a portion corresponding to one unit cell UC.

  First, a silicon carbide substrate containing a first conductivity type impurity is prepared as the semiconductor substrate 1. Here, as a material of the semiconductor substrate 1, in addition to silicon carbide, a wide band gap semiconductor having a band gap larger than that of silicon (Si) can be used. Examples of other wide band gap semiconductors include gallium nitride. Materials, aluminum nitride materials, diamond, and the like.

  Switching devices and diodes composed of such wide bandgap semiconductors as substrate materials have high voltage resistance and high allowable current density, and therefore can be made smaller than silicon semiconductor devices. By using switching devices and diodes, it is possible to reduce the size of a semiconductor device module incorporating these devices.

  In addition, since the heat resistance is high, it is possible to reduce the size of the heat sink fins of the heat sink and to cool by air cooling instead of water cooling, thereby further miniaturizing the semiconductor device module.

  Further, the surface orientation of the semiconductor substrate 1 may be inclined to 8 ° or less with respect to the c-axis direction, but may not be inclined, and may have any surface orientation. .

Next, in the step shown in FIG. 8, a silicon carbide epitaxial layer of the first conductivity type is formed on the upper portion of the semiconductor substrate 1 by epitaxial crystal growth to form the drift layer 2. Here, the impurity concentration of the first conductivity type of the drift layer 2 is, for example, in the range of 1 × 10 ¹³ cm ⁻³ to 1 × 10 ¹⁸ cm ⁻³ , and the thickness is 4 μm to 200 μm.

  Next, a resist material is applied on the main surface of the drift layer 2 (or a silicon oxide film is formed) and patterned by photolithography (and etching) to form the well region 20 and the termination well region 27 (FIG. 3). An implantation mask 100 in which the corresponding part is an opening is formed. Thereafter, ion implantation of the second conductivity type impurity is performed using the implantation mask 100 to form the well region 20 and the termination well region 27 (FIG. 3).

  Here, the semiconductor substrate 1 at the time of implanting impurity ions may not be positively heated, or may be ion-implanted by heating to a temperature of 100 ° C. to 800 ° C. As the implanted impurity, nitrogen (N) or phosphorus (P) is preferable when the first conductivity type is n-type, and aluminum (Al) or boron is preferable when the first conductivity type is p-type. (B) is preferred.

  The depth of the well region 20 is set so as not to exceed the bottom surface of the drift layer 2, and is set to a depth in the range of 0.3 μm to 2.0 μm, for example.

The impurity concentration of the well region 20 exceeds the impurity concentration of the drift layer 2 and is set, for example, in the range of 1 × 10 ¹⁵ cm ⁻³ to 1 × 10 ¹⁹ cm ⁻³ . However, only in the vicinity of the outermost surface of well region 20, the impurity concentration of the second conductivity type of well region 20 is the first conductivity type of drift layer 2 in order to increase the conductivity in the channel region of silicon carbide MOS transistor 1000. The impurity concentration may be lower.

  That is, if the impurity concentration of the first conductivity type in the channel region is relatively higher than the impurity concentration of the second conductivity type, the first conductivity type carriers (electrons if the first conductivity type is n type) are correspondingly generated. More will be present, increasing the conductivity of the channel.

  For such a configuration, the ion implantation of the second conductivity type impurity when forming the well region 20 may be a profile having a concentration peak in the deep portion of the drift layer 2. In the silicon carbide semiconductor, impurities are hardly thermally diffused even by heat treatment, so such a method is effective.

  Further, as shown in FIG. 8, the cross-sectional shape of the well region 20 has a trapezoidal shape with a wide bottom surface and a narrow top surface. This is because the impurity ions are implanted by using a high vertical implantation mask 100 as shown in FIG. 8, and the impurity ions are implanted at a high acceleration energy without intentionally implanting from an oblique direction of the substrate. This is because scattering in the lateral direction (direction parallel to the main surface of the substrate 1) in the drift layer 2 increases, and the end surface is tapered to form a trapezoidal well region 20.

  The lateral diffusion distance L4 of the implanted impurity from the end of the implantation mask 100 shown in FIG. 8 is about 0.3 μm, and the acceleration energy of the impurity ions for obtaining this value is, for example, about 500 keV.

  Thus, by obtaining the well region 20 having the tapered end surface, the shielding effect of the JFET region 7 is promoted by the depletion layer spreading from the vicinity of the apex of the tapered end surface when the silicon carbide MOS transistor 1000 is turned off. The electric field applied to the gate insulating film 30 (FIG. 4) to be turned off is reduced, and the reliability of the silicon carbide MOS transistor 1000 can be improved.

  Further, as described above, the impurity ion implantation is performed so that the ion implantation of the second conductivity type impurity when forming the well region 20 has a profile having a concentration peak in the deep portion of the drift layer 2. In this case, the following effects can be obtained by using the implantation mask 100 having high perpendicularity as shown in FIG.

  In other words, in the implantation mask having low verticality, ion implantation of the second conductivity type impurity is performed through the tapered portion on the side surface of the implantation mask 100, and the region having a high impurity concentration reaches a relatively shallow portion of the well region 20. It will be. As a result, the conductivity of the channel cannot be increased and the threshold voltage is low and a low channel resistance cannot be realized. Silicon carbide MOS transistor 1000 that can be formed in a deep portion, has improved channel conductivity, has a low threshold voltage, and low channel resistance can be realized.

  Next, after removing the implantation mask 100, in the step shown in FIG. 9, a resist material is applied on the main surface of the drift layer 2 and patterned by photolithography to correspond to the source extension region 10 and the JFET extension region 11. An implantation mask 101 having an opening narrower than the portion to be formed and covering a portion of the well region 20 that will later become a channel region with a width wider than the channel length is formed. The planar view shapes of the implantation mask 101 and the implantation mask 102 formed later will be described later.

  Next, in the step shown in FIG. 10, the implantation mask 101 is isotropically etched by an etching process in a gas phase using oxygen plasma or an etching process in a liquid phase using an organic solvent such as acetone. An implantation mask 102 having a width (the same length as the channel length) is formed. The channel length to be formed later is determined by the width of the implantation mask 102.

  The implantation mask 102 is preferably formed only on the surface of the well region 20 and is not formed on the surface of the drift layer 2 beyond the end of the well region 20. By doing so, a channel region to be formed later can be limited to the inside of the well region 20.

  Note that the implantation mask 102 may be formed by dry etching other than the etching process in the gas phase by oxygen plasma, or by wet etching other than the etching process in the liquid phase by an organic solvent such as acetone. Any isotropic etching may be used.

  When the width of the implantation mask 101 is a resolution limit width in photolithography, the width of the implantation mask 102 obtained by isotropic etching of the implantation mask 101 is larger than the resolution limit width in photolithography. Therefore, the channel length can be reduced and low channel resistance can be achieved. Further, since the channel length can be easily reduced, the cost can be reduced.

  Next, in the step shown in FIG. 11, the first conductivity type impurity is ion-implanted using the implantation mask 102 to simultaneously form the first conductivity type source extension region 10 and the JFET extension region 11.

The depths of the source extension region 10 and the JFET extension region 11 are set such that their bottom surfaces do not exceed the bottom surface of the well region 20, and the impurity concentration of the first conductivity type is the first concentration near the surface of the well region 20. It exceeds the impurity concentration of the two conductivity type, and is set to a value in the range of 5 × 10 ¹⁶ cm ⁻³ to 1 × 10 ¹⁸ cm ⁻³ , for example. That is, the entire region is set to a value that is not depleted when silicon carbide MOS transistor 1000 is not operating.

  Further, at the time of the ion implantation, ion implantation is performed with an acceleration energy such that the source extension region 10 and the JFET extension region 11 are not connected to each other by lateral scattering in the well region 20, for example, an acceleration energy within a range of 30 keV to 180 keV. Is done.

  Further, the impurity distribution in the depth direction of the source extension region 10 and the JFET extension region 11 may be a uniform distribution, or a distribution in which the concentration is low on the surface side and becomes higher as the depth increases. Also good. In particular, when the latter distribution is adopted, in the MOS structure formed by the gate insulating film 30 and the gate electrode 35, the deterioration of the quality of the gate insulating film 30 due to the influence of surface-side crystal defects due to ion implantation is suppressed. And a high-quality MOS structure can be realized.

  The source extension region 10 is formed only inside the well region 20, and the JFET extension region 11 is formed in the drift layer 2 between the two well regions 20 that face each other, and the two well regions 20 that face each other. It is formed so as to include the end portion.

  Here, the distance L1 between the source extension region 10 and the JFET extension region 11 corresponds to the channel length of the silicon carbide MOS transistor, but this is substantially determined by the width of the implantation mask 102. Conventionally, the channel length is determined by two photolithography and implantation processes. However, according to the manufacturing method of the present invention, the uniformity of the channel length within the chip and within the wafer is remarkably excellent, and the electrical characteristics are improved. A device with small variation can be obtained.

  Next, although not shown, a resist material is applied on the main surface of the drift layer 2 (or a silicon oxide film is formed), and is patterned by photolithography (and etching) to form a JTE region 50 (FIG. 3). An implantation mask having an opening corresponding to the portion is formed, and second conductivity type impurity ions are implanted using the implantation mask to form the JTE region 50.

  Next, in the step shown in FIG. 12, a resist material is applied or a silicon oxide film is formed on the main surface of the drift layer 2 and patterned by photolithography to form the source region 12 and the field stop region 13 (FIG. 3). An implantation mask 110 having an opening corresponding to the corresponding portion is formed, and ion implantation of a first conductivity type impurity is performed using the implantation mask to form the source region 12 and the field stop region 13 (FIG. 3).

Here, the depth of the source region 12 is set so that the bottom surface thereof does not exceed the bottom surface of the well region 20, and the value of the impurity concentration of the first conductivity type exceeds the value of the impurity concentration of the well region 20. For example, it is set in the range of 1 × 10 ¹⁷ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ . The same applies to the field stop region 13.

  Subsequently, after removing the implantation mask 110, in the step shown in FIG. 13, a resist material is applied on the main surface of the drift layer 2 (or a silicon oxide film is formed) and patterned by photolithography (and etching). Then, an implantation mask 111 having an opening corresponding to the well contact region 21 is formed, ion implantation of a second conductivity type impurity is performed using the implantation mask, and the well contact region 21 is formed in the well region 20. Form.

  The well contact region 21 is a region for realizing good metal contact between the well region 20 and the source pad 41 (FIG. 3), and is formed to have an impurity concentration higher than that of the well region 20. .

  This ion implantation is preferably performed at a substrate temperature of 150 ° C. or higher. By setting such a temperature, a second conductivity type region having a low sheet resistance is formed.

  Further, the termination low resistance region 28 (FIG. 3) may be formed in the surface of the termination well region 27 (FIG. 3) simultaneously with the well contact region 21. In this way, good metal contact with the source pad 41 (FIG. 3) can be realized, and parasitic resistance in the termination well region 27 can be reduced. For example, dV / dt (time t of the drain voltage V) It is possible to make the structure excellent in resistance.

  Needless to say, the termination low resistance region 28 may not be formed simultaneously with the well contact region 21.

  Through the above steps, the source extension region 10, the JFET extension region 11, the source region 12, and the well contact region 21 are obtained as shown in FIG.

  Immediately after this, or somewhere in the previous implantation step, or before the previous implantation step, the first conductivity type impurity is ion-implanted into the entire surface of the drift layer 2, as shown in FIG. In addition, the first conductivity type current control layer 8 having an impurity concentration higher than that of the drift layer 2 may be formed.

  The current control layer 8 has an impurity concentration higher than that of the drift layer 2 below the JFET region 7 and the well region 20, and can reduce the resistance of the JFET region 7. Therefore, there is an effect of reducing the on-resistance of silicon carbide MOS transistor 1000, and the avalanche breakdown between well region 20 and drift layer 2 when reverse bias is applied to silicon carbide MOS transistor 1000 is reduced with well region 20. By causing it to occur at the pn junction formed by the current control layer 8, there is also an effect of causing avalanche breakdown more stably.

For example, the impurity concentration of the current control layer 8 is lower than the maximum concentration of the second conductivity type impurity in the well region 20 and higher than the concentration of the first conductivity type impurity in the drift layer 2, for example. It is set in the range of 1 × 10 ¹⁶ cm ⁻³ to 1 × 10 ¹⁸ cm ⁻³ . It should be noted that the concentration distribution in the depth direction may be uniform or not uniform.

  The current control layer 8 may be formed by epitaxial growth on the drift layer 2 before the well region 20 is formed.

  Thereafter, the implanted impurities are subjected to heat treatment in an inert gas atmosphere such as argon or nitrogen, or in a vacuum at a temperature in the range of 1500 ° C. to 2200 ° C. for a time in the range of 0.5 to 60 minutes. Is activated electrically. This heat treatment may be performed in a state where the surface of the drift layer 2 or the surface of the drift layer 2 and the back surface and end surface of the semiconductor substrate 1 are covered with a film containing carbon. By doing so, it is possible to prevent the surface of the drift layer 2 from being exposed by etching due to residual moisture or residual oxygen in the process apparatus during the heat treatment, and to prevent the surface of the drift layer 2 from being roughened.

  Next, after a silicon oxide film is formed on the entire surface of the drift layer 2 by thermal oxidation, the silicon oxide film is removed by hydrofluoric acid, thereby removing the surface alteration layer on the drift layer 2 and obtaining a clean surface. After that, a silicon oxide film is deposited on the entire surface of the drift layer 2 by a CVD (chemical vapor deposition) method or the like, and is patterned so that only the active region AR (FIG. 2) becomes an opening. A field oxide film 31 is formed to cover the region other than FIG. The film thickness of the field oxide film 31 is 0.5 μm to 2 μm.

Next, in the step shown in FIG. 16, after a silicon oxide film is formed on the drift layer 2 by, for example, thermal oxidation or CVD, a nitrided oxidizing gas atmosphere such as NO or N ₂ O is formed on the silicon oxide film. The gate insulating film 30 is formed by heat treatment in an ammonia atmosphere and heat treatment in an inert gas such as argon.

  Next, a polysilicon layer serving as a gate electrode material is deposited on the gate insulating film 30 and the field oxide film 31 (FIG. 3) by, for example, the CVD method, and a resist material is applied on the polysilicon layer to perform photo processing. Patterning is performed by lithography to form an etching mask 120 having openings other than the gate electrode formation region (FIG. 17). Then, the gate electrode 35 is patterned by etching the polysilicon layer using the etching mask 120.

  In the above process, the gate electrode 35 is not formed immediately above the source region 12. In other words, in order to reduce the on-resistance of silicon carbide MOS transistor 1000, source region 12 and ohmic electrode 40 to be formed later need to have a low contact resistance. It is necessary to increase the conductivity type impurity concentration.

  On the other hand, when a MOS structure composed of the gate electrode 35 and the gate insulating film 30 is formed on the surface of the semiconductor layer having a high impurity concentration formed by ion implantation, the gate insulating film 30 formed on the surface of the semiconductor layer has a good quality. Therefore, there is a high possibility that problems such as an increase in gate leakage current from the gate electrode 35 occur. Therefore, even if the gate insulating film 30 is formed immediately above the source region 12, the gate electrode 35 is not formed. The upper portion of the source region 12 is preferably connected to the ohmic electrode 40 or an interlayer insulating film 32 formed later.

  The polysilicon layer preferably contains phosphorus or boron and has a low sheet resistance. Phosphorus and boron may be taken in during the formation of the polysilicon layer, or may be introduced by ion implantation and activated by a subsequent heat treatment. The gate electrode 35 may be a multilayer film of polysilicon, metal, and intermetallic compound.

  Next, after removing the etching mask 120, a silicon oxide film is deposited on the entire surface of the drift layer 2 by the CVD method or the like in the step shown in FIG.

  Thereafter, in the step shown in FIG. 19, the source contact hole SC reaching the source region 12 and the well contact region 21 and the well contact hole WC reaching the terminal low resistance region 28 (FIG. 4) are formed by, for example, dry etching. . Here, a gate contact hole GC (FIG. 4) reaching the gate electrode 35 (FIG. 4) on the terminal low resistance region 28 may be formed simultaneously. By doing so, the process steps can be simplified and the manufacturing cost can be reduced.

  The source contact hole SC is later filled with the source pad 41, and the gate contact hole GC is later filled with the gate wiring 44.

  Next, in the process shown in FIG. 20, a metal film ML is formed on the interlayer insulating film 32 by, for example, sputtering, so that the bottom of the source contact hole SC opened in the interlayer insulating film 32 and the well contact hole WC ( A metal film ML is also formed on the bottom of FIG.

  This metal layer ML will later become the ohmic electrode 40, and is mainly made of nickel (Ni). Thereafter, silicide is formed between the silicon carbide by heat treatment at 600 to 1100 ° C., and the metal film ML remaining on the interlayer insulating film 32 is mixed with nitric acid, sulfuric acid, hydrochloric acid, or a mixture of these and hydrogen peroxide water. By removing by wet etching using a liquid or the like, an ohmic electrode 40 of nickel silicide is formed on the bottom of the source contact hole SC and the bottom of the well contact hole WC as shown in FIG.

  Note that the heat treatment may be performed again after the metal film ML remaining on the interlayer insulating film 32 is removed. Here, an ohmic contact with a lower contact resistance is formed by performing the process at a higher temperature than the previous heat treatment.

  Further, in the process of forming the ohmic electrode 40, a similar metal film ML may be formed on the back surface of the semiconductor substrate 1, and heat treatment may be performed to form the ohmic electrode 42. By forming such an ohmic electrode 42, a good ohmic contact is formed between the silicon carbide semiconductor substrate 1 and the drain electrode 43.

  The ohmic electrode 40 may be composed of the same intermetallic compound (silicide) at any location, but is composed of separate intermetallic compounds suitable for the p-type semiconductor layer and the n-type semiconductor layer. May be.

  That is, it is important for the ohmic electrode 40 to have a sufficiently low ohmic contact resistance with respect to the source region 12 of the first conductivity type in order to reduce the on-resistance of the silicon carbide MOS transistor 1000. The two-conductivity type well contact region 21 also has a low contact resistance for fixing the well region 20 to the ground potential and improving the forward characteristics of the body diode incorporated in the silicon carbide MOS transistor 1000. Is required.

  For example, an intermetallic compound of nickel and silicon is suitable for an n-type semiconductor layer, and an intermetallic compound of titanium, aluminum, and silicon is suitable for a p-type semiconductor layer.

  As described above, in order to change the material of the ohmic electrode 40 between the source region 12 of the first conductivity type and the well contact region 21 of the second conductivity type, after patterning a suitable metal film on each of them, By applying heat treatment to both simultaneously, different silicides can be formed.

  As described above, when the gate contact hole GC (FIG. 4) is formed simultaneously with the formation of the source contact hole SC and the well contact hole WC (FIG. 4), the bottom surface of the gate contact hole GC is formed. In the case where the exposed gate electrode 35 is polysilicon, silicide is also formed on the bottom surface of the gate contact hole GC.

  When the gate contact hole GC is separately formed, the silicide is not formed on the bottom surface of the gate contact hole GC because the gate contact hole GC is formed by photolithography and etching after the ohmic electrode 40 is formed.

  Next, on the interlayer insulating film 32, Al, Ag (silver), Cu (copper), Ti (titanium), Ni (nickel), Mo (molybdenum), W (tungsten), Ta (tantalum), and nitriding thereof A wiring metal composed of a material, a laminated film, and an alloy thereof is formed by sputtering or vapor deposition, followed by patterning, whereby gate wiring 44 (FIG. 4), gate pad 45 (FIG. 1), source pad 41 is formed.

  Further, by forming a drain electrode 43 by forming a metal film such as Ti, Ni, Ag and Au (gold) on the ohmic electrode 42 on the back surface of the semiconductor substrate 1, the silicon carbide MOS transistor 1000 shown in FIG. Is completed.

  Although not shown, the surface side may be covered with a protective film such as a silicon nitride film or polyimide. They are opened at appropriate positions of the gate pad 45 and the source pad 41, and can be connected to an external control circuit.

<Planar shape of implantation masks 101 and 102>
Next, the planar view shapes of the implantation masks 101 and 102 formed in the steps shown in FIGS. 9 and 10 will be described.

  23 to 25 are diagrams showing the shape of one corner portion of the impurity region in the plan view of the unit cell as shown in FIG.

  When the plan view of the first and second impurity diffusion layers disclosed in Patent Document 1 is applied to the structure of the present invention, the corner portions of the JFET extension region 11 and the source extension region 10 are perpendicular to each other as shown in FIG. Become. In this case, when silicon carbide MOS transistor 1000 is turned on, current from the vicinity of the corner portion of JFET extension region 11 flows into the corner portion of source extension region 10 to cause current concentration. This path is longer than the original channel length L1, and it cannot be said that the channel length is uniform within the unit cell.

  In general, when an implantation mask is made of a photoresist by photolithography using ultraviolet light or the like, the intensity decreases due to the light diffraction phenomenon at the corner of the pattern. It is known that the resist pattern to be rounded at the corners.

  Therefore, even if an attempt is made to form a right-angled corner as shown in FIG. 23, actually, as shown in FIG. 24, the corner of the JFET extension region 11 has a radius of curvature r1 whose center is F1. The corner portion of the source extension region 10 has a radius of curvature r1 with the center being F0.

  Here, the radius of curvature r1 varies depending on the exposure apparatus used for photolithography, the wavelength of the light source, the type of photoresist, the photosensitivity, the film thickness, and the like. FIG. 26 and FIG. 27 show the calculation results of the influence of this finite radius of curvature on the channel width in the unit cell of the MOS transistor.

  FIG. 26 shows a case where the cell pitch (μm) of the unit cell is changed when the unit cell has a square shape in plan view and the channel length (L1) is 0.5 μm and the JFET length (L2) is 2 μm. It is a figure which shows the ratio (%) of the round part which occupies for the channel width of a unit cell about the case where the curvature radius of a round part is changed with 0.2 micrometer, 0.5 micrometer, 0.7 micrometer, and 1.0 micrometer.

  FIG. 27 also shows that when the planar shape of the unit cell is a regular hexagon, the cell pitch (μm) of the unit cell is changed when the channel length (L1) is 0.5 μm and the JFET length (L2) is 2 μm. It is a figure which shows the ratio (%) of the round part which occupies for the channel width of the unit cell at the time of changing the curvature radius of a round part with 0.2 micrometer, 0.5 micrometer, 0.7 micrometer, and 1.0 micrometer. .

  The cell pitch is the distance between the centers of the unit cells. In the above, the JFET length (L2) is fixed to 2 μm, so reducing the cell pitch means that each unit cell is made smaller overall. It means that. If the unit cell becomes smaller as a whole, the proportion of the round part in the channel width also increases.

  From FIG. 26 and FIG. 27, it can be seen that the ratio of the round portion increases as the cell pitch is reduced by miniaturization regardless of whether the unit cell is square or regular hexagon, and this is more remarkable as the radius of curvature of the corner portion increases. I know that there is.

  When the inventors actually patterned the photoresist using an i-line stepper, the curvature radius was found to be 0.5 to 0.7 μm.

  For example, when the cell pitch is reduced to about 8 μm, around 20% of the channel width becomes a round portion, which affects the channel resistance to a degree that cannot be ignored. In particular, in the case of a MOS transistor using a silicon carbide substrate, a channel resistance is larger than that of a MOS transistor using a silicon substrate, so that a significant difference appears as an on-resistance. Needless to say, the larger the ratio of the round portion, the larger the variation in the on-current distribution.

  Therefore, in silicon carbide MOS transistor 1000 of the first embodiment according to the present invention, as shown in FIG. 25, the corner portions of source extension region 10 and JFET extension region 11 have a common center of curvature radius F2, and the curvature is the same. Manufacturing is performed so that r2−r1 = L1 is satisfied with the radii r1 and r2.

  As a result, the channel length in the unit cell is constant in all portions including the corner portion, the on-current distribution is made uniform, and a MOS transistor exhibiting desired characteristics can be obtained.

  Next, an example of the implantation mask 102 formed by etching the implantation mask 101 formed in the step shown in FIG. 9 will be described with reference to FIGS.

  FIG. 28 shows an electron microscope image of the corner portion of the implantation mask 101 made of a photoresist formed by performing photolithography using a chrome mask having a corner portion having a right angle, that is, a corner portion having no curvature. ing.

  FIG. 29 shows an electron microscope image of a corner portion of the implantation mask 102 obtained by reducing the implantation mask 101 of FIG. 28 by oxygen plasma etching.

  It can be seen from FIG. 29 that the shape of the photoresist after the oxygen plasma etching does not reflect isotropic etching due to the geometrical and steric effects of the photoresist.

  Specifically, the radius of curvature is reduced on the JFET extension region 11 side, that is, the outer corner portion of the implantation mask 102, and the curvature radius is increased on the source extension region 10 side, that is, the inner corner portion of the implantation mask 102. As a result, the nonuniformity of the channel length in the corner portion is enlarged.

  In FIG. 29, the straight portion has a resist width of 0.6 μm, but the corner portion has a maximum of 1.2 μm in the diagonal direction.

  Therefore, in the present invention, the source extension region 10 side, that is, the inside of the implantation mask 101 is set to have a radius of curvature larger than the minimum curvature radius generated by photolithography, and the curvature radius outside the JFET extension region 11 side, that is, outside the implantation mask 101 is set. Then, resist patterning is performed by photolithography using a chromium mask in which the resist width is added to the inside radius of curvature and the inside and the center are aligned.

  Thereafter, an implantation mask 102 is formed by oxygen plasma etching, and electron microscope images of the implantation mask 102 are shown in FIGS. FIG. 30 shows an implantation mask 102 obtained by a chrome mask having a right corner, and FIG. 31 shows a curvature of 0.5 μm on the source extension region 10 side, that is, on the inside of the corner portion, and on the JFET extension region 11 side. FIG. 32 shows the implantation mask 102 obtained by the chromium mask having a radius common to the inside and the center and having a curvature radius obtained by adding 0.5 μm to the resist pattern width of the straight line portion. It is obtained by a chromium mask in which the radius of curvature on the inside of the corner is 1.0 μm, the radius of curvature on the JFET extension region 11 side is common to the inside and the center, and the radius of curvature is 1.5 μm added to the resist pattern width of the straight portion. An implantation mask 102 is shown.

  From FIG. 31 and FIG. 32, the implantation mask 101 is formed by photolithography using a chromium mask whose inner corner portion is, for example, 0.5 μm or more, and isotropically etched, so that the inner and outer corner portions are formed. It can be seen that the etching proceeds isotropically, and the implantation mask 102 having a uniform width is formed in all portions. As a result, by ion implantation using this implantation mask 102, a channel region having a uniform channel length is obtained in all portions in the unit cell.

  Next, a plan view of the well region 20 and the JFET extension region 11 will be described. FIG. 33 and FIG. 34 are diagrams showing a plurality of adjacent unit cells corresponding to the planar configuration of the unit cell shown in FIG. 4 taken along line EE, and FIG. 33 shows a square unit cell. FIG. 34 shows an example in which cell pitches are arranged at the same intervals at the same intervals as the adjacent arrangements, and FIG. 34 shows that the square unit cells are staggered with a half-cycle shift from the adjacent cell pitches evenly spaced. An example of such an arrangement is shown.

  Generally, in a vertical MOS transistor having a cell structure, the shorter the separation distance (L2) between adjacent well regions 20, the more the electric field applied to the gate insulating film in the MOS structure existing on the JFET region 7 when the transistor is turned off. Can be reduced.

  However, as shown in FIG. 33 and FIG. 34 as the diagonal dimension L3, there is a portion that is longer than the design dimension L2 as the original JFET length in the diagonal direction of the unit cell.

  The longer the diagonal dimension L3 is, the less desirable from the viewpoint of device reliability. However, in order to make the diagonal dimension L3 as short as possible, the corners of each well region 20 are preferably close to a right angle.

  However, as explained so far, the actual pattern is round with a radius of curvature with a corner portion. That is, when the radius of curvature of the outer peripheral portion of the well region 20 is r3, the radius of curvature is the same as the corner portions of the source extension region 10 and the JFET extension region 11 described above with reference to FIG. A round shape that matches the center of r1 and r2 is not preferable because it increases the diagonal dimension L3.

  FIG. 35 shows the curvature radii r1 and r2 of the corner portions of the source extension region 10 and the JFET extension region 11, and the curvature radius r3 of the corner portion of the outer peripheral portion of the well region 20 together. Thus, by setting r3 to be smaller than r2 or even r1, the electric field applied to the gate insulating film on the JFET region 7 when the reverse bias is applied when the transistor is turned off is relaxed, and the reliability of the transistor is improved. Can be improved.

<Effect>
According to silicon carbide MOS transistor 1000 according to the first embodiment described above, channel length L1 is defined by the distance between source extension region 10 and JFET extension region 11 provided in the surface of well region 20. In the configuration including the channel region, in the plan view shape of the source extension region 10 and the JFET extension region 11, the curvature radius of the corner portion on the JFET extension region 11 side is r2, and the curvature radius of the corner portion on the source extension region 10 side is r1, the centers of curvature radii r1 and r2 are made common, and the channel region is formed so that r2−r1 = L1, so that the channel length in the unit cell is constant in all parts including the corner part, Uniform on-current distribution Te, it is possible to obtain a MOS transistor having a high reliability which indicates the desired characteristics.

  In silicon carbide MOS transistor 1000 according to the first embodiment, the configuration in which gate electrode 35 does not exist immediately above source region 12 can suppress an increase in gate leakage current from gate electrode 35.

  Further, since the impurity concentration of the first conductivity type in the source extension region 10 and the JFET extension region 11 is lower than the impurity concentration of the first conductivity type in the source region 12 at least near the surface, the impurity concentration on the source extension region 10 and the JFET extension. The reliability of the gate insulating film 30 in the MOS structure on the region 11 is improved.

  In silicon carbide MOS transistor 1000 according to the first embodiment, source extension region 10 and JFET extension region 11 are formed at the same time, and the channel region is also determined at that time, but the width of implantation mask 102 that determines the channel region Since it can be made smaller than the resolution limit in photolithography, the channel resistance can be reduced by reducing the channel length.

  In silicon carbide MOS transistor 1000 according to the first embodiment, the curvature radius of the corner portion of the outer peripheral portion of well region 20 is set to r3, and the curvature of each corner portion of source extension region 10 and JFET extension region 11 is set. By making it smaller than the radii r1 and r2, the electric field applied to the gate insulating film on the JFET region 7 when the reverse bias is applied when the transistor is turned off can be relaxed, and the reliability of the transistor can be improved. .

<Embodiment 2>
<Device configuration>
Next, characteristics of silicon carbide MOS transistor 2000 according to the second embodiment of the present invention will be described using FIG.

  36 is a diagram showing a cross-sectional configuration of silicon carbide MOS transistor 2000, and is a diagram corresponding to the cross-sectional configuration of silicon carbide MOS transistor 1000 shown in FIG. 22 is different from silicon carbide MOS transistor 1000 shown in FIG. 22 in that second conductivity type source pocket region 51 and JFET pocket region 52 are formed so as to surround source extension region 14 and JFET extension region 15, respectively. In order to electrically connect the JFET extension region 15 and the JFET region 7, the first conductivity provided so as to penetrate the JFET pocket region 52 from the central portion of the JFET extension region 15 to the drift layer 2 immediately below. It is a point provided with a current control region 9 (first current control region) of a mold.

  Note that the source extension region 14 and the JFET extension region 15 are substantially the same as the source extension region 10 and the JFET extension region 11 shown in FIG. 22, and the source extension region 14 provided in the surface of the well region 20. In a configuration including a channel region in which the channel length L1 is defined by a distance from the JFET extension region 15, the curvature of the corner portion on the JFET extension region 15 side in the plan view shape of the source extension region 14 and the JFET extension region 15 The radius is r2, the radius of curvature of the corner portion on the source extension region 14 side is r1, the centers of the curvature radii r1 and r2 are common, and the channel region is formed so that r2−r1 = L1. As a result, the channel length in the unit cell is constant in all parts including the corner part, the on-current distribution is made uniform, and a highly reliable MOS transistor having desired characteristics is obtained. This is the same as silicon carbide MOS transistor 1000.

  In addition to the above effects, silicon carbide MOS transistor 2000 has JFET pocket region 52, so that the growth of a depletion layer extending from JFET extension region 15 and source extension region 14 to the channel region can be suppressed, and even at a shorter channel length. An increase in leakage current and a decrease in threshold voltage can be suppressed, and the effect of contributing to a reduction in on-resistance by promoting a reduction in channel and cell pitch is achieved.

  Here, the current control region 9 of the first conductivity type is provided in order to prevent the JFET extension region 15 and the JFET region 7 from being disconnected by the JFET pocket region 52 and to prevent an increase in resistance of the JFET region 7. ing. The current control region 9 may be formed so as to be in contact with the well region 20.

<Manufacturing method>
Next, a method for manufacturing silicon carbide MOS transistor 2000 will be described with reference to FIGS. Since it is basically the same as the method for manufacturing silicon carbide MOS transistor 1000 of the first embodiment, the description of the overlapping steps is omitted.

  After the steps described with reference to FIGS. 8 to 10 in the first embodiment, in the step shown in FIG. 37, ion implantation of the first conductivity type impurity is performed using the implantation mask 102, and the first conductivity type source is obtained. The extension region 14 and the JFET extension region 15 are formed simultaneously.

  The conditions for forming the source extension region 14 and the JFET extension region 15 are the same as the conditions for forming the source extension region 10 and the JFET extension region 11.

  Next, in the step shown in FIG. 38, the implantation mask 102 is isotropically etched by etching in a gas phase using oxygen plasma to form an implantation mask 103 having a desired width.

  Then, ion implantation of the second conductivity type impurity is performed using the implantation mask 103 to form the second conductivity type source pocket region 51 and the JFET pocket region 52 around the source extension region 14 and the JFET extension region 15, respectively. To do.

  The depths of the source pocket region 51 and the JFET pocket region 52 are set so that their bottom surfaces exceed the bottom surfaces of the source extension region 14 and the JFET extension region 15.

  In this step, the source mask region 51 and the JFET pocket region 52 may be formed by utilizing the lateral scattering in the ion implantation without reducing the implantation mask 102, oblique ion implantation of impurities, or a substrate. Alternatively, it may be formed by rotational injection (or step rotational injection) performed while tilting and rotating.

  Next, after removing the implantation mask 103, in the step shown in FIG. 39, a resist material is applied on the main surface of the drift layer 2 (or a silicon oxide film is formed) and patterned by photolithography (and etching). Then, an implantation mask 104 having an opening corresponding to the current control region 9 is formed, and ions of a first conductivity type impurity are implanted using the implantation mask, and a drift layer is formed from the bottom surface of the JFET extension region 15. 2, the current control region 9 is formed.

  The depth of the current control region 9 is set so as to reach the drift layer 2 beyond the bottom surface of the JFET pocket region 52 but shallower than the bottom surface of the well region 20. The impurity concentration of the first conductivity type is set higher than the impurity concentration of the second conductivity type in the JFET pocket region 52.

  After the current control region 9 is formed, the configuration shown in FIG. 36 is obtained through steps similar to those described with reference to FIGS.

  Here, FIG. 40 shows the shape of one corner portion of the impurity region in plan view of the unit cell. The radius of curvature r1 centered on F2 of the corner portion of the source extension region 14 and the JFET extension region 15 and r2 and the radius of curvature r3 of the corner portion of the outer peripheral portion of the well region 20 are shown together.

  Since the JFET pocket region 52 is formed using the implantation mask 103 reduced by isotropic oxygen plasma etching, the distance from the end of the source extension region 14 to the end of the source pocket region 51, and the JFET extension The distance from the end of the region 15 to the end of the JFET pocket region 52 is equal in all parts in the unit cell, and the channel length in the unit cell is constant in all parts including the corner part, A MOS transistor exhibiting desired characteristics can be obtained with uniform on-current distribution.

  Further, by setting the radius of curvature r3 of the corner portion of the outer peripheral portion of the well region 20 to be smaller than r2 or r1, it is applied to the gate insulating film on the JFET region 7 when a reverse bias is applied when the transistor is turned off. Thus, the reliability of the transistor can be improved.

  FIG. 41 is a diagram corresponding to the plane configuration along the line GG shown in FIG. 36, showing a plurality of adjacent unit cells, and FIG. 40 is a diagram showing square unit cells at equal intervals and cell pitches. Shows an example in which are arranged at the same cycle as the adjacent arrangement.

  In FIG. 41, the corner portion of the well region 20 is rounded as shown in the first embodiment, but the corner portion of the current control region 9 is also rounded. As shown in FIG. 41, the current control region 9 has a constant distance from the end of the well region 20 so that the corners of the current control region 9 are different from the radius of curvature of the well region 20 but the center is the same. Also good. Although not shown, the radius of curvature of the corner portion of the current control region 9 is the same as that of the corner portion of the well region 20, but the center may be different.

<Effect>
According to silicon carbide MOS transistor 2000 according to the second embodiment described above, source pocket region 51 and JFET pocket region 52 are formed in a self-aligned manner around source extension region 14 and JFET extension region 15, respectively. , The extension of the depletion layer from the JFET extension region 15 and the source extension region 14 to the channel region can be suppressed, and an increase in leakage current and a decrease in threshold voltage can be suppressed even with a shorter channel length. It is possible to reduce the on-resistance by channeling or shortening the cell pitch.

  Furthermore, since a part of the bottom surface of the JFET extension region 15 is covered with the second conductivity type JFET pocket region 52, the gate insulating film on the JFET region 7 is applied when a reverse bias is applied to the silicon carbide MOS transistor 2000. The reliability of silicon carbide MOS transistor 2000 that can relax the electric field applied to transistor 30 can be improved.

<Embodiment 3>
<Device configuration>
Next, characteristics of silicon carbide MOS transistor 3000 according to the third embodiment of the present invention will be described with reference to FIG.

  FIG. 42 shows a cross-sectional configuration of silicon carbide MOS transistor 3000, and is a diagram corresponding to a cross-sectional configuration of silicon carbide MOS transistor 1000 shown in FIG.

  22 is different from silicon carbide MOS transistor 1000 shown in FIG. 22 in that second conductivity type source pocket region 51 and JFET pocket region 52 are formed so as to surround source extension region 14 and JFET extension region 15, respectively. In order to electrically connect the JFET extension region 15 and the JFET region 7, the first conductivity provided so as to penetrate the JFET pocket region 52 from the central portion of the JFET extension region 15 to the drift layer 2 immediately below. And a current control region 120 (second current control region) in contact with the source extension region 14 and the source region 12 inside the well region 20. Is a point. The current control region 9 may be formed so as to be in contact with the well region 20.

  The source extension region 14 and the JFET extension region 15 are substantially the same as the source extension region 10 and the JFET extension region 11 shown in FIG. 22, and the source extension region 14 and the JFET extension provided in the surface of the well region 20. In the configuration including the channel region in which the channel length L1 is defined by the distance to the region 15, the curvature radius of the corner portion on the JFET extension region 15 side in the plan view shape of the source extension region 14 and the JFET extension region 15 is set. The channel region is formed such that r2 is r2, the radius of curvature of the corner portion on the source extension region 14 side is r1, the centers of the curvature radii r1 and r2 are the same, and r2-r1 = L1. The structure and effect that the channel length in the unit cell is constant in all parts including the corner portion, the on-current distribution is uniformed, and a highly reliable MOS transistor exhibiting desired characteristics is obtained. This is the same as the silicon MOS transistor 1000.

  In addition to the above effects, silicon carbide MOS transistor 3000 has JFET pocket region 52, so that the extension of the depletion layer extending from JFET extension region 15 and source extension region 14 to the channel region is suppressed, and even at a shorter channel length. An increase in leakage current and a decrease in threshold voltage can be suppressed, and the effect of contributing to a reduction in on-resistance by promoting a reduction in channel and cell pitch is achieved.

  Since the current control layer 9 and the current control layer 120 are formed in a self-aligned manner, the length from the end of the current control region 9 to the end of the JFET extension region 15 is equal in all parts of the unit cell. There is an effect that the current distribution is made uniform and the reliability of silicon carbide MOS transistor 3000 is improved.

  In addition, by providing the current control region 120, the parasitic resistance of the source extension 14 and the source region 12 can be reduced, and consequently the on-resistance of the silicon carbide MOS transistor 3000 can be reduced.

<Manufacturing method>
Next, a method for manufacturing silicon carbide MOS transistor 3000 will be described with reference to FIGS. Since it is basically the same as the method for manufacturing silicon carbide MOS transistor 1000 of the first embodiment, the description of the overlapping steps is omitted.

  After the steps described with reference to FIGS. 8 to 10 in the first embodiment, in the step shown in FIG. 43, ion implantation of the first conductivity type impurity is performed using the implantation mask 102 and the first conductivity type source is obtained. The extension region 14 and the JFET extension region 15 are formed simultaneously.

  The conditions for forming the source extension region 14 and the JFET extension region 15 are the same as the conditions for forming the source extension region 10 and the JFET extension region 11.

  Next, as described with reference to FIG. 38, the implantation mask 102 is isotropically etched by an etching process in a gas phase using oxygen plasma to form an implantation mask 103 having a desired width. In this case, the etching conditions are set so that the width of the implantation mask 103 is smaller than the channel length.

  Then, ion implantation of the first conductivity type impurity is performed using the implantation mask 103, ion implantation of the first conductivity type impurity is performed, and the second conductivity type is formed around the source extension region 14 and the JFET extension region 15, respectively. Source pocket region 51 and JFET pocket region 52 are formed.

  The depths of the source pocket region 51 and the JFET pocket region 52 are set so that their bottom surfaces exceed the bottom surfaces of the source extension region 14 and the JFET extension region 15.

  Thereafter, in the step shown in FIG. 44, a silicon oxide film is formed on the entire surface of the drift layer 2 in a state where the implantation mask 103 is formed by, for example, the CVD method, and anisotropic etching is performed around the implantation mask 103. Then, an implantation mask 105 made of a silicon oxide film is formed in a sidewall shape.

  Then, ion implantation of the first conductivity type impurity is performed using the composite mask 106 including the implantation mask 103 and the implantation mask 105, and the first conductivity type current control region 9 is formed in a region not covered with the composite mask 106. And 120 are formed.

  As described above, since the implantation mask 105 is formed by a so-called frame forming method, the distance between the end portion of the implantation mask 103 and the end portion of the implantation mask 105 can be made equal in all portions of the unit cell. Then, the distance from the end portion of the current control layer 9 formed thereafter to the end portion of the JFET extension region 15, that is, the length to the channel region becomes equal in all portions of the unit cell, and the on-current distribution is made uniform. There is an effect.

  The depths of the current control region 9 and the current control region 120 are set so as to exceed the bottom surface of the JFET pocket region 52 and shallower than the bottom surface of the well region 20. The impurity concentration of the first conductivity type is set higher than the impurity concentration of the second conductivity type in the JFET pocket region 52.

  After forming the current control regions 9 and 120, the configuration shown in FIG. 42 is obtained through steps similar to those described with reference to FIGS.

  FIG. 45 is a diagram corresponding to the plane configuration along the line H-H shown in FIG. 42, showing a plurality of adjacent unit cells. FIG. 42 is a diagram showing square unit cells at equal intervals and cell pitches. Shows an example in which are arranged at the same cycle as the adjacent arrangement.

  In FIG. 45, the corner portions of the current control region 9 and the current control region 120 are both round, but since the composite implantation mask 106 is used by framing the implantation mask 103, the radius of curvature of the corner portion of the current control region 9 is used. Is larger than the radius of curvature of the current control region 120.

<Effect>
According to silicon carbide MOS transistor 3000 according to the third embodiment described above, source pocket region 51 and JFET pocket region 52 are formed in a self-aligned manner around source extension region 14 and JFET extension region 15, respectively. , The extension of the depletion layer from the JFET extension region 15 and the source extension region 14 to the channel region can be suppressed, and an increase in leakage current and a decrease in threshold voltage can be suppressed even with a shorter channel length. It is possible to reduce the on-resistance by channeling or shortening the cell pitch.

  Further, since the JFET extension region 15 is partially covered with the second conductivity type JFET pocket region 52, the gate insulating film on the JFET region 7 is applied when a reverse bias is applied to the silicon carbide MOS transistor 2000. The reliability of silicon carbide MOS transistor 2000 that can relax the electric field applied to transistor 30 can be improved.

  In addition, since the current control layer 9 and the current control layer 120 are formed in a self-aligned manner, the length from the end of the current control region 9 to the end of the JFET extension region 15 is equal in all parts of the unit cell. There is an effect that the on-current distribution is made uniform and the reliability of silicon carbide MOS transistor 3000 is improved.

  In addition, by providing the current control region 120, the parasitic resistance of the source extension 14 and the source region 12 can be reduced, and consequently the on-resistance of the silicon carbide MOS transistor 2000 can be reduced.

<Embodiment 4>
<Device configuration>
Next, characteristics of silicon carbide MOS transistor 4000 of the fourth embodiment according to the present invention will be described using FIG.

  46 is a diagram showing a cross-sectional configuration of silicon carbide MOS transistor 4000, and is a diagram of a portion corresponding to the cross-sectional configuration of silicon carbide MOS transistor 1000 shown in FIG.

  22 is different from silicon carbide MOS transistor 1000 shown in FIG. 22 in that the bottom surfaces of source extension region 16 and JFET extension region 17 are partially covered immediately below source extension region 16 and JFET extension region 17, respectively. In order to electrically connect the point where the second conductivity type source pocket region 53 and the JFET pocket region 54 are formed and the JFET extension region 17 and the JFET region 7, a drift immediately below the center of the JFET extension region 15 is provided. A point is that a first conductivity type current control region 9 (first current control region) provided so as to penetrate the JFET pocket region 52 over the layer 2 is provided. The current control region 9 may be formed so as to be in contact with the well region 20.

  The source extension region 16 and the JFET extension region 17 are substantially the same as the source extension region 10 and the JFET extension region 11 shown in FIG. 22, and the source extension region 64 and the JFET extension provided in the surface of the well region 20. In the configuration including the channel region in which the channel length L1 is defined by the distance between the region 17 and the plan view shape of the source extension region 16 and the JFET extension region 17, the curvature radius of the corner portion on the JFET extension region 17 side is set. The channel region is formed such that r2 is r2, the radius of curvature of the corner portion on the source extension region 16 side is r1, the centers of the curvature radii r1 and r2 are common, and r2-r1 = L1. The structure and effect that the channel length in the unit cell is constant in all parts including the corner portion, the on-current distribution is uniformed, and a highly reliable MOS transistor exhibiting desired characteristics is obtained. This is the same as the silicon MOS transistor 1000.

  In addition to the above-described effects, silicon carbide MOS transistor 4000 has a JFET extension region 17 that is partly covered with the second conductivity type JFET pocket region 54, and is therefore reverse to silicon carbide MOS transistor 4000. Since the electric field applied to gate insulating film 30 when bias is applied can be relaxed, the reliability of silicon carbide MOS transistor 4000 can be improved.

<Manufacturing method>
Next, a method for manufacturing silicon carbide MOS transistor 4000 will be described with reference to FIGS. Since it is basically the same as the method for manufacturing silicon carbide MOS transistor 1000 of the first embodiment, the description of the overlapping steps is omitted.

  After the steps described with reference to FIGS. 8 and 9 in the first embodiment, a resist material is applied to the main surface of the drift layer 2 (or a silicon oxide film is formed) in the step shown in FIG. Patterning is performed by lithography (and etching) to form an implantation mask 107 having openings corresponding to the source pocket region 53 and the JFET pocket region 54. Thereafter, ion implantation of a second conductivity type impurity is performed using the implantation mask 107 to simultaneously form the second conductivity type source pocket region 53 and the JFET pocket region 54.

  Next, the implantation mask 107 is isotropically etched by an etching process in a gas phase using oxygen plasma to form an implantation mask 102 having a desired width shown in FIG. The channel length to be formed later is determined by the width of the implantation mask 102.

  Subsequently, the first conductivity type impurity is ion-implanted using the implantation mask 102 to simultaneously form the first conductivity type source extension region 16 and the JFET extension region 17.

  The depths of the source extension region 16 and the JFET extension region 17 are set such that their bottom surfaces do not exceed the bottom surfaces of the source pocket region 53 and the JFET pocket region 54. Further, the source extension region 16 and the JFET extension region 17 are connected to the well region 20 without passing through the source pocket region 53 and the JFET pocket region 54 in the vicinity of the surface where the channel is formed, respectively. The JFET pocket region 54 is formed wider than the size in plan view.

  Next, after removing the implantation mask 102, in the step shown in FIG. 49, a resist material is applied on the main surface of the drift layer 2 (or a silicon oxide film is formed) and patterned by photolithography (and etching). Then, an implantation mask 104 having an opening corresponding to the current control region 9 is formed, and ion implantation of the first conductivity type impurity is performed using the implantation mask, and a drift layer is formed from the bottom surface of the JFET extension region 17. 2, the current control region 9 is formed.

  The depth of the current control region 9 is set so as to reach the drift layer 2 beyond the bottom surface of the JFET pocket region 54 but shallower than the bottom surface of the well region 20. The impurity concentration of the first conductivity type is set higher than the impurity concentration of the second conductivity type in the JFET pocket region 54.

  After the current control region 9 is formed, the configuration shown in FIG. 46 is obtained through steps similar to those described with reference to FIGS.

<Effect>
According to silicon carbide MOS transistor 4000 according to the fourth embodiment described above, source pocket region 53 and JFET pocket region 54 are formed in a self-aligned manner under source extension region 16 and JFET extension region 17, respectively. The electric field applied to the gate insulating film on JFET region 7 at the time of reverse bias application at the time of turn-off of silicon carbide MOS transistor 4000 can be relaxed, and the reliability of silicon carbide MOS transistor 4000 can be improved.

<Embodiment 5>
<Device configuration>
Next, characteristics of silicon carbide MOS transistor 5000 according to the fifth embodiment of the present invention will be described with reference to FIG.

  50 is a diagram showing a cross-sectional configuration of silicon carbide MOS transistor 5000, and is a diagram corresponding to the cross-sectional configuration of silicon carbide MOS transistor 1000 shown in FIG.

  22 is different from silicon carbide MOS transistor 1000 shown in FIG. 22 in that the bottom surfaces of source extension region 16 and JFET extension region 17 are partially covered immediately below source extension region 16 and JFET extension region 17, respectively. In order to electrically connect the JFET extension region 17 and the JFET region 7 to the point where the second conductivity type source pocket region 53 and the JFET pocket region 54 are formed, a drift immediately below the center of the JFET extension region 17 is formed. The first conductivity type current control region 9 (first current control region) provided so as to penetrate the JFET pocket region 54 over the layer 2, and the source extension region 16 and the source in the well region 20 Region 12 and It is that it includes a current control region 120 (second current control region). The current control region 9 may be formed so as to be in contact with the well region 20.

  The source extension region 16 and the JFET extension region 17 are substantially the same as the source extension region 10 and the JFET extension region 11 shown in FIG. 22, and the source extension region 16 and the JFET extension provided in the surface of the well region 20. In the configuration including the channel region in which the channel length L1 is defined by the distance between the region 17 and the plan view shape of the source extension region 16 and the JFET extension region 17, the curvature radius of the corner portion on the JFET extension region 17 side is set. The channel region is formed such that r2 is r2, the radius of curvature of the corner portion on the source extension region 16 side is r1, the centers of the curvature radii r1 and r2 are common, and r2-r1 = L1. The structure and effect that the channel length in the unit cell is constant in all parts including the corner portion, the on-current distribution is uniformed, and a highly reliable MOS transistor exhibiting desired characteristics is obtained. This is the same as the silicon MOS transistor 1000.

  In addition to the above-described effects, silicon carbide MOS transistor 5000 has a JFET extension region 17 that is partly covered with the second conductivity type JFET pocket region 54, and is therefore reverse to silicon carbide MOS transistor 5000. Since the electric field applied to gate insulating film 30 when a bias is applied can be relaxed, the reliability of silicon carbide MOS transistor 5000 can be improved.

  In addition, since the current control layer 9 and the current control layer 120 are formed in a self-aligned manner, the length from the end of the current control region 9 to the end of the JFET extension region 17 is equal in all parts of the unit cell. The ON current distribution is made uniform, and the reliability of the silicon carbide MOS transistor 5000 is improved.

  In addition, by providing the current control region 120, the parasitic resistance of the source extension 16 and the source region 12 can be reduced, and as a result, the on-resistance of the silicon carbide MOS transistor 5000 can be reduced.

<Manufacturing method>
Next, a method for manufacturing silicon carbide MOS transistor 5000 will be described with reference to FIG. Since it is basically the same as the method for manufacturing silicon carbide MOS transistor 1000 of the first embodiment, the description of the overlapping steps is omitted.

  After the step described with reference to FIGS. 47 and 48 in the fourth embodiment, in the step shown in FIG. 51, a silicon oxide film is formed on the entire surface of drift layer 2 in the state where implantation mask 103 is formed by, for example, the CVD method. Then, by performing anisotropic etching, an implantation mask 105 made of a silicon oxide film in a sidewall shape is formed around the implantation mask 102.

  Then, ion implantation of the first conductivity type impurity is performed using the composite mask 108 including the implantation mask 102 and the implantation mask 105, and the first conductivity type current control region 9 is formed in a region not covered with the composite mask 108. And 120 are formed.

  As described above, since the implantation mask 105 is formed by a so-called frame forming method, the distance between the end portion of the implantation mask 102 and the end portion of the implantation mask 105 can be made equal in all portions of the unit cell. Then, the distance from the end portion of the current control layer 9 formed thereafter to the end portion of the JFET extension region 17, that is, the length to the channel region becomes equal in all portions of the unit cell, and the on-current distribution is made uniform. There is an effect.

<Effect>
According to silicon carbide MOS transistor 5000 according to the fifth embodiment described above, source pocket region 53 and JFET pocket region 54 are formed in a self-aligned manner below source extension region 16 and JFET extension region 17, respectively. The electric field applied to the gate insulating film on JFET region 7 when the reverse bias is applied when silicon carbide MOS transistor 5000 is turned off can be relaxed, and the reliability of silicon carbide MOS transistor 5000 can be improved.

  In addition, since the current control layer 9 and the current control layer 120 are formed in a self-aligned manner, the length from the end of the current control region 9 to the end of the JFET extension region 17 is equal in all parts of the unit cell. The ON current distribution is made uniform, and the reliability of the silicon carbide MOS transistor 5000 is improved.

  The manufacturing method described in Embodiments 1 to 5 according to the present invention described above is an example, and the same effect can be obtained even when manufactured by another manufacturing method.

  Embodiments 1 to 5 according to the present invention described above exemplify aspects to which the present invention can be applied, and the present invention is not limited to this. In other words, various modifications and variations to the described aspects can be considered without departing from the scope of the present invention.

  In the present invention, the case where the semiconductor device is a vertical MOS transistor is disclosed. For example, in the silicon carbide MOS transistor 1000 shown in FIG. 4, between the semiconductor substrate 1 and the ohmic electrode 42 on the back surface side. By providing the collector layer of the second conductivity type, the above-described effects of the present invention can be similarly achieved even when a semiconductor device having an IGBT (insulated gate bipolar transistor) cell region is configured. Therefore, it can be said that the range of the scope of the present invention is a semiconductor device as a switching device having a MOS structure such as a MOS transistor or IGBT.

  Further, in the present invention, the semiconductor device itself having the MOS structure described in the first to fifth embodiments is defined as “semiconductor device” in a narrow sense. For example, the semiconductor device is connected to the semiconductor device. A power module itself such as an inverter module that is mounted on a lead frame and sealed together with a freewheel diode connected in antiparallel and a control circuit that generates and applies a gate voltage of the semiconductor device and the like is also a semiconductor device in a broad sense. Is defined.

  1 semiconductor substrate, 2 drift layer, 9,120 current control region, 10, 14, 16 source extension region, 11, 15, 17 JFET extension region, 12 source region, 20 well region, 51, 53 source pocket region, 52, 54 JFET pocket region, 100, 101, 102, 103, 104, 105, 106 Implant mask.

Claims (8)

A first conductivity type semiconductor substrate;
A first conductivity type semiconductor layer disposed on the semiconductor substrate;
A plurality of second-conductivity-type well regions selectively disposed in the upper layer portion of the semiconductor layer;
A source region of a first conductivity type selectively disposed in a surface of the well region;
An extension region of a first conductivity type disposed in the surface of the well region so as to surround the source region in contact with an edge of the source region;
A first conductivity type semiconductor region disposed so as to extend between upper side edge portions of the well regions adjacent to each other,
The channel length of the channel region is defined by the distance between the extension region and the semiconductor region,
The extension region has an arc shape in which a corner portion has a first radius of curvature in a plan view shape thereof,
The semiconductor region, in its plan view shape, to name a circular arc shape having a second radius of curvature corner portion is also the first radius of curvature and the center,
The well region has an arc shape in which a corner portion has a third radius of curvature in a plan view shape thereof,
The semiconductor device, wherein the third radius of curvature is a radius of curvature smaller than the first and second radius of curvature. A first conductivity type semiconductor substrate;
A first conductivity type semiconductor layer disposed on the semiconductor substrate;
A plurality of second-conductivity-type well regions selectively disposed in the upper layer portion of the semiconductor layer;
A source region of a first conductivity type selectively disposed in a surface of the well region;
An extension region of a first conductivity type disposed in the surface of the well region so as to surround the source region in contact with an edge of the source region;
A first conductivity type semiconductor region disposed so as to extend between upper side edge portions of the well regions adjacent to each other,
The channel length of the channel region is defined by the distance between the extension region and the semiconductor region,
The extension region has an arc shape in which a corner portion has a first radius of curvature in a plan view shape thereof,
The semiconductor region has an arc shape in which the corner portion has a second radius of curvature that is the same as the center of the first radius of curvature in the plan view shape;
A first pocket region of a second conductivity type disposed in the surface of the well region and covering the extension region;
A second pocket region of a second conductivity type disposed in the surface of the semiconductor layer and in the surface of the well region and covering the semiconductor region ;
Wherein toward the semiconductor layer immediately below the semiconductor region, and the second of the first current control region of the first conductivity type provided so as to penetrate through the pocket area, Ru further comprising a semi-conductor device. A first conductivity type semiconductor substrate;
A first conductivity type semiconductor layer disposed on the semiconductor substrate;
A plurality of second-conductivity-type well regions selectively disposed in the upper layer portion of the semiconductor layer;
A source region of a first conductivity type selectively disposed in a surface of the well region;
An extension region of a first conductivity type disposed in the surface of the well region so as to surround the source region in contact with an edge of the source region;
A first conductivity type semiconductor region disposed so as to extend between upper side edge portions of the well regions adjacent to each other,
The channel length of the channel region is defined by the distance between the extension region and the semiconductor region,
The extension region has an arc shape in which a corner portion has a first radius of curvature in a plan view shape thereof,
The semiconductor region has an arc shape in which the corner portion has a second radius of curvature that is the same as the center of the first radius of curvature in the plan view shape;
A first pocket region of a second conductivity type disposed immediately below the extension region in the well region and partially covering the bottom surface of the extension region;
A second pocket region of a second conductivity type disposed at least immediately below the semiconductor region in the semiconductor layer and partially covering the bottom surface of the semiconductor region ;
Wherein toward the semiconductor layer immediately below the semiconductor region, and the second of the first current control region of the first conductivity type provided so as to penetrate through the pocket area, Ru further comprising a semi-conductor device. 4. The semiconductor device according to claim 2 , wherein a length from an end portion of the semiconductor region to the first current control region is equal in all portions of one unit of the semiconductor device. 5. The semiconductor device according to claim 4 , further comprising a second current control region of a first conductivity type disposed so as to surround the source region in the well region and in contact with the extension region and the source region . A first conductivity type semiconductor substrate; a first conductivity type semiconductor layer disposed on the semiconductor substrate; and a plurality of second conductivity type well regions selectively disposed on an upper layer portion of the semiconductor layer; A source region of a first conductivity type selectively disposed in the surface of the well region and a surface of the well region so as to surround the source region in contact with an edge of the source region. An extension region of a first conductivity type provided, and a semiconductor region of a first conductivity type disposed so as to extend between edge portions on the upper surface side of the well regions adjacent to each other. A manufacturing method comprising:
(a) preparing the semiconductor substrate;
(b) forming the semiconductor layer on one main surface of the semiconductor substrate;
(c) selectively forming a plurality of the well regions in the upper layer portion of the semiconductor layer;
(d) a first opening that has a narrower opening on the semiconductor layer than a portion corresponding to the extension region and the semiconductor region, and covers a portion that later becomes a channel region in the well region with a width wider than a channel length; Forming an implantation mask;
(e) forming the second implantation mask by isotropically etching the first implantation mask to reduce its width to the channel length;
(f) performing ion implantation of a first conductivity type impurity using the second implantation mask to form the extension region and the semiconductor region;
(g) forming a third implantation mask having an opening corresponding to the source region on the semiconductor layer after removing the second implantation mask;
(h) performing ion implantation of a first conductivity type impurity using the third implantation mask to form the source region, and
The step (d)
The inside of the first implantation mask in the plan view shape is set to a radius of curvature larger than the minimum curvature radius generated by photolithography, and the curvature radius outside the first implantation mask is set to the inside curvature radius. A method for manufacturing a semiconductor device, comprising: a step of patterning the first implantation mask by photolithography using a mask that is added with a width of the implantation mask and having a center aligned with the inside. Between the steps (f) and (g),
(f1) forming the fourth implantation mask by isotropically etching the second implantation mask to reduce its width to be smaller than the channel length;
(f2) The second conductivity type impurity is ion-implanted using the fourth implantation mask to form a second conductivity type first pocket region covering the extension region in the surface of the well region. Forming a second pocket region of a second conductivity type covering the semiconductor region in the surface of the semiconductor layer and in the surface of the well region;
(f3) A silicon oxide film is formed on the entire surface of the semiconductor layer in a state where the fourth implantation mask is formed, and anisotropic etching is performed to form a sidewall-like shape around the fourth implantation mask. Forming a fifth implantation mask;
(f4) Using a sixth implantation mask constituted by the fourth and fifth implantation masks, ion implantation of a first conductivity type impurity is performed, and the second region is formed from the semiconductor region to the semiconductor layer immediately below. The first conductivity type first current control region is formed so as to penetrate the first pocket region, and the first conductivity type is formed so as to penetrate the first pocket region from the extension region to the well region immediately below. The method of manufacturing a semiconductor device according to claim 6, further comprising: forming a second current control region. Between steps (d) and (e),
(d1) Using the first implantation mask, second conductivity type impurity ions are implanted to form a second pocket type first pocket region deeper than the extension region in the surface of the well region. And forming a second conductivity type second pocket region deeper than the semiconductor region extending from the surface of the semiconductor layer to the surface of the well region;
Between the steps (f) and (g),
(f1) A silicon oxide film is formed on the entire surface of the semiconductor layer in a state where the second implantation mask is formed, and anisotropic etching is performed to form a sidewall-like shape around the second implantation mask. Forming a fourth implantation mask;
(f2) Ion implantation of a first conductivity type impurity is performed using a fifth implantation mask composed of the second and fourth implantation masks, and the second region is formed from the semiconductor region to the semiconductor layer immediately below. The first conductivity type first current control region is formed so as to penetrate the first pocket region, and the first conductivity type is formed so as to penetrate the first pocket region from the extension region to the well region immediately below. The method of manufacturing a semiconductor device according to claim 6, further comprising: forming a second current control region.