JP7643621B2 - Semiconductor Device - Google Patents

Description

This invention relates to a semiconductor device.

Conventionally, in power semiconductor elements, vertical MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) with a trench structure have been fabricated (manufactured) to reduce the on-resistance of the element. In vertical MOSFETs, a trench structure in which the channel is formed perpendicular to the substrate surface can increase the cell density per unit area compared to a planar structure in which the channel is formed parallel to the substrate surface, and therefore the current density per unit area can be increased, which is advantageous from a cost perspective.

The trench gate structure is a three-dimensional structure in which a MOS gate (insulated gate made of metal-oxide-semiconductor) is embedded in a trench formed in a semiconductor substrate made of silicon carbide (hereafter referred to as silicon carbide substrate), and the portion along the sidewall of the trench is used as a channel (inversion layer). For this reason, when comparing elements with the same on-resistance (Ron), the trench gate structure can overwhelmingly reduce the element area (chip area) compared to a planar gate structure in which a MOS gate is provided in a flat plate shape on a silicon carbide substrate, making it a promising device structure for the future.

In a trench MOSFET, a trench for a Schottky Barrier Diode (SBD) is formed between adjacent gate trenches, and a Schottky junction is formed on the side of the trench. FIG. 13 is a cross-sectional view showing the configuration of a conventional trench-type silicon carbide semiconductor device with an SBD built in. In FIG. 13, the left side of the omitted dashed line in the center shows the configuration of the active section 21 where the element structure is formed and where current flows when on, and the right side of the omitted dashed line in the center shows the configuration of the gate pad section 20.

As shown in FIG. 13, the conventional trench-type silicon carbide semiconductor device includes, in an active portion 21, a trench-type MOS gate (insulating gate made of metal-oxide film-semiconductor) structure on the front surface of an n-type silicon carbide substrate 1, and a contact trench 19 in which a trench-type SBD is embedded. The active portion 21 is a region that carries a current that flows when the device is on. Specifically, the n-type silicon carbide substrate 1 is formed by epitaxially growing an n-type layer that becomes an n ^- type drift layer 2 on the n ^- type silicon carbide substrate 1 that is a drain layer. A MOS gate structure consisting of a p-type base layer 6, an n ⁺ -type source region 7, a p ⁺ -type contact region 8, a gate insulating film 9, and a gate electrode 10 is provided on the front surface (the surface on the n ^- type drift layer 2 side) of the n-type silicon carbide substrate 1.

A p ⁺ -type base region 3 is provided in order to reduce the electric field applied to the gate insulating film 9 at the bottom of the gate trench 18 and the contact trench 19. A contact trench 19 is provided in the mesa portion to a depth approximately equal to that of the gate trench 18.

The n ⁺ type source region 7 is selectively provided inside the p type base layer 6 between the adjacent gate trenches 18 and contact trenches 19. The n ⁺ type source region 7 and the p type base layer 6 exposed on the inner wall of the contact trench 19 are exposed in a contact hole penetrating the interlayer insulating film 11 in the depth direction. A source electrode pad 14 is provided as a front surface electrode through the contact hole so as to contact the source electrode 13 in ohmic contact with the n ⁺ type source region 7 and the p ⁺ type contact region 8 and the Schottky electrode 15 embedded in the contact trench 19, and contacts the p type base layer 6 and the n ⁺ type source region 7. A drain electrode (not shown) is provided as a back surface electrode on the back surface (the surface opposite to the n ^- type drift layer 2) of the n type silicon carbide substrate 1.

The gate pad section 20 is a section where a gate electrode pad 17 electrically connected to the gate electrode 10 is provided, and no element structures such as a gate trench 18 or a contact trench 19 are formed. As shown in FIG. 13, when on, a current S flows from the drain electrode side to the source electrode 13 side of the active section 21.

In the case of an SBD built into a trench MOSFET having such a structure, the drift region can be shared with the MOSFET, so the chip area can be smaller than the combined chip area of the external SBD and the MOSFET. Also, in the case of an external SBD, when the VF (forward voltage) of the SBD becomes equal to or exceeds the built-in voltage of the body diode formed by the p-type base layer 6 and n ^- type drift layer 2 of the MOSFET, the body diode turns on, and the bipolar action of the body diode causes the characteristics to change over time (deterioration over time), reducing reliability.

On the other hand, with an internal SBD, even if the voltage of the drain of the MOSFET, which corresponds to the cathode of the external SBD, exceeds the built-in voltage of the body diode, the potential difference near the pn junction that constitutes the body diode is low because the voltage is maintained in the drift region, making it difficult for current to flow through the body diode. As a result, even large currents do not flow through the body diode, making it less likely to deteriorate due to bipolar operation.

In addition, a semiconductor device is known in which the element section has a first trench structure having a first buried layer and a plurality of first protective trenches formed deeper than the gate trenches to prevent destruction of the gate pad section, and the gate pad section has a second trench structure having a second buried layer made of a metal layer that forms a Schottky contact and is electrically connected to the source electrode layer (see, for example, Patent Document 1).

International Publication No. 2016/006696

Here, in the gate pad section 20, p-type regions (p ⁺ type base region 3, p-type base layer 6) are usually formed to ensure a breakdown voltage. These p-type regions have a larger area than the p-type region of the active section 21, so a lateral voltage drop occurs due to spreading resistance. As a result, when a pn junction consisting of a p-type region and an n ^- type drift layer is forward biased, minority carriers (holes) are injected, and a current flows through the body diode in the gate pad section 20 even at a relatively small current density. Thus, the body diode in the gate pad section 20 has a problem in that its characteristics change over time due to bipolar operation, decreasing its reliability.

The purpose of this invention is to provide a semiconductor device that can solve the above-mentioned problems by suppressing the lateral voltage drop in the gate pad section, suppressing the injection of minority carriers (holes), and preventing the body diode from turning on even with a large current.

In order to solve the above-mentioned problems and achieve the object of the present invention, the semiconductor device according to the present invention has the following features. The semiconductor device includes a first trench and a second trench extending toward a gate electrode pad in a top view, a source electrode portion at least a part of which is provided above the first trench and the second trench, a gate pad portion including a gate electrode pad, a gate electrode including a first buried portion embedded inside the first trench and a protruding portion provided protruding above the first trench, and a conductive layer including a second buried portion embedded inside the second trench. The source electrode portion includes a first source electrode connection portion provided between the protruding portion and the gate electrode pad in a top view, and a second source electrode connection portion sandwiching the protruding portion between the first source electrode connection portion in a top view. The second trench includes a first source connection trench in which the conductive layer is connected to the first source electrode connection portion.

The semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the first source connection trench extends below the gate electrode pad.

The semiconductor device according to the present invention is characterized in that in the above-mentioned invention, the second trench includes a second source connection trench in which the conductive layer is connected to the second source electrode connection portion.

The semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, at least a portion of the first source connection trench is arranged opposite the first trench in the direction of the gate electrode pad when viewed from above.

The semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the protrusion has a portion that extends in a second direction perpendicular to the gate electrode pad direction in a top view.

The semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the protruding portion is provided from above the first trench toward the outside of the first buried portion in the direction of the gate electrode pad.

The semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the second source connection trench is arranged between adjacent first trenches, parallel to the first trenches and spaced apart from the first trenches.

The semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the semiconductor device includes a silicon carbide semiconductor base, the first embedded portion of the gate electrode contacts the silicon carbide semiconductor base via a gate insulating film, and the second embedded portion of the conductive layer contacts at least a portion of the silicon carbide semiconductor base.

The semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the silicon carbide semiconductor substrate includes a drift layer of a first conductivity type, a base layer of a second conductivity type provided above the drift layer, a high-concentration contact region of the second conductivity type selectively provided on the surface side of the base layer and having a higher impurity concentration than the base layer, and a high-concentration source region of the first conductivity type selectively provided on the surface side of the base layer and having a higher impurity concentration than the drift layer.

The semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the second buried portion buried inside the second source connection trench is in contact with at least a portion of the high-concentration contact region.

The semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the silicon carbide semiconductor substrate includes a high-concentration region of the first conductivity type on the surface side of the base layer, the high-concentration region having a higher impurity concentration than the drift layer, which is selectively provided under the first source electrode connection portion.

The semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the silicon carbide semiconductor substrate includes a second conductivity type under-trench base layer provided under the first trench or the second trench.

The semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the source electrode portion includes a source electrode pad, the first source electrode connection portion is a source contact portion that electrically connects the conductive layer of the first source connection trench to the source electrode portion, and the second source electrode connection portion is a source electrode that electrically connects the conductive layer of the second source connection trench to the source electrode portion.

The semiconductor device according to the present invention has the effect of suppressing the lateral voltage drop in the gate pad portion, suppressing the injection of minority carriers (holes), and preventing the body diode from turning on even with a large current.

4 is a cross-sectional view taken along the line Y-Y' of FIG. 3 showing the configuration of a silicon carbide semiconductor device according to a first embodiment. 4 is a cross-sectional view taken along the line X-X' of FIG. 3 showing the configuration of a silicon carbide semiconductor device according to a first embodiment. FIG. 1 is a top view showing a configuration of a silicon carbide semiconductor device according to a first embodiment; 4 is an enlarged view of a portion A in FIG. 3 showing the configuration of the silicon carbide semiconductor device according to the first embodiment. FIG. 4 is a diagram showing current flow in the Y-Y' cross section of FIG. 3 in the silicon carbide semiconductor device according to the first embodiment. 1A to 1C are cross-sectional views (part 1) illustrating schematic diagrams of a silicon carbide semiconductor device in the middle of its manufacture according to the first embodiment; 1A to 1C are cross-sectional views (part 2) illustrating schematic diagrams of a silicon carbide semiconductor device in the middle of its manufacture according to the first embodiment; 1A to 1C are cross-sectional views (part 3) illustrating schematic diagrams of a silicon carbide semiconductor device in the middle of its manufacture according to the first embodiment; 4 is a cross-sectional view illustrating a schematic midway through the manufacture of the silicon carbide semiconductor device according to the first embodiment (part 4); FIG. FIG. 5 is a cross-sectional view illustrating a silicon carbide semiconductor device according to the first embodiment during its manufacture (part 5). 11 is a cross-sectional view showing a configuration of a gate pad portion of a silicon carbide semiconductor device according to a second embodiment. FIG. 13 is a cross-sectional view showing another configuration of the gate pad portion of the silicon carbide semiconductor device according to the second embodiment. FIG. 1 is a cross-sectional view showing a configuration of a conventional SBD-embedded trench-type silicon carbide semiconductor device.

Below, with reference to the attached drawings, a preferred embodiment of the semiconductor device according to the present invention will be described in detail. In this specification and the attached drawings, in layers and regions marked with n or p, electrons or holes, respectively, are the majority carriers. In addition, + and - marked with n or p, respectively, indicate a higher impurity concentration and a lower impurity concentration than layers or regions without them. When the notations of n and p, including + and -, are the same, it indicates that the concentrations are close, but not necessarily the same. In the following description of the embodiment and the attached drawings, similar configurations are marked with the same reference numerals, and duplicate explanations will be omitted.

(Embodiment 1)
The semiconductor device according to the present invention is configured using a wide band gap semiconductor. In the first embodiment, a silicon carbide semiconductor device fabricated using, for example, silicon carbide (SiC) as a wide band gap semiconductor will be described using a MOSFET as an example. Fig. 1 is a Y-Y' cross-sectional view of Fig. 3 showing the configuration of the silicon carbide semiconductor device according to the first embodiment. Fig. 2 is an XX' cross-sectional view of Fig. 3 showing the configuration of the silicon carbide semiconductor device according to the first embodiment. Fig. 3 is a top view showing the configuration of the silicon carbide semiconductor device according to the first embodiment.

The semiconductor device according to the first embodiment shown in FIG. 1 is a trench-type SiC-MOSFET having a gate trench (first trench) 18 and a contact trench (second trench) 19 on the front surface side of a semiconductor substrate (semiconductor chip) in an active portion 21. The active portion 21 is a region through which current flows when in an on-state. The gate trench 18 is a trench in which a gate electrode 10 is embedded via a gate insulating film 9. The contact trench 19 is a trench in which an SBD having a Schottky junction formed by a conductive layer 15, which will be described later, is embedded.

Specifically, as shown in FIGS. 1 and 2 , in the silicon carbide semiconductor device according to the embodiment, an n-type drift layer (first semiconductor layer of first conductivity type) 2 is deposited on a first main surface (front surface), for example, a (0001) surface (Si surface), of an n ^- type silicon carbide substrate (semiconductor substrate of first conductivity type) 1.

The n-type silicon carbide substrate 1 is a silicon carbide single crystal substrate doped with, for example, nitrogen (N). The ^n- type drift layer 2 is a low-concentration n-type drift layer doped with, for example, nitrogen, at an impurity concentration lower than that of the n ^- type silicon carbide substrate 1. An n-type high-concentration region 5 is formed on the surface of the n-type drift layer 2 opposite to the n-type silicon carbide substrate 1. The n-type high-concentration region 5 is a high-concentration n ^- type drift layer doped with, for example, nitrogen, at an impurity concentration lower than that of the n-type silicon carbide substrate 1 and higher than that of the n-type drift layer 2. Hereinafter, the n-type silicon carbide substrate 1, the n ^- type drift layer 2, and a p-type base layer (second semiconductor layer of the second conductivity type) 6 described later are collectively referred to as a silicon carbide semiconductor base.

A back electrode (not shown) is provided on the second main surface (back surface, i.e., the back surface of the silicon carbide semiconductor body) of the n-type silicon carbide substrate 1. The back surface electrode constitutes a drain electrode.

A trench structure is formed on the first main surface side (p-type base layer 6 side) of the silicon carbide semiconductor substrate. Specifically, the gate trench 18 and the contact trench 19 penetrate the p-type base layer 6 from the surface of the p-type base layer 6 opposite to the n-type silicon carbide substrate 1 side (the first main surface side of the silicon carbide semiconductor substrate) to reach the n ^- type drift layer 2. A gate insulating film 9 is formed on the bottom and side walls of the gate trench 18 along the inner wall of the gate trench 18, and a gate electrode 10 is formed inside the gate insulating film 9 in the gate trench 18. The gate electrode 10 is insulated from the n ^- type drift layer 2 and the p-type base layer 6 by the gate insulating film 9. A part of the gate electrode 10 may protrude from the upper side of the gate trench 18 (the source electrode pad 14 side) to the gate electrode pad 17 side.

In the active portion 21, the contact trenches 19 are arranged in a striped planar layout extending in the X-X' direction between adjacent gate trenches 18, parallel to the gate trenches 18 and spaced apart from the gate trenches 18. For example, when the contact trenches 19 are arranged in all the mesa portions, the gate trenches 18 and the contact trenches 19 are arranged alternately and repeatedly spaced apart from each other in the Y-Y' direction perpendicular to the X-X' direction. The contact trenches 19 extend from the first main surface side of the silicon carbide semiconductor substrate through the p-type base layer 6 to reach the n ^- type drift layer 2. The depth of the contact trenches 19 is approximately equal to the depth of the gate trenches 18.

A p ⁺ -type base region 3 is selectively provided in the surface layer of the n ^- -type drift layer 2 on the opposite side (the first main surface side of the silicon carbide semiconductor base) to the n -type silicon carbide substrate 1 side. The p ⁺ -type base region 3 is formed under the gate trench 18 and the contact trench 19, and ^the width of the p ⁺ -type base region 3 is wider than the width of the gate trench 18 and the contact trench 19. The p ⁺ -type base region 3 is doped with aluminum, for example. The p + -type base region 3 is provided away from the p-type base layer 6. The p ⁺ -type base region 3 under the gate trench 18 and the contact trench 19 may be connected to each other at a location not shown. The high-concentration n-type drift layer 5 may be formed to a position deeper than the p ⁺ -type base region 3.

A p-type base layer 6 is provided on the first main surface side of the substrate of the n ^- type drift layer 2. An n ⁺ type source region (first semiconductor region of a first conductivity type) 7 and a p ⁺ type contact region 8 are selectively provided inside the p-type base layer 6 on the first main surface side of the substrate. The n ⁺ type source region 7 is in contact with the gate trench 18. The n ⁺ type source region 7 and the p ⁺ type contact region 8 are in contact with each other.

Although FIG. 1 shows only two trench MOS structures, many more trench MOS gate (metal-oxide-semiconductor insulated gate) structures may be arranged in parallel.

The interlayer insulating film 11 is provided on the entire surface of the first main surface side of the silicon carbide semiconductor substrate so as to cover the gate electrode 10 embedded in the gate trench 18. In the gate pad portion 20, the interlayer insulating film 11 is provided so as to cover the conductive layer 15 embedded in the contact trench 19. The source electrode (first electrode) 13 contacts the n ⁺ type source region 7 and the p ⁺ type contact region 8 through a contact hole opened in the interlayer insulating film 11. The source electrode 13 is electrically insulated from the gate electrode 10 by the interlayer insulating film 11. A source electrode pad 14 is provided on the source electrode 13. Between the source electrode 13 and the interlayer insulating film 11, a barrier metal 12 is provided, which is a single layer or a multilayer of Ti or TiN, for example, that prevents diffusion of metal atoms from the source electrode 13 to the gate electrode 10.

A conductive layer 15 made of, for example, Ti silicide (TiSi) is provided along the front surface of the silicon carbide semiconductor substrate and the inner wall of the contact trench 19. The conductive layer 15 may be configured by stacking electrodes made of different materials. The conductive layer 15 functions as a front surface electrode together with the source electrode 13. The conductive layer 15 contacts the p ⁺ type contact region 8 from the front surface of the silicon carbide semiconductor substrate to the side wall of the contact trench 19.

Moreover, the conductive layer 15 contacts the p ⁺ -type base region 3 over the entire surface from the bottom to the corner of the contact trench 19. The conductive layer 15 contacts the n-type high concentration region 5 on the sidewall of the contact trench 19 and forms a Schottky junction with the n-type high concentration region 5. This forms a Schottky barrier diode consisting of the conductive layer 15 in the contact trench 19 and the n-type high concentration region 5. If the n-type high concentration region 5 is not provided, a Schottky junction with the n ^-type drift layer 2 is formed on the sidewall of the contact trench 19, and a Schottky barrier diode consisting of the conductive layer 15 in the contact trench 19 and the n ^-type drift layer 2 is formed.

A gate electrode pad 17 electrically connected to the gate electrode 10 is provided in the gate pad section 20. The gate electrode pad 17 is electrically insulated from the conductive layer 15 by the interlayer insulating film 11.

The contact trench 19 is also provided in the gate pad portion 20. In the gate pad portion 20, the conductive layer 15 connects to the source electrode 13 in the peripheral portion of the gate pad portion 20. The peripheral portion of the gate pad portion 20 is the boundary portion with the active portion 21 of the gate pad portion 20. In addition, for example, a portion B (see FIG. 3) partially lacking the gate electrode 10 may be provided in the center of the gate pad portion 20, and a source contact portion 24 may be provided inside the portion B to connect the anode electrode of the SBD under the gate electrode pad 17 to the source electrode 13.

FIG. 4 is an enlarged view of a portion A in FIG. 3 showing the configuration of the silicon carbide semiconductor device according to the first embodiment. As shown in FIG. 4, it is preferable to provide an n ⁺ -type region 25 for ohmic contact under the source contact portion 24 (on the n-type silicon carbide substrate 1 side). In addition, in FIG. 1 and FIG. 4, the interval W1 between the p ⁺ -type base regions 3 of the gate pad portion 20 is the same width as the interval W2 between the p ⁺ -type base region 3 covering the bottom surface of the contact trench 19 of the active portion 21 and the p ⁺ -type base region 3 covering the bottom surface of the gate trench 18. However, for example, the interval W1 may be narrower than the interval W2 by narrowing the interval between the contact trenches 19 of the gate pad portion 20. This is because the active portion 21 has a MOS structure, and narrowing the interval W2 narrows the region through which the current passes and increases the on-resistance, so the interval W2 cannot be narrowed. On the other hand, in the gate pad portion 20, when the SBD is conductive, the depletion layer shrinks due to the forward bias of the pn junction, so the interval W2 can be narrowed.

Figure 5 is a diagram showing the current flow when the pn junction is forward biased in the Y-Y' cross section of Figure 3 of the silicon carbide semiconductor device according to the first embodiment. By providing an SBD in the gate pad portion 20 in the same manner as the active portion 21, the SBD current S1 can be caused to flow under the gate pad portion 20 as shown in Figure 5, and this current can suppress the lateral voltage drop under the gate pad portion 20 and suppress the injection of minority carriers (holes).

(Method of Manufacturing Silicon Carbide Semiconductor Device According to First Embodiment)
Next, a description will be given of a method for manufacturing the silicon carbide semiconductor device according to the first embodiment. Figures 6 to 10 are cross-sectional views that typically show states during the manufacturing process of the silicon carbide semiconductor device according to the first embodiment.

First, an n-type silicon carbide substrate 1 made of n-type silicon carbide is prepared. Then, an n-type drift layer 2 made of silicon carbide is epitaxially grown on a first main surface of the n ^- type silicon carbide substrate 1 while being doped with n-type impurities, for example, nitrogen atoms. The state up to this point is shown in FIG.

Next, an ion implantation mask having predetermined openings is formed, for example, from an oxide film by photolithography on the surface of the n ^- type drift layer 2. Then, p-type impurities such as aluminum are implanted into the openings in the oxide film to form p ⁺ -type base regions 3.

Next, a lower n-type high concentration region, which is a part of n-type high concentration region 5, is formed by doping an n-type impurity such as nitrogen on the surface of n ⁻ -type drift layer 2. Next, an n-type epitaxial layer is formed.

Next, a part of the ion implantation mask is removed, and n-type impurities such as nitrogen are ion-implanted into the opening to provide an upper n-type high concentration region in a part of the surface region of the n ^- type drift layer 2. This upper n-type high concentration region and the lower n-type high concentration region are formed so that at least a part of them are in contact with each other to form an n-type high concentration region 5. However, this n-type high concentration region 5 may or may not be formed over the entire surface of the substrate. The state up to this point is shown in FIG.

Next, a p-type base layer 6 doped with p-type impurities such as aluminum is formed by epitaxial growth on the surface of the n ^- type drift layer 2. Next, an ion implantation mask having a predetermined opening is formed, for example, of an oxide film, on the surface of the p ^{-type base layer 6 and the exposed surface of the n-} type drift layer 2 by photolithography. An n-type impurity such as phosphorus (P) is ion-implanted into this opening to form an n ⁺ -type source region 7 in a part of the surface of the p-type base layer 6. The impurity concentration of the n ⁺ -type source region 7 is set to be higher than the impurity concentration of the n-type high concentration region 5. Next, the ion implantation mask used for forming the n ⁺ -type source region 7 is removed, and an ion implantation mask having a predetermined opening is formed in the same manner, and p-type impurities such as aluminum are ion-implanted into a part of the surface of the p-type base layer 6 to provide a p ⁺ -type contact region 8. The impurity concentration of the p ⁺ -type contact region 8 is set to be higher than the impurity concentration of the p-type base layer 6. The state up to this point is shown in FIG. 8. The p-type base layer 6 may be formed by ion implantation of p-type impurities such as aluminum, instead of epitaxial growth.

Next, a heat treatment (annealing) is performed in an inert gas atmosphere at about 1700° C. to activate the p ⁺ type base region 3, the n ⁺ type source region 7, and the p ⁺ type contact region 8. As described above, the ion implantation regions may be activated collectively by a single heat treatment, or the heat treatment may be performed each time an ion implantation is performed.

Next, a trench forming mask having a predetermined opening is formed, for example, from an oxide film, on the surface of the p-type base layer 6 by photolithography. Next, a gate trench 18 and a contact trench 19 are formed by dry etching, penetrating the p ^- type base layer 6 and reaching the n-type drift layer 2. The bottoms of the gate trench 18 and the contact trench 19 may reach the p ⁺ type base region 3 formed in the n ^- type drift layer 2. The gate trench 18 is formed in the active portion 21, and the contact trench 19 is formed in the active portion 21 and the gate pad portion 20. Next, the trench forming mask is removed. The state up to this point is shown in FIG. 9.

Next, annealing is performed to round the corners of the bottoms and openings of the gate trench 18 and contact trench 19. Before annealing, isotropic etching may be performed to remove damage to the gate trench 18 and contact trench 19.

Next, a gate insulating film 9 is formed along the surfaces of the n ⁺ -type source region 7 and the p ⁺ -type contact region 8 and the bottom and sidewalls of the gate trench 18. This gate insulating film 9 may be formed by thermal oxidation through heat treatment at a temperature of about 1000° C. in an oxygen atmosphere. Alternatively, this gate insulating film 9 may be formed by a method of deposition through a chemical reaction such as high temperature oxidation (High Temperature Oxide: HTO).

Next, a polycrystalline silicon layer doped with, for example, phosphorus atoms is provided on the gate insulating film 9. This polycrystalline silicon layer may be formed so as to fill the gate trench 18. This polycrystalline silicon layer is patterned by photolithography and left inside the gate trench 18 to form the gate electrode 10.

Next, a conductive layer 15 is formed along the surfaces of the n ⁺ -type source region 7 and the p ⁺ -type contact region 8 and the bottom and sidewalls of the contact trench 19. This conductive layer 15 may be formed of Ti silicide.

Next, for example, phosphorus glass is deposited to a thickness of about 1 μm to cover the gate insulating film 9, the gate electrode 10, and the conductive layer 15, forming the interlayer insulating film 11. Next, a barrier metal 12 made of titanium (Ti) or titanium nitride (TiN) is formed to cover the interlayer insulating film 11. The interlayer insulating film 11 and the gate insulating film 9 are patterned by photolithography to form contact holes that expose the n ⁺ -type source region 7 and the p ⁺ -type contact region 8. Thereafter, the interlayer insulating film 11 is planarized by performing a heat treatment (reflow).

Next, a conductive film such as nickel (Ni) is provided in the contact hole and on the interlayer insulating film 11 to become the source electrode 13. This conductive film is patterned by photolithography, leaving the source electrode 13 only in the contact hole. The state up to this point is shown in Figure 10.

Next, a back electrode (not shown) made of nickel or the like is provided on the second main surface of the n-type silicon carbide semiconductor substrate 1. Thereafter, a heat treatment is performed in an inert gas atmosphere at about 1000° C. to form the n ⁺ -type source region 7, the p ⁺ -type contact region 8, and the source electrode 13 and the back electrode that are in ohmic junction with the n-type silicon carbide semiconductor substrate 1.

Next, an aluminum film having a thickness of about 5 μm is deposited by sputtering on the first main surface of n ⁺ silicon carbide semiconductor substrate 1, and the aluminum is removed by photolithography so as to cover source electrode 13 and interlayer insulating film 11 of active portion 21, to form source electrode pad 15. Next, by a similar method, gate electrode pad 17 is formed so as to cover interlayer insulating film 11 of gate pad portion 20.

Next, a drain electrode pad (not shown) is formed on the surface of the back electrode by sequentially stacking, for example, titanium (Ti), nickel, and gold (Au). In this manner, the silicon carbide semiconductor device shown in Figures 1 and 2 is completed.

As described above, according to the silicon carbide semiconductor device of the first embodiment, an SBD is provided in the gate pad portion as well as in the active portion. This allows the SBD current to flow even under the gate pad portion, suppressing the lateral voltage drop under the gate pad portion and suppressing the injection of minority carriers (holes). This prevents the body diode from turning on even with a large current.

(Embodiment 2)
Next, the structure of a silicon carbide semiconductor device according to the second embodiment will be described. FIG. 11 is a cross-sectional view showing the configuration of a gate pad portion of the silicon carbide semiconductor device according to the second embodiment. FIG. 12 is a cross-sectional view showing another configuration of the gate pad portion of the silicon carbide semiconductor device according to the second embodiment. The structure of the active portion 21 of the silicon carbide semiconductor device according to the second embodiment is the same as that of the first embodiment, and therefore will not be described (see FIG. 1). The silicon carbide semiconductor device according to the second embodiment differs from the silicon carbide semiconductor device according to the first embodiment in that the contact trench 19 is not provided in the gate pad portion 20, and the p-type region (p ⁺ type base region 3 ′, p-type base layer 6 ′) of the gate pad portion 20 is floating.

The p-type region of the gate pad portion 20 is separated by a predetermined distance W3 from the p-type region of the source potential (p ⁺ -type base region 3, p-type base layer 6) and the n-type high concentration region 5. In this way, by floating the p-type region of the gate pad portion 20, it is possible to prevent continuous injection of minority carriers into the pn junction consisting of the p ⁺ -type base region 3' and the n ^- -type drift layer 2 during forward bias.

In order to prevent a decrease in breakdown voltage when the pn junction is reverse biased due to floating, it is preferable to provide the p-type region of the source potential and the p-type region of the gate pad section 20 at a predetermined distance W3. This predetermined distance W3 is preferably equal to or less than the interval W2 (see FIG. 1) between the p ⁺ type base regions 3 of the active section 21. By making W3 small, when the pn junction is reverse biased, the depletion layer extending from the p ⁺ type base region 3 of the active section 21 easily reaches the p ⁺ type base region 3', resulting in a punch-through state. When the potential of the p ⁺ type base region 3' approaches the p ⁺ type base region 3, the depletion layer also extends from the p ⁺ type base region 3' to the n-type drift region, so that the breakdown voltage does not decrease.

Next, a method for manufacturing the silicon carbide semiconductor device according to the second embodiment will be described. The method for manufacturing the active portion 21 is omitted since it is similar to the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. In the gate pad portion 20, after the ^n- type drift layer 2 is formed, the p ⁺ type base region 3 and the p ⁺ type base region 3' are formed at a predetermined distance W3 between them, with the n- type high concentration region 5 interposed therebetween.

Next, after forming the p-type base layer 6 by epitaxial growth, the gate pad portion 20 and its periphery are etched in an etching process to selectively remove the p-type base layer 6. Here, the p-type base layer 6 may be removed from the entire gate pad portion 20 as shown in FIG. 11, or only the periphery of the gate pad portion 20 as shown in FIG. 12. The OUT etching process is a process for removing the p-type base layer 6 from the chip periphery (voltage-resistant structure portion) since the voltage-resistant structure portion cannot be formed if the p-type base layer 6 is present. When the p-type base layer 6 is formed by ion implantation, the p-type base layer 6 may be formed by separating it from the p-type base layer 6 by a predetermined distance W3 using a mask. The p ⁺ -type base region 3' may be formed to be connected to the p-base layer 6' as shown in FIG. 11 and FIG. 12, or may be formed to be separated from the active portion.

As described above, according to the second embodiment, the p-type region of the gate pad is separated from the p-type region of the source potential. This makes the p-type region of the gate pad floating, and prevents continuous minority carrier injection into the pn junction consisting of the p-type region and the n ^- type drift layer during forward bias. This prevents the body diode from turning on even with a large current.

In addition, in the embodiments of the present invention, a trench MOSFET has been described as an example, but the present invention is not limited to this and can be applied to semiconductor devices of various configurations, such as MOS type semiconductor devices such as planar gate MOSFETs and IGBTs. In addition, in each of the above-mentioned embodiments, silicon carbide has been used as the wide band gap semiconductor, but the same effect can be obtained when a wide band gap semiconductor other than silicon carbide, such as gallium nitride (GaN), is used. In addition, in each embodiment, the first conductivity type is n-type and the second conductivity type is p-type, but the present invention is similarly valid even if the first conductivity type is p-type and the second conductivity type is n-type.

As described above, the semiconductor device according to the present invention is useful for power semiconductor devices used in power conversion devices and power supply devices for various industrial machines, and is particularly suitable for semiconductor devices with a trench gate structure.

REFERENCE SIGNS LIST 1 n-type silicon carbide substrate 2 n ^- type drift layer 3, 3' p ⁺ -type base region 5 n-type high concentration region 6, 6' p-type base layer 7 n ⁺ -type source region 8 p ⁺ -type contact region 9 Gate insulating film 10 Gate electrode 11 Interlayer insulating film 12 Barrier metal 13 Source electrode 14 Source electrode pad 15 Conductive layer 16 Field oxide film 17 Gate electrode pad 18 Gate trench 19 Contact trench 20 Gate pad portion 21 Active portion 24 Source contact portion 25 n ⁺ -type region

Claims (13)

a first trench and a second trench extending toward a gate electrode pad in a top view;
a source electrode portion, at least a portion of which is provided above the first trench and the second trench;
a gate pad portion including a gate electrode pad;
a gate electrode including a first buried portion buried in the first trench and a protruding portion protruding above the first trench;
a conductive layer including a second buried portion buried inside the second trench;
Equipped with
the source electrode portion includes a first source electrode connection portion provided between the protruding portion and the gate electrode pad in a top view, and a second source electrode connection portion sandwiching the protruding portion between the first source electrode connection portion and the second source electrode connection portion in a top view,
The second trench includes a first source connection trench in which the conductive layer connects to the first source electrode connection portion. The semiconductor device according to claim 1, characterized in that the first source connection trench extends below the gate electrode pad. The semiconductor device according to claim 1 or 2, characterized in that the second trench includes a second source connection trench in which the conductive layer connects to the second source electrode connection portion. The semiconductor device according to claim 3, characterized in that at least a portion of the first source connection trench is arranged opposite the first trench in the direction of the gate electrode pad when viewed from above. The semiconductor device according to claim 3 or 4, characterized in that, in top view, the protrusion has a portion that extends in a second direction perpendicular to the gate electrode pad direction. The semiconductor device according to any one of claims 3 to 5, characterized in that the protruding portion is provided from above the first trench toward the outside of the first buried portion in the direction of the gate electrode pad. The semiconductor device according to any one of claims 3 to 6, characterized in that the second source connection trench is disposed between adjacent first trenches, parallel to the first trenches and spaced apart from the first trenches. The semiconductor device includes a silicon carbide semiconductor substrate,
the first embedded portion of the gate electrode is in contact with the silicon carbide semiconductor base via a gate insulating film;
8. The semiconductor device according to claim 3, wherein the second embedded portion of the conductive layer is in contact with at least a portion of the silicon carbide semiconductor base. The silicon carbide semiconductor substrate is
A drift layer of a first conductivity type;
a second conductivity type base layer provided above the drift layer;
a high-concentration contact region of a second conductivity type having an impurity concentration higher than that of the base layer, the high-concentration contact region being selectively provided on a surface side of the base layer;
a first conductivity type high concentration source region having an impurity concentration higher than that of the drift layer, the high concentration source region being selectively provided on a surface side of the base layer;
9. The semiconductor device according to claim 8, further comprising: The semiconductor device according to claim 9, characterized in that the second buried portion buried inside the second source connection trench contacts at least a portion of the high concentration contact region. The semiconductor device according to claim 9 or 10, characterized in that the silicon carbide semiconductor substrate includes a high-concentration region of the first conductivity type on the surface side of the base layer, the high-concentration region having a higher impurity concentration than the drift layer, which is selectively provided under the first source electrode connection portion. The semiconductor device according to any one of claims 8 to 11, characterized in that the silicon carbide semiconductor substrate includes a second conductivity type under-trench base layer provided under the first trench or the second trench. the source electrode portion includes a source electrode pad,
the first source electrode connection portion is a source contact portion that electrically connects the conductive layer of the first source connection trench to the source electrode portion;
13. The semiconductor device according to claim 3, wherein the second source electrode connection portion is a source electrode that electrically connects the conductive layer of the second source connection trench to the source electrode portion.

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