JP7563002B2 - Semiconductor Device - Google Patents

Description

This invention relates to a semiconductor device.

Silicon carbide (SiC) is expected to be the next-generation semiconductor material to replace silicon (Si). Compared to conventional semiconductor elements that use silicon carbide as the semiconductor material, semiconductor elements that use silicon carbide as the semiconductor material (hereafter referred to as silicon carbide semiconductor devices) have various advantages, such as the ability to reduce the resistance of the element in the on-state to one-hundredth of that of conventional semiconductor elements that use silicon as the semiconductor material, and the ability to be used in higher temperature environments (200°C or higher). This is due to the characteristics of the material itself, in that the band gap of silicon carbide is about three times larger than that of silicon, and its dielectric breakdown field strength is nearly one order of magnitude greater than that of silicon.

Silicon carbide semiconductor devices that have been commercialized to date include Schottky barrier diodes (SBDs) and vertical MOSFETs (metal oxide semiconductor field effect transistors) with planar gate and trench gate structures.

The planar gate structure is a MOS gate structure in which a MOS gate is provided in a flat plate shape on the front surface of a semiconductor substrate. The trench gate structure is a MOS gate structure in which a MOS gate is embedded in a trench formed on the front surface of a semiconductor substrate (semiconductor chip), and a channel (inversion layer) is formed along the sidewall of the trench in a direction perpendicular to the front surface of the semiconductor substrate. Therefore, compared to a planar gate structure in which a channel is formed along the front surface of a semiconductor substrate, it is possible to increase the unit cell (element constituent unit) density per unit area, and therefore the current density per unit area, which is advantageous in terms of cost.

The structure of a conventional silicon carbide semiconductor device will be described by taking a trench MOSFET as an example. FIG. 15 is a cross-sectional view showing the structure of an active region of a conventional silicon carbide semiconductor device. FIG. 15 shows the structure of an active region 140 through which a current flows when the device is on. As shown in FIG. 15, in a trench MOSFET 170, an n ^- type silicon carbide epitaxial layer 102 is deposited on the front surface of an n ⁺ type silicon carbide substrate 101. An n-type high concentration region 105 is provided on the front surface side of the n ^- type silicon carbide epitaxial layer 102 opposite to the n+ type silicon carbide substrate 101 side. A first p ⁺ type base region 103 is selectively provided in the n ^- type silicon carbide ^epitaxial layer 102 so as to cover the entire bottom surface of the trench 116.

Further, as the MOS structure, a p-type silicon carbide epitaxial layer 106, an n ⁺ -type source region 107, a p ⁺ -type contact region 108, a gate insulating film 109, a gate electrode 110, an interlayer insulating film 111, a source electrode 112, a back electrode 113, a trench 116, a source electrode pad (not shown), and a drain electrode pad (not shown) are provided. The source electrode 112 is provided on the n ⁺ -type source region 107 and the p-type silicon carbide epitaxial layer 106, and a source electrode pad is provided on the source electrode 112.

By providing the first p ⁺ type base region 103 on the bottom surface of the trench 116, the electric field is prevented from concentrating on the bottom surface of the trench 116, and the gate insulating film 109 is protected. On the other hand, in order to maintain the breakdown voltage, the first p ⁺ type base region 103 needs to be set to the source electrode 112 and have the same potential, rather than floating. For this reason, a structure is known in which the second p ⁺ type base region 104 is selectively provided on a part of the side wall of the channel of the trench 116. This prevents punch-through and maintains the breakdown voltage. By providing the second p ⁺ type base region 104 on the side wall of the m-plane of the trench 116, the a-plane with high mobility can be used for the channel. Furthermore, by providing the second p ⁺ type base region 104, it is no longer necessary to provide a p-type region between the trenches 116, and the cell pitch can be reduced.

A semiconductor device is also known that can reduce the electric field applied to the bottom surface of the gate trench when the semiconductor device is in the off state by providing an electric field reduction region in contact with the bottom surface of the gate trench (see Patent Document 1 below). A semiconductor device is also known in which a second trench is provided in the non-element region, the bottom surface of which reaches the drift layer, and a low resistance region is provided in the second trench via an inner surface insulating film to form a capacitance, and during high-speed switching, the displacement current passing through the second reduction region below the second trench is branched to the low resistance region, thereby suppressing the magnitude of the potential drop caused by the displacement current (see Patent Document 2 below).

JP 2019-195081 A International Publication No. 2019/159351

FIG. 16 is a cross-sectional view showing a first structure of a gate pad region of a conventional silicon carbide semiconductor device. FIG. 17 is a cross-sectional view showing a second structure of a gate pad region of a conventional silicon carbide semiconductor device. In the gate pad region 150, similar to the active region 140, an n ^- type silicon carbide epitaxial layer 102 and a p-type silicon carbide epitaxial layer 106 are provided on the front surface of an n ⁺ type silicon carbide substrate 101. A gate electrode pad 114 is provided on the p-type silicon carbide epitaxial layer 106 via an interlayer insulating film 111. As shown in FIG. 17, a gate electrode wiring 115 may be provided in the interlayer insulating film 111. A back electrode 113 is provided on the back surface of the ⁿ⁺ type silicon carbide substrate 101.

As shown in FIG. 16 and FIG. 17, in the conventional trench structure, the gate pad region 150 does not have a trench structure. Therefore, the first p ⁺ -type base region 103 and the second p ⁺ -type base region 104 cannot be provided. As a result, in the gate pad region 150, the pn interface between the p-type silicon carbide epitaxial layer 106 and the n ^- -type silicon carbide epitaxial layer 102 is located shallower from the surface of the p-type silicon carbide epitaxial layer 106 than in the active region 140, and an electric field is concentrated at the pn interface of the gate pad region 150. Therefore, there is a problem that avalanche breakdown occurs in the gate pad region 150, the breakdown voltage cannot be maintained, and the reliability of the gate pad region 150 is deteriorated.

The purpose of this invention is to provide a semiconductor device that can eliminate the concentration of avalanche current in the gate pad region and improve the reliability of the gate pad region in order to solve the problems of the conventional technology described above.

In order to solve the above-mentioned problems and achieve the object of the present invention, the semiconductor device according to the present invention has the following features. The semiconductor device includes a semiconductor substrate of a first conductivity type having an active portion and a gate pad portion, a first semiconductor layer of a first conductivity type having a lower impurity concentration than the semiconductor substrate and provided on a front surface of the semiconductor substrate, and a second semiconductor layer of a second conductivity type selectively provided on a surface of the first semiconductor layer opposite to the semiconductor substrate side. The active portion includes a first semiconductor region of the first conductivity type selectively provided in a surface layer of the second semiconductor layer opposite to the semiconductor substrate side, a first trench penetrating the first semiconductor region or the second semiconductor layer and reaching the first semiconductor layer, a first gate electrode provided inside the first trench via a gate insulating film, an interlayer insulating film provided on the first gate electrode, a first electrode provided on surfaces of the second semiconductor layer and the first semiconductor region, a second electrode provided on a rear surface of the semiconductor substrate, and a second semiconductor region of the second conductivity type provided so as to contact a bottom of the first trench. The gate pad portion includes a second trench that penetrates the second semiconductor layer and reaches the first semiconductor layer, a second gate electrode provided inside the second trench via an insulating film, a fourth semiconductor region of a second conductivity type provided so as to contact a bottom of the second trench, and a gate electrode pad electrically connected to the second gate electrode. A polycrystalline silicon film is provided between the gate electrode pad and the semiconductor substrate. The insulating film is also provided on a surface of the semiconductor substrate in a mesa region between adjacent second trenches, and the polycrystalline silicon film is a gate wiring electrode provided on the insulating film on the surface of the mesa region.

In order to solve the above-mentioned problems and achieve the object of the present invention, the semiconductor device according to the present invention has the following features. The semiconductor device includes a semiconductor substrate of a first conductivity type having an active portion and a gate pad portion, a first semiconductor layer of a first conductivity type having a lower impurity concentration than the semiconductor substrate and provided on a front surface of the semiconductor substrate, and a second semiconductor layer of a second conductivity type selectively provided on a surface of the first semiconductor layer opposite to the semiconductor substrate side. The active portion includes a first semiconductor region of the first conductivity type selectively provided in a surface layer of the second semiconductor layer opposite to the semiconductor substrate side, a first trench penetrating the first semiconductor region or the second semiconductor layer and reaching the first semiconductor layer, a first gate electrode provided inside the first trench via a gate insulating film, an interlayer insulating film provided on the first gate electrode, a first electrode provided on surfaces of the second semiconductor layer and the first semiconductor region, a second electrode provided on a rear surface of the semiconductor substrate, and a second semiconductor region of the second conductivity type provided so as to contact a bottom of the first trench. The gate pad portion includes a second trench that penetrates the second semiconductor layer and reaches the first semiconductor layer, a second gate electrode provided inside the second trench via an insulating film, a fourth semiconductor region of a second conductivity type provided so as to contact a bottom of the second trench, and a gate electrode pad electrically connected to the second gate electrode. A polycrystalline silicon film is provided between the gate electrode pad and the semiconductor substrate. The extension direction of the second trench is parallel to a wire connected to the gate pad portion. In order to solve the above-mentioned problems and achieve the object of the present invention, the semiconductor device according to the present invention has the following features. The semiconductor device includes a semiconductor substrate of a first conductivity type having an active portion and a gate pad portion, a first semiconductor layer of a first conductivity type having a lower impurity concentration than the semiconductor substrate and provided on a front surface of the semiconductor substrate, and a second semiconductor layer of a second conductivity type selectively provided on a surface of the first semiconductor layer opposite to the semiconductor substrate. The active section includes a first semiconductor region of a first conductivity type selectively provided in a surface layer of the second semiconductor layer on the opposite side to the semiconductor substrate side, a first trench penetrating the first semiconductor region or the second semiconductor layer and reaching the first semiconductor layer, a first gate electrode provided inside the first trench via a gate insulating film, an interlayer insulating film provided on the first gate electrode, a first electrode provided on the surface of the second semiconductor layer and the first semiconductor region, a second electrode provided on the back surface of the semiconductor substrate, and a second semiconductor region of a second conductivity type provided so as to contact the bottom of the first trench. The gate pad section includes a second trench penetrating the second semiconductor layer and reaching the first semiconductor layer, a second gate electrode provided inside the second trench via an insulating film, a fourth semiconductor region of a second conductivity type provided so as to contact the bottom of the second trench, and a gate electrode pad electrically connected to the second gate electrode. A polycrystalline silicon film is provided between the gate electrode pad and the semiconductor substrate. The polycrystalline silicon film is the second gate electrode, and the second gate electrode is provided on the entire surface between the gate electrode pad and the semiconductor substrate. In order to solve the above-mentioned problems and achieve the object of the present invention, the semiconductor device according to the present invention has the following features. The semiconductor device includes a semiconductor substrate of a first conductivity type having an active portion and a gate pad portion, a first semiconductor layer of the first conductivity type provided on a front surface of the semiconductor substrate and having a lower impurity concentration than the semiconductor substrate, and a second semiconductor layer of a second conductivity type selectively provided on a surface of the first semiconductor layer opposite to the semiconductor substrate side. The active portion includes a first semiconductor region of a first conductivity type selectively provided in a surface layer of the second semiconductor layer opposite to the semiconductor substrate side, a first trench penetrating the first semiconductor region or the second semiconductor layer and reaching the first semiconductor layer, a first gate electrode provided inside the first trench via a gate insulating film, an interlayer insulating film provided on the first gate electrode, a first electrode provided on the surfaces of the second semiconductor layer and the first semiconductor region, a second electrode provided on the back surface of the semiconductor substrate, and a second semiconductor region of a second conductivity type provided so as to contact the bottom of the first trench. The gate pad portion includes a second trench that penetrates the second semiconductor layer and reaches the first semiconductor layer, a second gate electrode provided inside the second trench via an insulating film, a fourth semiconductor region of a second conductivity type provided so as to contact the bottom of the second trench, a gate electrode pad electrically connected to the second gate electrode, and a fifth semiconductor region of a second conductivity type provided in the first semiconductor layer so as to contact a sidewall of the second trench and electrically connecting the second semiconductor region and the fourth semiconductor region. A polycrystalline silicon film is provided between the gate electrode pad and the semiconductor substrate. The fourth semiconductor region has a higher impurity concentration than the second semiconductor region.

The semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, it further comprises a third semiconductor region of a second conductivity type that electrically connects the second semiconductor region and the second semiconductor layer and is provided in the first semiconductor layer so as to contact at least one sidewall of the first trench in a second direction perpendicular to a first direction parallel to the extension direction of the first trench.

The semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the third semiconductor region is provided in a plurality of regions spaced apart from one another within the first semiconductor layer.

The semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, it further comprises a fifth semiconductor region of the second conductivity type that is provided in the first semiconductor layer so as to contact the sidewall of the second trench and electrically connects the second semiconductor region and the fourth semiconductor region.

The semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the fifth semiconductor region is provided in the first semiconductor layer so as to contact both trench sidewalls of the second trench.

The semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the second trench is wider than the first trench.

The semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the second trench is deeper than the first trench.

The semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the first trench provided at the outermost periphery of the active portion does not have the first semiconductor region provided on the sidewall on the gate pad portion side in a second direction perpendicular to a first direction parallel to the extension direction of the first trench.

According to the above-mentioned invention, the gate pad region is also provided with a trench and a first p ⁺ -type base region (second semiconductor region of the second conductivity type) covering the bottom surface of the trench. This makes the pn interface between the n ^- -type silicon carbide epitaxial layer (first semiconductor layer of the first conductivity type) and the first p ⁺ -type base region in the active region and the gate pad region the same depth from the surface of the silicon carbide semiconductor substrate. This prevents avalanche current from concentrating in the gate pad region, making it possible to maintain the breakdown voltage of the gate pad region and improve the reliability of the gate insulating film.

The semiconductor device according to the present invention has the effect of eliminating the concentration of avalanche current in the gate pad region, thereby improving the reliability of the gate pad region.

1 is a cross-sectional view showing a structure of an active region of a silicon carbide semiconductor device according to a first embodiment. 2 is a cross-sectional view showing a first structure of a gate pad region of the silicon carbide semiconductor device in accordance with the first embodiment; 4 is a cross-sectional view showing a second structure of the gate pad region of the silicon carbide semiconductor device according to the first embodiment. FIG. 4 is a cross-sectional view showing a third structure of the gate pad region of the silicon carbide semiconductor device according to the first embodiment. FIG. 11 is a cross-sectional view showing a fourth structure of the gate pad region of the silicon carbide semiconductor device according to the first embodiment. FIG. FIG. 11 is a cross-sectional view showing a fifth structure of the gate pad region of the silicon carbide semiconductor device according to the first embodiment. 1 is a top view showing a structure of a silicon carbide semiconductor device according to a first embodiment; 1A to 1C are cross-sectional views showing a state during manufacture of a silicon carbide semiconductor device according to a first embodiment (part 1). 1 is a cross-sectional view showing a state during manufacture of the silicon carbide semiconductor device according to the first embodiment (part 2). FIG. 11A to 11C are cross-sectional views showing a state during manufacture of the silicon carbide semiconductor device according to the first embodiment (part 3). 4 is a cross-sectional view showing a state during manufacture of the silicon carbide semiconductor device according to the first embodiment (part 4). 5 is a cross-sectional view showing a state during manufacture of the silicon carbide semiconductor device according to the first embodiment (part 5). 11 is a cross-sectional view showing a structure of an active region and a gate pad region of a silicon carbide semiconductor device according to a second embodiment. FIG. FIG. 11 is a top view showing a structure of a silicon carbide semiconductor device according to a second embodiment. 1 is a cross-sectional view showing a structure of an active region of a conventional silicon carbide semiconductor device. 1 is a cross-sectional view showing a first structure of a gate pad region of a conventional silicon carbide semiconductor device. FIG. 11 is a cross-sectional view showing a second structure of a gate pad region of a conventional silicon carbide semiconductor device.

The preferred embodiment of the semiconductor device according to the present invention will be described in detail below with reference to the attached drawings. In this specification and the attached drawings, in layers and regions with n or p, electrons or holes are the majority carriers, respectively. In addition, + and - attached to n or p respectively mean that the impurity concentration is higher and lower than that of layers and regions without n or p. Note that in the following description of the embodiment and the attached drawings, the same reference numerals are used for similar configurations, and duplicated explanations are omitted. In addition, in this specification, in the notation of Miller indices, "-" means a bar attached to the index immediately following it, and adding "-" before an index indicates a negative index. In addition, it is preferable that the description of "same" or "equivalent" includes within 5% in consideration of manufacturing variations.

(Embodiment 1)
The semiconductor device according to the present invention is configured using a wide band gap semiconductor. In the first embodiment, a trench-type MOSFET 70 will be described as an example of a silicon carbide semiconductor device fabricated (manufactured) using silicon carbide (SiC) as a wide band gap semiconductor. FIG 1 is a cross-sectional view showing a structure of an active region of the silicon carbide semiconductor device according to the first embodiment.

In the silicon carbide semiconductor device according to the first embodiment, an edge termination region that surrounds the active region 40 and maintains a breakdown voltage and a gate pad region 50 that is connected to the gate electrode are provided on the outer periphery of the active region 40 through which the main current flows. In FIG. 1, only the active region 40 of the trench MOSFET 70 is shown.

1, trench MOSFET 70 includes a MOS gate having a trench gate structure on the front surface (the surface on the side of a p-type silicon carbide epitaxial layer 6 described later) of a semiconductor substrate. The silicon carbide semiconductor base is formed by epitaxially growing an n ^- type silicon carbide epitaxial layer (first semiconductor layer of first conductivity type) 2 in this order on an n ⁺ type silicon carbide substrate (semiconductor substrate of first conductivity type) 1 made of silicon carbide. An n-type high concentration region 5 may also be epitaxially grown on n-type silicon carbide epitaxial layer 2.

The MOS gate of the trench gate structure is composed of a p-type silicon carbide epitaxial layer (second semiconductor layer of second conductivity type) 6, an n ⁺ -type source region (first semiconductor region of first conductivity type) 7, a p ⁺ -type contact region 8, a trench (first trench) 16a, a gate insulating film 9, and a gate electrode (first gate electrode) 10. Note that the p ⁺ -type contact region 8 does not necessarily have to be provided.

Specifically, trenches 16a penetrate p-type silicon carbide epitaxial layer 6 from the front surface of the semiconductor substrate in depth direction y to reach n-type high concentration region 5 (if n-type high concentration region 5 is not provided, n ^-type silicon carbide epitaxial layer 2, hereinafter referred to as (2)). Depth direction y is the direction from the front surface to the back surface of the semiconductor substrate. Trenches 16a are arranged in a stripe pattern (see FIG. 7).

Inside the trench 16a, a gate insulating film 9 is provided along the inner wall of the trench 16a, and a gate electrode 10 is provided on the gate insulating film 9 so as to be embedded inside the trench 16a. The gate electrode 10 in one trench 16a and the adjacent mesa regions 17a (regions between adjacent trenches 16a) sandwiching the gate electrode 10 form one unit cell of the main semiconductor element. Although only three trench MOS structures are shown in FIG. 1, many more trench-structured MOS gate (insulated gate made of metal-oxide film-semiconductor) structures may be arranged in parallel.

An n-type region (hereinafter referred to as n-type high concentration region) 5 may be provided in the surface layer of the source side (the source electrode 12 side described later) of the n ^- type silicon carbide epitaxial layer 2 so as to contact the p-type silicon carbide epitaxial layer 6. The n-type high concentration region 5 is a so-called current spreading layer (CSL) that reduces the spreading resistance of carriers. For example, the n-type high concentration region 5 is uniformly provided in a direction parallel to the front surface of the substrate (front surface of the semiconductor substrate) so as to cover the inner wall of the trench 16a. The n-type high concentration region 5 is provided from the interface with the p-type silicon carbide epitaxial layer 6 to a position not reaching the bottom surface of the trench 16a. The n-type high concentration region 5 may be provided to a position deeper than the bottom surface of the trench 16a and shallower than the bottom surface of the first p ⁺ type base region 3 described later.

A first p ⁺ type base region (second semiconductor region of a second conductivity type) 3 may be selectively provided inside the n ^- type silicon carbide epitaxial layer 2. The first p ⁺ type base region 3 covers at least the bottom surface of the trench 16a and the bottom surface corner portion. The bottom surface corner portion of the trench 16a is the boundary between the bottom surface and the sidewall of the trench 16a.

The pn junction between the first p ⁺ type base region 3 and the n ^- type silicon carbide epitaxial layer 2 is formed at a position deeper on the drain side than the bottom surface of the trench 16a. The depth position of the drain side end of the first p ⁺ type base region 3 may be changed in various ways according to design conditions as long as the pn junction between the first p ⁺ type base region 3 and the n ^- type silicon carbide epitaxial layer 2 is located deeper on the drain side than the bottom surface of the trench 16a. The first p ⁺ type base region 3 can prevent a high electric field from being applied to the gate insulating film 9 in the portion along the bottom surface of the trench 16a.

A second p + -type base region (third semiconductor region of second conductivity type) 4 may be provided in the n ^-type silicon carbide epitaxial layer 2 (when the n-type high concentration region 5 is provided, the n ^-type silicon carbide epitaxial layer 2 and the n-type high concentration region 5, hereinafter referred to as (2, 5)) so as to contact at least one of the trench sidewalls in a second direction ( ^x direction) perpendicular to a first direction (z direction) parallel to the extension direction of the trench 16a. One of the trench sidewalls may be an m-plane or an a-plane.

The second p ⁺ type base region (third semiconductor region of second conductivity type) 4 is provided so as to contact the p type silicon carbide epitaxial layer 6 and the first p ⁺ type base region 3. As shown in FIG. 1, the bottom surface of the second p ⁺ type base region 4 may contact the n ^- type silicon carbide epitaxial layer 2 at the same depth as the first p ⁺ type base region 3, and the top surface may contact the n ⁺ type source region 7 described later. The second p ⁺ type base region 4 electrically connects the first p ⁺ type base region 3 and the p type silicon carbide epitaxial layer 6, and the first p ⁺ type base region 3 is not floating but has the same potential as the source electrode 12. This prevents punch-through and maintains the breakdown voltage.

The second p ⁺ type base region 4 may be provided in the n ^- type silicon carbide epitaxial layer 2 (2, 5) at intervals in a first direction parallel to the extension direction of the trench 16 a. In this case, one side wall of the trench 16 a in the first direction is in contact with the second p ⁺ type base region 4 and the n ^- type silicon carbide epitaxial layer 2 (2, 5) alternately.

Alternatively, the second p ⁺ type base region 4 may be provided on one sidewall of the trench 16 a without any spacing therebetween. In this case, one sidewall of the trench 16 a contacts the second p ⁺ type base region 4 in the first direction.

An n ⁺ type source region 7 and p ⁺ type contact region 8 are selectively provided inside p type silicon carbide epitaxial layer 6. N ⁺ type source region 7 contacts gate insulating film 9 on the side wall of trench 16a, and faces gate electrode 10 via gate insulating film 9 on the side wall of trench 16a.

The interlayer insulating film 11 is provided over the entire front surface of the semiconductor substrate so as to cover the gate electrode 10. A contact hole is opened in the interlayer insulating film 11, penetrating the interlayer insulating film 11 in the depth direction y to reach the front surface of the substrate.

The source electrode (first electrode) 12 is in ohmic contact with the semiconductor substrate (n ⁺ type source region 7) in a contact hole opened in the interlayer insulating film 11, and is electrically insulated from the gate electrode 10 by the interlayer insulating film 11. A source electrode pad (not shown) is provided on the source electrode 12. The source electrode 12 is in ohmic contact with the n ⁺ type source region 7 and the p ⁺ type contact region 8. If the p ⁺ type contact region 8 is not provided, the source electrode 12 is in ohmic contact with the n ⁺ type source region 7 and the p type silicon carbide epitaxial layer 6.

A back electrode (second electrode) 13 that serves as a drain electrode is provided on the back surface of the semiconductor substrate. A drain electrode pad (not shown) is provided on the back surface electrode 13.

2 is a cross-sectional view showing a first structure of the gate pad region of the silicon carbide semiconductor device according to the first embodiment. In the gate pad region 50, similarly to the active region 40, an n ⁻ type silicon carbide epitaxial layer 2 and a p type silicon carbide epitaxial layer 6 are provided on the front surface of an n ⁺ type silicon carbide substrate 1. The thicknesses and impurity concentrations of the n ⁺ type silicon carbide substrate 1, the n ⁻ type silicon carbide epitaxial layer 2, and the p type silicon carbide epitaxial layer 6 in the gate pad region 50 are the same as those of the n ⁺ type silicon carbide substrate 1, the n ⁻ type silicon carbide epitaxial layer 2, and the p type silicon carbide epitaxial layer 6 in the active region. The p type silicon carbide epitaxial layer 6 in the gate pad region 50 is connected to the p type silicon carbide epitaxial layer 6 in the active region 40.

In the first embodiment, a trench gate structure consisting of a trench (second trench) 16b, a gate insulating film (insulating film) 9b, and a gate electrode (second gate electrode) 10b is provided in the gate pad region 50. The width and depth of the trench 16b in the gate pad region 50 are the same as the width and depth of the trench 16a in the active region 40. In the gate pad region 50, a gate insulating film 16b is also provided on the surface of the semiconductor substrate in the mesa region 17b between adjacent trenches 16b.

A first p ⁺ type base region (fourth semiconductor region of the second conductivity type) 3b may be selectively provided inside the n ⁻ type silicon carbide epitaxial layer 2. The first p ⁺ type base region 3b covers at least the bottom surface of the bottom surface and the bottom corner portions of the trench 16b, similarly to the active region 40. The width and depth of the first p ⁺ type base region 3b in the gate pad region 50 are the same as the width and depth of the first p ⁺ type base region 3 in the active region 40.

The interlayer insulating film 11 is provided on the entire front surface of the semiconductor substrate via the gate insulating film 9b, and a gate electrode pad 14 electrically connected to the gate electrode 10 is provided on the interlayer insulating film 11. A back surface electrode 13 serving as a drain electrode is provided on the back surface of the semiconductor substrate. A drain electrode pad (not shown) is provided on the back surface electrode 13. An n-type high concentration region 5 may be provided in the surface layer on the source side of the n ^-type silicon carbide epitaxial layer 2 so as to be in contact with the p-type silicon carbide epitaxial layer 6.

Thus, in the first embodiment, the gate pad region 50 is also provided with the trench 16b, and the first p ⁺ -type base region 3b is provided to cover the bottom surface of the trench 16b. This allows the pn interfaces between the n ^- -type silicon carbide epitaxial layer 2 and the first p ⁺ -type base regions 3, 3b in the active region 40 and the gate pad region 50 to be at the same depth from the surface of the silicon carbide semiconductor substrate. This prevents the avalanche current from concentrating in the gate pad region 50, making it possible to maintain the breakdown voltage of the gate pad region 50 and improve the reliability of the gate insulating film 9.

Here, the trench 16b of the gate pad region 50 may or may not be connected to the trench 16a of the active region 40. When the trench 16b is connected to the trench 16a, the first p ⁺ type base region 3b can be easily set to the same potential as the source electrode 12 by connecting the first p ⁺ type base region 3b to the first p ⁺ type base region 3 of the active region 40. When the trench 16b is not connected to the trench 16a, the width and depth of the trench 16b can be made larger than those of the trench 16a. Also, the impurity concentration of the first p ⁺ type base region 3b can be made higher than that of the first p ⁺ type base region 3 of the active region 40. This makes it easier for holes to concentrate in the trench 16b, making it easier to control the holes.

3 is a cross-sectional view showing a second structure of the gate pad region of the silicon carbide semiconductor device according to the first embodiment. As shown in FIG. 3, in the gate pad region 50, the interlayer insulating film 11A is provided on the entire front surface of the semiconductor substrate via the gate insulating film 9b so as to cover the p-type silicon carbide epitaxial layer 6. The interlayer insulating film 11A has a contact hole that penetrates the interlayer insulating film 11A in the depth direction y and reaches the front surface of the substrate. In the gate pad region 50, a gate electrode wiring (polycrystalline silicon film) 15 made of polycrystalline silicon (Poly-Si) is provided on the entire front surface of the semiconductor substrate. The gate electrode wiring 15 may be made of refractory metals such as titanium and tungsten, their silicides, nitrides, or laminated films thereof, in addition to polycrystalline silicon. The gate electrode wiring 15 is in ohmic contact with the gate electrode 10 in a contact hole provided in the interlayer insulating film 11A, and is electrically insulated from the p-type silicon carbide epitaxial layer 6 by the interlayer insulating film 11A.

The gate electrode pad 14 is provided on the gate electrode wiring 15 via the interlayer insulating film 11B. That is, a polycrystalline silicon film is provided as the gate electrode wiring 15 on the entire surface between the gate electrode pad 14 and the n ⁺ type silicon carbide substrate 1. The gate electrode wiring 15 and the gate electrode pad 14 are electrically connected. In FIG. 3, the interlayer insulating film 11B in the gate pad region 50 is not provided with a contact hole, and the gate electrode wiring 15 and the gate electrode pad 14 are connected in a portion other than the gate pad region 50. In this case, there is an advantage that the bonding area when bonding the wire to the gate electrode pad 14 is not reduced. Furthermore, since the interlayer insulating film 11B is always present directly below the gate electrode pad 14, damage to the element structure below is small. In addition, it is also possible to provide a contact hole in the interlayer insulating film 11B in the gate pad region 50, and to electrically connect the gate electrode wiring 15 and the gate electrode pad 14 through the contact hole. In this case, the interlayer insulating film 11B between the gate electrode pad 14 and the gate electrode wiring 15 can be opened widely, and the contact resistance between the gate electrode pad 14 and the gate electrode wiring 15 can be reduced.

In this way, by providing the gate electrode wiring 15 on the entire lower surface of the gate electrode pad 14 in the gate pad region 50, the surface of the gate electrode pad 15 can be made flat, and the bonding area when bonding a wire to the gate electrode pad 14 can be increased. Furthermore, the cross-sectional area of the gate electrode wiring 15 under the gate electrode pad 14 is increased, so the gate resistance (Rg) can be reduced.

4 is a cross-sectional view showing a third structure of the gate pad region of the silicon carbide semiconductor device according to the first embodiment. As shown in FIG. 4, in the gate pad region 50, a second p ⁺ type base region (a fifth semiconductor region of a second conductivity type) 4b is selectively provided on a part of the sidewall of the trench 16b. The second p ⁺ type base region 4b is provided so as to contact the p-type silicon carbide epitaxial layer 6 and the first p ⁺ type base region 3b. The width and depth of the second p ⁺ type base region 4b in the gate pad region 50 are the same as the width and depth of the second p ⁺ type base region 4 in the active region 40.

The p-type silicon carbide epitaxial layer 6 in the gate pad region 50 is continuously connected to the p-type silicon carbide epitaxial layer 6 in the active region 40 in the first direction (z direction) (see FIG. 7). For this reason, similarly to the active region 40, the second p ⁺ -type base region 4b electrically connects the first p ⁺ -type base region 3b and the p-type silicon carbide epitaxial layer 6, and the first p ⁺ -type base region 3b is not floating but is at the same potential as the source electrode 12. This prevents punch-through and maintains the breakdown voltage.

Similarly to the active region 40, the second p ⁺ type base region 4b may be provided in the n ^- type silicon carbide epitaxial layer 2 in a first direction parallel to the extension direction of the trench 16b with a gap therebetween. In this case, one sidewall of the trench 16b in the first direction is in contact with the second p ⁺ type base region 4b and the n ^- type silicon carbide epitaxial layer 2 alternately. Alternatively, the second p ⁺ type base region 4b may be provided on one sidewall of the trench 16b without a gap therebetween. In this case, one sidewall of the trench 16b in the first direction is in contact with the second p ⁺ type base region 4b.

5 is a cross-sectional view showing a fourth structure of the gate pad region of the silicon carbide semiconductor device according to the first embodiment. As shown in FIG. 5, in the gate pad region 50, the gate electrode wiring 15 is provided on the entire front surface of the semiconductor substrate, and the second p ⁺ -type base region 4b is selectively provided on a part of the side wall of the trench 16b. In this way, the fourth structure has the features of the second structure and the third structure, and has the effects of both the second structure and the third structure.

FIG. 6 is a cross-sectional view showing a fifth structure of the gate pad region of the silicon carbide semiconductor device according to the first embodiment. As shown in FIG. 6, the second p ⁺ type base region 4b is selectively provided on both sides of the sidewall of the trench 16b. The trench 16b in the gate pad region 50 does not function as a MOS gate, and does not need to form a channel, and the second p ⁺ type base region 4b can be provided on both sides of the sidewall. This makes it possible to prevent punch-through and maintain a breakdown voltage more effectively than the third structure in FIG. 4. Although not shown, the structure in FIG. 6 also makes it possible to provide a gate electrode wiring 15 on the entire front surface of the semiconductor substrate in the gate pad region 50.

7 is a top view showing the structure of a silicon carbide semiconductor device according to the first embodiment. In FIG. 7, the region below the source electrode 12 is the active region 40, and the region below the gate electrode pad 14 is the gate pad region 50. The p-type silicon carbide epitaxial layer 6 in the gate pad region 50 is connected to the p-type silicon carbide epitaxial layer 6 in the active region 40. As shown in FIG. 7, the extension direction (x direction) of the trench 16b in the gate pad region 50 is preferably provided in the same direction as the extension direction of the trench 16a in the active region 40. The extension direction of the trench 16b in the gate pad region 50 is preferably parallel to the wire connected to the gate electrode pad 14. For example, one end of the wire is at position A outside the x direction of the trench MOSFET 70, and position A and the gate electrode pad 14 are connected by a wire. This prevents shell cracks, such as those that destroy the interlayer insulating film 11, from occurring when connecting a wire to the gate electrode pad 14.

(Method of Manufacturing Silicon Carbide Semiconductor Device According to First Embodiment)
Next, a description will be given of a method for manufacturing the silicon carbide semiconductor device according to the first embodiment. Figures 8 to 12 are cross-sectional views showing states during the manufacturing process of the silicon carbide semiconductor device according to the first embodiment.

First, an n ⁺ type silicon carbide substrate 1 made of n type silicon carbide is prepared. Then, a lower n ^- type silicon carbide epitaxial layer 2a made of silicon carbide is epitaxially grown on the front surface of the n ⁺ type silicon carbide substrate 1 while doping with n type impurities, for example, nitrogen atoms. The state up to this point is shown in FIG.

Next, an ion implantation mask having predetermined openings is formed on the surface of the lower n ^- type silicon carbide epitaxial layer 2a by photolithography, for example, and p-type impurities such as aluminum are implanted into the openings in the oxide film to form the first p ⁺ type base regions 3, 3b.

Next, an upper n ^- type silicon carbide epitaxial layer 2b made of silicon carbide is epitaxially grown on the surface of the lower n ^- type silicon carbide epitaxial layer 2a while doping with an n-type impurity such as nitrogen. The lower n ^- type silicon carbide epitaxial layer 2a and the upper n ^- type silicon carbide epitaxial layer 2b are combined to form the n ^- type silicon carbide epitaxial layer 2.

Next, a part of the ion implantation mask may be removed, and an n-type impurity such as nitrogen may be ion-implanted into the opening to form an n-type high concentration region 5 in a part of the surface region of the n ^-type silicon carbide epitaxial layer 2. However, this n-type high concentration region 5 may or may not be formed over the entire surface of the substrate. The state up to this point is shown in FIG.

Next, a p-type silicon carbide epitaxial layer 6 is formed by epitaxial growth on the surface of the n ^- type silicon carbide epitaxial layer 2. After the p-type silicon carbide epitaxial layer 6 is formed by epitaxial growth, a p-type impurity such as aluminum may be further ion-implanted into the channel region of the p-type silicon carbide epitaxial layer 6.

Next, an ion implantation mask having a predetermined opening is formed on the surface of the p-type silicon carbide epitaxial layer 6 by photolithography, for example, an oxide film. N-type impurities such as nitrogen (N) and phosphorus (P) are ion-implanted into this opening to form an n ⁺ -type source region 7 on a part of the surface of the p-type silicon carbide epitaxial layer 6. The n ⁺ -type source region 7 is formed only in the active region 40. Next, the ion implantation mask used to form the n ⁺ -type source region 7 is removed. A new ion implantation mask is formed, and p-type impurities such as aluminum (Al) and boron (B) are ion-implanted to form a p ⁺ -type contact region 8 between adjacent n ⁺ -type source regions 7. The p ⁺ -type contact region 8 is formed only in the active region 40. The state up to this point is shown in FIG. 10.

Next, a trench forming mask having a predetermined opening is formed, for example, from an oxide film, on the surface of the p-type silicon carbide epitaxial layer 6 by photolithography. Next, trenches 16a and 16b are formed by dry etching, penetrating the p-type silicon carbide epitaxial layer 6 and reaching the n ^- type silicon carbide epitaxial layer 2. The bottoms of the trenches 16a and 16b reach the first p ⁺ type base region 3 formed in the n ^- type silicon carbide epitaxial layer 2. The trench 16a is formed in the active region 40, and the trench 16b is formed in the gate pad region 50. Next, the trench forming mask is removed.

Next, p-type impurities such as aluminum are obliquely ion-implanted from the opening of the trench 16a to form a second p ⁺ type base region 4 on a part of the side wall of the trench 16a. A second p ⁺ type base region 4b may be simultaneously formed on the side wall of the trench 16b.

Next, a heat treatment (annealing) is performed in an inert gas atmosphere at about 1700° C. to activate the first p ⁺ type base regions 3, 3b, the second p ⁺ type base region 4, the p ⁺ type contact region 8, and the n ⁺ type source region 7. As described above, each ion implantation region may be activated collectively by a single heat treatment, or may be activated by performing a heat treatment each time an ion implantation is performed. The state up to this point is shown in FIG.

Next, a gate insulating film 9 is formed along the surface of the n ⁺ -type source region 7 and the bottoms and sidewalls of the trenches 16 a, 16 b. This gate insulating film 9 may be formed by thermal oxidation at a temperature of about 1000° C. in an oxygen atmosphere. Alternatively, this gate insulating film 9 may be formed by a method of deposition by a chemical reaction such as high temperature oxidation (HTO).

Next, a polycrystalline silicon film doped with, for example, phosphorus atoms is provided on the gate insulating film 9. This polycrystalline silicon film may be formed so as to fill the trenches 16a and 16b. This polycrystalline silicon film is patterned by photolithography and left inside the trenches 16a and 16b to form the gate electrode 10. The state up to this point is shown in FIG. 12.

Next, for example, phosphorus glass is formed to a thickness of about 1 μm so as to cover the gate insulating film 9 and the gate electrode 10, forming the interlayer insulating film 11. The interlayer insulating film 11 and the gate insulating film 9 are patterned by photolithography to form contact holes exposing the n ⁺ type source region 7 and the p type silicon carbide epitaxial layer 6. Then, a heat treatment (reflow) is performed to flatten the interlayer insulating film 11. In addition, after forming the contact holes in the interlayer insulating film 11, a barrier metal made of titanium (Ti), titanium nitride (TiN), or a laminate of titanium and titanium nitride may be formed. In this case, a contact hole exposing the n ⁺ type source region 7 is also provided in the barrier metal. When forming the gate wiring electrode 15, for example, a polycrystalline silicon film doped with phosphorus atoms and a process of forming, for example, phosphorus glass to a thickness of about 1 μm as the interlayer insulating film 11B are added thereafter.

Next, a conductive film that will become the source electrode 12 is formed in the contact hole provided in the interlayer insulating film 11 and on the interlayer insulating film 11. The conductive film is, for example, a nickel (Ni) film. Then, a heat treatment is performed at a temperature of, for example, about 970°C to silicide the nickel film inside the contact hole to form the source electrode 12. Then, the unreacted nickel film is selectively removed, leaving the source electrode 12 only in the contact hole, for example.

Next, a source electrode pad (not shown) is formed so as to fill the contact hole. A part of the metal layer deposited to form the source electrode pad may be used as the gate electrode pad 14. On the back surface of the n ⁺ type silicon carbide substrate 1, a metal film such as a nickel (Ni) film or a titanium (Ti) film is formed on the contact portion of the back surface electrode 13 by using sputter deposition or the like. This metal film may be laminated by combining a plurality of Ni films and Ti films. Then, annealing such as rapid thermal annealing (RTA) is performed so that the metal film is silicided to form an ohmic contact. Then, a thick film such as a laminated film in which, for example, a Ti film, a Ni film, and gold (Au) are laminated in order is formed by electron beam (EB) deposition or the like to form the back surface electrode 13.

In the above-mentioned epitaxial growth and ion implantation, for example, nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), etc., which are n-type for silicon carbide, may be used as n-type impurities (n-type dopants). For example, boron (B), aluminum (Al), gallium (Ga), indium (In), thallium (Tl), etc., which are p-type for silicon carbide, may be used as p-type impurities (p-type dopants). In this way, the trench-type MOSFET 70 shown in FIG. 1 is completed. Here, an example of the second structure is shown as the gate pad region 50, but other structures can be formed in the same manner.

As described above, according to the first embodiment, the gate pad region is also provided with a trench and a first p ⁺ -type base region covering the bottom surface of the trench. This allows the pn interfaces between the n ^- -type silicon carbide epitaxial layer and the first p ⁺ -type base region in the active region and the gate pad region to be at the same depth from the surface of the silicon carbide semiconductor substrate. This prevents avalanche current from concentrating in the gate pad region, making it possible to maintain the breakdown voltage of the gate pad region and improve the reliability of the gate insulating film.

(Embodiment 2)
Fig. 13 is a cross-sectional view showing the structure of an active region and a gate pad region of a silicon carbide semiconductor device according to embodiment 2. Fig. 14 is a top view showing the structure of a silicon carbide semiconductor device according to embodiment 2. Fig. 13 is a cross-sectional view of the A-A' cross section of Fig. 14. The silicon carbide semiconductor device according to embodiment 2 differs from the silicon carbide semiconductor device according to embodiment 1 in that the width of trench 16b in gate pad region 50 is wider than the width of trench 16a in active region 40, and only one trench 16b is provided in gate pad region 50.

In the trench 16b in the gate pad region 50, the size of the trench 16b is slightly larger than that of the gate electrode pad 14. That is, the width of the trench 16b is slightly wider than that of the gate electrode pad 14, and the depth (length in the z direction) of the trench 16b is slightly longer than that of the gate electrode pad 14. A polycrystalline silicon film spreads over the entire surface of the back electrode 13 side of the gate electrode pad 14 as the gate electrode 10 in the trench 16b via the interlayer insulating film 11. The gate electrode 10 may be slightly smaller than the gate electrode pad 14. For example, if each side of the gate electrode 10 is about 10% smaller than the gate electrode pad 14, it can be considered that the polycrystalline silicon film spreads over the entire surface of the lower part of the gate electrode pad 14. In addition to polycrystalline silicon, the gate electrode 10 may be made of a high melting point metal such as titanium or tungsten, its silicide, its nitride, or a laminated film of these. Here, a contact hole may be provided in the interlayer insulating film 11, and the gate electrode 10 in the trench 16b and the gate electrode pad 14 may be electrically connected. This facilitates contact with the first p ⁺ type base region 3 at the bottom of the trench 16b, and the protection capability of the gate insulating film 9 in the gate pad region 50 is improved compared to the first embodiment. The trench 16b in the gate pad region 50 may also have the second p ⁺ type base region 4 selectively provided on one sidewall as in the third structure of the first embodiment. Also, the second p ⁺ type base region 4 may be selectively provided on both sidewalls as in the fifth structure of the first embodiment.

Moreover, the outermost trench 16a of the active region 40 does not have the n ⁺ type source region 7 provided on the gate pad region 40 side, and is in contact with the p type silicon carbide epitaxial layer 6. This makes it possible to easily extract holes from the first p ⁺ type base region 3 of the gate pad region 50.

The first p ⁺ type base region 3b is provided over the entire bottom surface of the trench 16b. Because the width of the trench 16b is wide, the first p ⁺ type base region 3b formed under the trench 16b has a higher impurity concentration than the first p ⁺ type base region 3 formed under the trench 16a of the active region 40. This is because, even if the trench 16b is formed by the same manufacturing method as the trench 16a, the proportion of impurities injected by ion implantation that are absorbed by the sidewall of the mask is low. Furthermore, because the width of the trench 16b is wide, it is formed deeper than the trench 16a. In this way, by providing the first p ⁺ type base region 3b with a high impurity concentration and a deep depth, holes tend to concentrate in the trench 16b, making it easier to control the holes. For example, in FIG. 13, there is only one wide trench 16b, but there may be two or more wide trenches 16b. In this case, a structure for extracting holes can be provided in the region between the trenches 16b, and holes can be controlled.

(Method of Manufacturing Silicon Carbide Semiconductor Device According to Second Embodiment)
The silicon carbide semiconductor device according to the second embodiment can be manufactured by forming one or more trenches 16b in the gate pad region 50, the width of which is wider than the width of the trenches 16a in the active region 40, in the manufacturing method of the silicon carbide semiconductor device according to the first embodiment. Moreover, instead of the step of forming the first p ⁺ -type base region 3b by ion implantation in Fig. 9, it is possible to form the first p ⁺ -type base region 3b having a high impurity concentration and a large depth by implanting ions into the bottom surfaces of the trenches 16a, 16b after the formation of the trenches 16a, 16b.

As described above, according to the second embodiment, the same effects as those of the first embodiment can be obtained. Furthermore, in the second embodiment, the width of the trench in the gate pad region is set wider than the width of the trench in the active region. This makes it easier to contact the first p ⁺ -type base region at the bottom of the trench, and the protection capability of the gate insulating film in the gate pad region is higher than that of the first embodiment.

The present invention can be modified in various ways without departing from the spirit of the present invention. In each of the above-mentioned embodiments, for example, the dimensions and impurity concentration of each part are set in various ways according to the required specifications. In addition, in each of the above-mentioned embodiments, the case where silicon carbide is used as the wide band gap semiconductor is described as an example, but the present invention can also be applied to wide band gap semiconductors other than silicon carbide, such as gallium nitride (GaN). In addition, the present invention can also be applied to semiconductors other than wide band gap semiconductors, such as silicon (Si) and germanium (Ge). In addition, in each of the embodiments, the first conductivity type is n-type and the second conductivity type is p-type, but the present invention is similarly valid even if the first conductivity type is p-type and the second conductivity type is n-type.

As described above, the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device according to the present invention are useful for power semiconductor devices used in power conversion devices such as inverters, power supply devices for various industrial machines, and igniters for automobiles.

1, 101 n ⁺ type silicon carbide substrate 2, 102 n ^- type silicon carbide epitaxial layer 2a Lower n ^- type silicon carbide epitaxial layer 2b Upper n ^- type silicon carbide epitaxial layer 3, 3b, 103 First p ⁺ type base region 4, 4b, 104 Second p ⁺ type base region 5, 105 N type high concentration region 6, 106 P type silicon carbide epitaxial layer 7, 107 n ⁺ type source region 8, 108 P ⁺ type contact region 9, 9b, 109 Gate insulating film 10, 10b, 110 Gate electrode 11, 111 Interlayer insulating film 12, 112 Source electrode 13, 113 Back electrode 14, 114 Gate electrode pad 15, 115 Gate electrode wiring 16a, 16b, 116 Trench 40 140 Active region 50 150 Gate pad region 70, 170 Trench MOSFET

Claims (11)

a first conductivity type semiconductor substrate having an active portion and a gate pad portion;
a first semiconductor layer of a first conductivity type provided on a front surface of the semiconductor substrate and having a lower impurity concentration than the semiconductor substrate;
a second semiconductor layer of a second conductivity type selectively provided on a surface of the first semiconductor layer opposite to the semiconductor substrate;
Equipped with
The active portion is
a first semiconductor region of a first conductivity type selectively provided in a surface layer of the second semiconductor layer on the opposite side to the semiconductor substrate;
a first trench penetrating the first semiconductor region or the second semiconductor layer and reaching the first semiconductor layer;
a first gate electrode provided inside the first trench via a gate insulating film;
an interlayer insulating film provided on the first gate electrode;
a first electrode provided on a surface of the second semiconductor layer and the first semiconductor region;
A second electrode provided on a rear surface of the semiconductor substrate;
a second semiconductor region of a second conductivity type provided in contact with a bottom portion of the first trench;
Equipped with
The gate pad portion is
a second trench penetrating the second semiconductor layer and reaching the first semiconductor layer;
a second gate electrode provided inside the second trench via an insulating film;
a fourth semiconductor region of a second conductivity type provided so as to be in contact with a bottom portion of the second trench;
a gate electrode pad electrically connected to the second gate electrode;
Equipped with
a polycrystalline silicon film is provided between the gate electrode pad and the semiconductor substrate ;
the insulating film is also provided on a surface of the semiconductor substrate in a mesa region between adjacent second trenches;
a gate electrode formed on the insulating film on the surface of the mesa region ; a first conductivity type semiconductor substrate having an active portion and a gate pad portion;
a first semiconductor layer of a first conductivity type provided on a front surface of the semiconductor substrate and having a lower impurity concentration than the semiconductor substrate;
a second semiconductor layer of a second conductivity type selectively provided on a surface of the first semiconductor layer opposite to the semiconductor substrate;
Equipped with
The active portion is
a first semiconductor region of a first conductivity type selectively provided in a surface layer of the second semiconductor layer on the opposite side to the semiconductor substrate;
a first trench penetrating the first semiconductor region or the second semiconductor layer and reaching the first semiconductor layer;
a first gate electrode provided inside the first trench via a gate insulating film;
an interlayer insulating film provided on the first gate electrode;
a first electrode provided on a surface of the second semiconductor layer and the first semiconductor region;
A second electrode provided on a rear surface of the semiconductor substrate;
a second semiconductor region of a second conductivity type provided in contact with a bottom portion of the first trench;
Equipped with
The gate pad portion is
a second trench penetrating the second semiconductor layer and reaching the first semiconductor layer;
a second gate electrode provided inside the second trench via an insulating film;
a fourth semiconductor region of a second conductivity type provided so as to be in contact with a bottom portion of the second trench;
a gate electrode pad electrically connected to the second gate electrode;
Equipped with
a polycrystalline silicon film is provided between the gate electrode pad and the semiconductor substrate;
The semiconductor device according to claim 1, wherein the second trench extends in a direction parallel to a wire connected to the gate pad portion. a first conductivity type semiconductor substrate having an active portion and a gate pad portion;
a first semiconductor layer of a first conductivity type provided on a front surface of the semiconductor substrate and having a lower impurity concentration than the semiconductor substrate;
a second semiconductor layer of a second conductivity type selectively provided on a surface of the first semiconductor layer opposite to the semiconductor substrate;
Equipped with
The active portion is
a first semiconductor region of a first conductivity type selectively provided in a surface layer of the second semiconductor layer on the opposite side to the semiconductor substrate;
a first trench penetrating the first semiconductor region or the second semiconductor layer and reaching the first semiconductor layer;
a first gate electrode provided inside the first trench via a gate insulating film;
an interlayer insulating film provided on the first gate electrode;
a first electrode provided on a surface of the second semiconductor layer and the first semiconductor region;
A second electrode provided on a rear surface of the semiconductor substrate;
a second semiconductor region of a second conductivity type provided in contact with a bottom portion of the first trench;
Equipped with
The gate pad portion is
a second trench penetrating the second semiconductor layer and reaching the first semiconductor layer;
a second gate electrode provided inside the second trench via an insulating film;
a fourth semiconductor region of a second conductivity type provided so as to be in contact with a bottom portion of the second trench;
a gate electrode pad electrically connected to the second gate electrode;
Equipped with
a polycrystalline silicon film is provided between the gate electrode pad and the semiconductor substrate;
a gate electrode formed on the semiconductor substrate and having a first insulating film and a second insulating film formed on the first insulating film; a first conductivity type semiconductor substrate having an active portion and a gate pad portion;
a first semiconductor layer of a first conductivity type provided on a front surface of the semiconductor substrate and having a lower impurity concentration than the semiconductor substrate;
a second semiconductor layer of a second conductivity type selectively provided on a surface of the first semiconductor layer opposite to the semiconductor substrate;
Equipped with
The active portion is
a first semiconductor region of a first conductivity type selectively provided in a surface layer of the second semiconductor layer on the opposite side to the semiconductor substrate;
a first trench penetrating the first semiconductor region or the second semiconductor layer and reaching the first semiconductor layer;
a first gate electrode provided inside the first trench via a gate insulating film;
an interlayer insulating film provided on the first gate electrode;
a first electrode provided on a surface of the second semiconductor layer and the first semiconductor region;
A second electrode provided on a rear surface of the semiconductor substrate;
a second semiconductor region of a second conductivity type provided in contact with a bottom portion of the first trench;
Equipped with
The gate pad portion is
a second trench penetrating the second semiconductor layer and reaching the first semiconductor layer;
a second gate electrode provided inside the second trench via an insulating film;
a fourth semiconductor region of a second conductivity type provided so as to be in contact with a bottom portion of the second trench;
a gate electrode pad electrically connected to the second gate electrode;
a fifth semiconductor region of a second conductivity type provided in the first semiconductor layer so as to be in contact with a side wall of the second trench and electrically connecting the second semiconductor region and the fourth semiconductor region;
Equipped with
a polycrystalline silicon film is provided between the gate electrode pad and the semiconductor substrate;
The fourth semiconductor region has a higher impurity concentration than the second semiconductor region. The semiconductor device according to any one of claims 1 to 4, characterized in that it comprises a third semiconductor region of a second conductivity type that is provided in the first semiconductor layer so as to contact at least one sidewall of the first trench in a second direction perpendicular to a first direction parallel to the extension direction of the first trench, and electrically connects the second semiconductor region and the second semiconductor layer. The semiconductor device according to claim 5 , wherein the third semiconductor region is provided in a plurality of regions spaced apart from one another in the first semiconductor layer. The semiconductor device according to any one of claims 1 to 4, characterized in that it further comprises a fifth semiconductor region of a second conductivity type provided in the first semiconductor layer so as to contact a side wall of the second trench and electrically connects the second semiconductor region and the fourth semiconductor region. The semiconductor device according to claim 7 , wherein the fifth semiconductor region is provided in the first semiconductor layer so as to be in contact with both side walls of the second trench. 9. The semiconductor device according to claim 1, wherein the second trench is wider than the first trench. 5. The semiconductor device according to claim 1, wherein the second trench is deeper than the first trench. The semiconductor device according to any one of claims 1 to 10, characterized in that the first trench provided at the outermost periphery of the active section does not have the first semiconductor region provided on the sidewall on the gate pad section side in a second direction perpendicular to a first direction parallel to the extension direction of the first trench.

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