JP2005276978A - Ohmic electrode structure manufacturing method, ohmic electrode structure, semiconductor device manufacturing method, and semiconductor device - Google Patents

Abstract

The present invention is advantageous in miniaturization and prevents resist contamination.
A high-concentration impurity region 2 selectively formed on a surface of a SiC substrate 1, a thick insulating film 3 placed on the SiC substrate 1, and a high-concentration impurity region 2 in the thick insulating film 3. The contact window 4 opened to expose the surface of the contact window 4, the heating reaction layer 5 disposed in a self-aligned manner on the inner bottom of the contact window 4, the surface of the heating reaction layer 5 in contact with the contact window 4, and An ohmic electrode structure having a wiring conductor 6 extended to the upper part of the thick insulating film 3.
[Selection] Figure 1

Description

  The present invention relates to an ohmic electrode structure manufacturing method, an ohmic electrode structure, a semiconductor device manufacturing method, and a semiconductor device.

  Silicon carbide (SiC) can form a pn junction, has a wider forbidden band Eg than other semiconductor materials such as silicon (Si) and gallium arsenide (GaAs), and is 2.23 eV, 6H in 3C-SiC. A value of about 2.93 eV for -SiC and about 3.26 eV for 4H-SiC has been reported. In addition, SiC is thermally, chemically and mechanically stable and has excellent radiation resistance, so it can be used not only in light-emitting elements and high-frequency devices but also in harsh conditions such as high temperatures, high power, and radiation irradiation. As a power semiconductor device (power device) exhibiting high reliability and stability, application in various industrial fields is expected.

  In particular, it has been reported that a high breakdown voltage MOSFET (metal-oxide-semiconductor field effect transistor) using SiC has a lower on-resistance in principle than a MOSFET using Si. It has also been reported that the forward voltage drop of a high voltage Schottky diode using SiC is lower than that of Si. As is well known, the on-resistance of a power device and the switching speed are in a trade-off relationship. However, according to the power device using SiC, there is a possibility that low on-resistance and high switching speed can be achieved at the same time.

  Reduction of the contact resistance ρc of the ohmic contact is an important factor for reducing the on-resistance of the power device using SiC. In particular, in order to reduce the on-resistance, a method of subdividing the main electrode region of the power device and arranging it on the SiC substrate at a high density is also employed. In order to reduce the on-resistance of such a finely sized power device, it is extremely important to obtain a low contact resistance ρc inside a fine opening (contact window).

  An example of such a low resistance n-type SiC ohmic electrode structure is described in Patent Document 1 below. This ohmic electrode structure is characterized by a remarkably high suitability for structures such as power devices and high-frequency devices and its manufacturing process compared to the prior art. Several power MOSFETs and high-frequency MESFETs (metal-semiconductor field effect transistors) using the body have been reported (for example, refer to Non-Patent Document 1 below).

  The ohmic electrode structure includes an n-type SiC region selectively formed on the surface of the SiC substrate, a field insulating film (or an interlayer insulating film, etc.) placed on the SiC substrate, and the field insulating film An electrode film and an opening part of the field insulating film which are arranged with a certain gap (side wall gap) from the field insulating film inside the opening part (contact window) opened so as to expose the surface of the n-type SiC region A heating reaction layer disposed between the electrode film and the n-type SiC region with a sidewall gap from the field insulating film, and in contact with the surface of the electrode film inside the opening of the field insulating film, and The wiring conductor piece extends to the upper part of the field insulating film. The field insulating film is composed of a laminated insulating film of a thin (5 to 40 nm thick) thermal oxide film of an SiC substrate and an upper insulating film made of an insulating film having a composition or density different from that of the thermal oxide film. The first conductor film that is the base material of the electrode film is Ni, Co, titanium (Ti), chromium (Cr), tantalum (Ta), tungsten (W), molybdenum (Mo), or one or more than one It is composed of a metal film, an alloy film, a compound film, or a composite film or a laminated film selected from metals. The heating reaction layer embedded between the electrode film and the n-type SiC region is a layer formed by a heating reaction between the n-type SiC region and the first conductor film that is a base material of the electrode film. The constant gap constituting the sidewall gap is controlled to a value smaller than the thickness of the field insulating film.

Next, the manufacturing process of the conventional ohmic electrode structure will be described.
(A) First, an SiO ₂ film having a thickness of about 1.5 μm is deposited on the entire surface of the 4H—SiC substrate by the CVD method, and a photoresist is spin-coated thereon. Then, the SiO ₂ film deposited on the n-type SiC region formation planned region is selectively removed by a well-known photolithography method and wet etching technique to form an ion implantation mask film.

(B) Then, an ion implantation through film made of a thin SiO ₂ film is again deposited on the entire surface of the ion implantation mask film by the CVD method. The ion implantation through film is a film for adjusting a projection range (depth) Rp at the time of ion implantation described later. Under the conditions of ³¹ P ⁺ (phosphorus ion) implantation described later, the thickness of the ion implanted through film is 20 to 25 nm. After depositing the ion-implanted through film, n-type impurity ions such as ³¹ P ⁺ , ¹⁴ N ⁺ (nitrogen ions) and ⁷⁵ As ⁺ (arsenic ions) are deposited on the entire surface of the SiC substrate, and at least the impurity density of the surface of the SiC substrate is 1. × becomes ¹⁰ 20 / cm ³ or more, and ion implantation so as not to impair the crystallinity of the SiC substrate. Implantation of n-type impurity ions, the SiC substrate heated to 500 ° C., it is preferred to inject the multiple stages while changing the dose amount [Phi / acceleration energy E _AC. For example, the dose Φ / acceleration energy EAC condition when ³¹ P ⁺ is implanted into a SiC substrate in multiple stages is as follows:
First ion implantation Φ = 5 × 10 ¹⁴ cm ⁻² / E _AC = 40 keV;
Second ion implantation Φ = 5 × 10 ¹⁴ cm ⁻² / E _AC = 70 keV;
Third ion implantation Φ = 1 × 10 ¹⁵ cm ⁻² / E _AC = 100 keV;
Fourth ion implantation Φ = 1 × 10 ¹⁵ cm ⁻² / E _AC = 150 keV;
Fifth ion implantation Φ = 2 × 10 ¹⁵ cm ⁻² / E _AC = 200 keV;
Sixth ion implantation Φ = 2 × 10 ¹⁵ cm ⁻² / E _AC = 250 keV.

(C) When the six-stage multi-stage ion implantation is completed, the ion implantation mask film and the ion implantation through film are entirely removed with hydrofluoric acid (HF). When a rapid heat treatment is performed at 1700 ° C. for 1 minute in an atmospheric pressure Ar atmosphere, the ion-implanted ³¹ P ⁺ is activated, and an n-type SiC region having a high impurity density is selectively formed. The diffusion depth of the n-type SiC region generated under the above ion implantation conditions and activation heat treatment conditions is approximately 350 nm.

(D) Then, the SiC substrate is sufficiently cleaned using a predetermined cleaning method such as an RCA cleaning method well known in the silicon (Si) process. The RCA cleaning method is a traditional method for cleaning a semiconductor Si substrate, which is performed by combining immersion treatment with a H ₂ O ₂ + NH ₄ OH mixed solution (SC-1) and a H ₂ O ₂ + HCl mixed solution (SC-2). . Then, the sufficiently cleaned surface of the SiC substrate is thermally oxidized in a dry oxygen atmosphere at 1000 ° C. to 1150 ° C. to grow a thermal oxide film having a thickness of 5 to 40 nm on the surface. Note that an atmosphere containing water vapor or nitrogen oxidizing gas may be used instead of the dry oxygen atmosphere. If thermal oxidation is performed in dry oxygen at a heat treatment temperature of 1150 ° C. for 3 hours, a thermal oxide film 3 of 35 to 40 nm is obtained. If thermal oxidation is performed at 1150 ° C. for 2 hours in a wet atmosphere using water vapor, a thermal oxide film 3 of 30 to 35 nm can be obtained. In the case of thermal oxidation in a wet atmosphere using water vapor, it is then preferable to anneal at 1150 ° C. for about 30 minutes in argon (Ar). In order to make the thickness of the thermal oxide film 3 20 nm or less, the oxidation temperature may be lowered or the oxidation time may be shortened.

  (E) Next, an upper insulating film made of 400 nm silicate glass (SiO 2, PSG, etc.) is deposited on the thermal oxide film by atmospheric pressure CVD to form a field insulating film having a two-layer structure. It is desirable that the total thickness of the field insulating film, which is the sum of the thickness of the thermal oxide film and the thickness of the upper insulating film, be at least 100 nm.

(F) Next, a photoresist having a thickness of 1 to 2 [mu] m is applied as a "mask material" to the surface of the field acid insulating film using a spinner. Then, using a predetermined photomask (reticle), the mask material (photoresist) is selectively exposed and developed to remove the portion of the photoresist corresponding to the opening, thereby forming a window. Subsequently, using the photoresist mask pattern as an etching mask, the SiC substrate is immersed in a BHF solution and wet-etched to form an opening in the field insulating film. When forming a fine opening, dry etching using gas plasma is preferable. For example, various dry etching methods such as a reactive ion etching (RIE) method using CHF ₃ or C ₂ F ₆ as an etchant and an electron cyclotron resonance ion etching (ECR ion etching) can be used. In this case, dry etching is first performed, and switching to wet etching is performed when the field insulating film is left several tens of nm thick. Regardless of whether the wet etching alone or the combination of dry etching and wet etching is used, the most important formation point is the wet etching or the dry etching that is slightly excessive (overetching). The opening of the field insulating film becomes larger than the opening of the photoresist so that an undercut portion is generated. For example, after the exposure of the surface of the n-type SiC region is confirmed by visual observation of the etching monitor (by color change), overetching may be added for a predetermined time. Furthermore, in order to control the precise depth of the undercut portion, etching utilizing a gas phase reaction (gas etching) may be used.

  (G) Thereafter, with the photoresist as an etching mask remaining, the BHF solution is completely rinsed (rinsed) with ultrapure water and then dried. Then, the SiC substrate with the resist mask attached is quickly installed in a chamber of a vacuum deposition apparatus, and immediately evacuated to deposit a first conductor film on the surface of the SiC substrate. For example, a Ni film may be deposited by electron beam (EB) as the first conductor film. At this time, since the opening of the field insulating film is formed to be larger than the opening of the photoresist mask as described above, the first conductor film piece (evaporated on the bottom of the opening) ( In the following, the "first conductor piece") is accurately transferred to the slightly smaller shape of the opening of the photoresist mask. Thus, a deposition limited region having a constant distance and a fine dimension is formed between the peripheral edge of the first conductor element piece and the side wall of the opening of the field insulating film. Since this fine deposition limited region is determined by the depth of the undercut portion described above, it can be precisely controlled by the overetching time of the opening etching. The thickness of the first conductor film is set to be thinner than ½ of the diffusion depth of the n-type SiC region below the first conductor film.

  (H) After vacuum deposition of the first conductor film (Ni film), the SiC substrate is taken out from the chamber of the vacuum deposition apparatus. Subsequently, a lift-off method is used to obtain a substrate structure in which the first conductor piece is selectively embedded only in the opening. That is, when the SiC substrate is immersed in an organic solvent such as acetone or a dedicated photoresist stripping solution and the photoresist remaining on the surface of the SiC substrate is completely removed, the first conductor film deposited on the photoresist Since the (Ni film) is also removed together with the photoresist, the first conductor piece selectively remains only inside the opening. As a result, a side wall gap having a fine dimension corresponding to the deposition limited region is formed in a self-aligned manner between the peripheral edge portion of the first conductor element piece and the opening side wall of the field insulating film.

(I) After that, when the SiC substrate is heat-treated in a non-oxidizing atmosphere at 700 ° C. to 1050 ° C. for a short time (about several minutes), the first conductor piece and the SiC substrate react with each other, A heat-reactive layer is generated in the interface region, and excellent ohmic characteristics are realized between the heat-reactive layer and the n-type SiC region. In order to perform heat treatment for a short time of about several minutes, infrared (IR) lamp heating may be used. Here, the “non-oxidizing atmosphere” is an atmosphere that does not contain a gas of a compound containing oxygen such as oxygen (O ₂ ) or water (H ₂ O). Specifically, an ultrahigh purity inert gas atmosphere such as ultrahigh purity argon (Ar) or ultrahigh purity nitrogen (N ₂ ), high vacuum, or the like is suitable as the “non-oxidizing atmosphere”. If even a small amount of oxygen is contained in these heat treatment atmospheres, metal oxides (= insulators) are formed on the surface by heat treatment, or the formation of the heat-reactive layer is hindered. Strict management is necessary. Specifically, the partial pressure of oxygen and water contained in the heat treatment atmosphere is at least about 1 × 10 ⁻³ Pa to 1 × 10 ⁻¹⁰ Pa, preferably 1.0 × 10 ⁻⁵ Pa to 1 × 10 ⁻ It is desirable to be about ¹⁰ Pa. When heat treatment is performed in an ultra-high purity inert gas atmosphere, strict management such as the use of a deoxygenation device or a gas purification device is required in addition to gas pipe baking and leak inspection. Further, when heat treatment is performed in a high vacuum, strictly speaking, the metal surface is oxidized even in a vacuum of about 1 × 10 ⁻⁸ Pa. Therefore, the partial pressure of oxygen and water is set to 1 × 10 6 using a cryopanel or the like. It is preferable to perform heat treatment under an ultra-high vacuum by controlling the pressure to about ⁻⁸ Pa to 1 × 10 ⁻¹⁰ Pa. For example, when a Ni film is used as the first conductor film, a heat reaction layer made of nickel silicide (NiSi _1-X , NiSi ₂ ) and carbon (C) or the like is formed on the first conductor piece by heat treatment. Generated at the bottom (bottom). The upper unreacted first conductor piece that did not become the heating reaction layer becomes an electrode film. Actually, the electrode film is in a state where nickel silicide (Ni ₂ Si) is diffused into unreacted Ni. The reason why the thickness of the first conductor film was set to be thinner than ½ of the thickness of the n-type SiC region below the first conductor film in the step of depositing the first conductor film was that the first conductor piece was completely heated. This is to ensure that the n-type SiC region remains in the lower portion even when it is converted into a heating reaction layer. When the high impurity density n-type SiC region completely disappears, a serious situation occurs in which the contact resistance increases rapidly. The condition of the thickness of the first conductor film is defined to avoid this situation.

  (N) After the heating reaction layer is formed, a second conductor film such as Al is deposited on the entire surface of the SiC substrate. Then, patterning is performed by a photolithography method and an etching technique such as RIE to form a wiring conductor piece, thereby completing an ohmic electrode structure. When the etchant (= etching solution or etching gas) at the time of patterning erodes the Ni-based electrode film, the second conductor film may be disposed so as to always cover the Ni-based electrode film.

JP 2002-93742 A N. Kiritani et al .: Materials Science Forum, 433-436, 2003, 669-672.

  However, in the ohmic electrode structure for the n-type SiC region according to the above-described prior art, the structure is always provided with a certain sidewall gap between the heating reaction layer and the contact window. There is a problem that the unit cell of the transistor becomes larger by an amount corresponding to the gap. In a power device in which several thousand to several tens of thousands of unit cells are arranged in parallel to form one device, even if such a small space in the unit cell is used, the whole area becomes a large wasteful area. . Further, in the structure of the prior art, an unreacted electrode film (= unreacted first conductor piece) deteriorated by the high-temperature heat treatment is left on the heating reaction layer. As a result of the unreacted electrode film being exposed to rapid heating at a high temperature around 1000 ° C., it deteriorates to become a sparse film and the resistance increases. That is, the conventional technique has a problem that the residual electrode base material whose resistance is increased due to deterioration pushes up the net resistance of the contact.

Furthermore, in the manufacturing process of the ohmic electrode structure based on the prior art, a photoresist or the like is used to dispose the first conductor film piece on the bottom of the opening of the field insulating film in a self-aligning manner. Because it was configured to use the lift-off method,
(1) As the contact miniaturization advances and the area of the opening becomes smaller, it becomes increasingly difficult to clean the substrate, resulting in poor contact and increased cleaning costs.
(2) Vapor deposition equipment for the Si integrated circuit process that prohibits the introduction of a substrate with a photoresist cannot be shared, and a vapor deposition equipment dedicated to the same process and a dedicated clean room space for installing it must be prepared. ,
There was a problem.

Here, the reason why cleaning becomes difficult will be described in more detail. In the step (h), when the unnecessary first conductor film formed on the photoresist is removed by lift-off, the removed conductor is removed. Part of the membrane is crushed into small pieces and adheres to the bottom of the opening. Since chemical cleaning with etching results in the removal of the first conductor film piece at the same time, physical cleaning such as ultrasonic vibration and scrubbing can be selected to remove the harmful adhered conductor film piece at the bottom. I do not get. However, if the diameter of the opening of the field insulating film is reduced, the physical impact hardly reaches the bottom of the opening, and the effect of removing the metal powder adhering to the bottom is greatly reduced.
The present invention has been made in order to solve the problems of such conventional ohmic electrode structures, semiconductor devices, and manufacturing methods thereof, and the object thereof is advantageous for miniaturization, and ohmic that can prevent resist contamination. An object of the present invention is to provide an electrode structure manufacturing method, an ohmic electrode structure, a semiconductor device manufacturing method, and a semiconductor device.

  In order to solve the above problems, the present invention includes a step of bringing an electrode base material into contact with a high-concentration impurity region on the surface of the silicon carbide substrate, and heat-treating the silicon carbide substrate to include the electrode base material and the high-concentration impurity region. A first heat treatment step of forming a heat reaction layer precursor layer between the silicon carbide substrate, a step of removing the unreacted electrode base material left on the heat reaction layer precursor layer, A second heat treatment step of heat-treating the silicon carbide substrate after the step to convert the heat-reactive layer precursor layer at the bottom of the contact window into the heat-reactive layer; and a heat-reactive layer precursor after the second heat-treatment step And a step of disposing a wiring conductor on the upper part of the layer.

  According to the present invention, it is advantageous for miniaturization and resist contamination can be prevented.

Hereinafter, first to fifth embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones. Accordingly, specific thicknesses and dimensions should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.
(First embodiment)
<Ohmic electrode structure>
As shown in FIGS. 1 to 3, the ohmic electrode structure according to the first embodiment of the present invention is selectively formed on a SiC substrate (for example, 4H—SiC) 1 and the surface of the SiC substrate 1. n-type or p-type high-concentration impurity region 2, thick insulating film 3 placed on SiC substrate 1, and contact window 4 opened to expose the surface of high-concentration impurity region 2 in thick insulating film 3 The heating reaction layer 5 arranged at the bottom of the contact window 4 and the wiring extending in contact with the surface of the heating reaction layer 5 and extending to the top of the thick insulating film 3 inside the contact window 4 of the thick insulating film 3 The conductor 6 is comprised.
The conductivity type of the SiC substrate 1 can be arbitrarily selected depending on the semiconductor device to which the present ohmic electrode structure is applied. Further, the crystal system of the substrate is not limited to 4H—SiC, and may be 6H—SiC, 3C—SiC, or other crystal systems.

The selectively formed high concentration impurity region 2 has an impurity concentration of at least 1 × 10 ¹⁸ / cm ³ to 2 × 10 ²¹ / cm ³ , preferably 1 × 10 ¹⁹ / cm at the contact point with the heating reaction layer 5. It is set in ^{cm 3 ~8 × 10 20 / cm} 3. The doping means may be an ion implantation / activation method, a high impurity concentration epitaxial growth method, or other methods. Impurities to be doped are P (phosphorus) and N (nitrogen) in the case of n-type, and Al (aluminum) and B (boron) in the case of p-type, but the present invention is of course limited to these. It is not a thing. The surface position of the high-concentration impurity region 2 may be arranged so as to be horizontal with respect to the surrounding SiC substrate 1 as shown in FIG. 1, or may be convex as shown in FIG. 2 or concave as shown in FIG. It can also be arranged.

The thick insulating film 3 is a dielectric having a thickness and an insulating property so that the wiring conductor 6 disposed on the insulating film 3 does not adversely affect the characteristics of the device formed on the surface of the lower SiC substrate 1. In a real device, it is a film called a field insulating film or an interlayer insulating film. Suitable films for this purpose include a thermal oxide film of SiC, NSG (additive silicate glass = SiO ₂ ), PSG (phosphosilicate glass) film, BSG (borosilicate glass), BPSG (borophosphosilicate glass) or Si. An insulating film having an element other than the above, a laminated film of these, and a mixed film can be used. When it is desired to reduce the contact resistance as much as possible, an NSG film having a thickness of several hundred nm is laminated on a thin SiC thermal oxide film having a thickness of several tens of nm by a CVD method as described in Patent Document 1 of the conventional example. Good results can be obtained with this structure. A special feature of the thick insulating film 3 is that the electrode base material is once deposited on the surface, heat-treated at a relatively low temperature, and then removed (details will be described later in the description of the manufacturing process). This is a point formed by tracing This point is greatly different from the thick insulating film (field insulating film) described in Patent Document 1 of the conventional example. The thickness of the thick insulating film 3 is desirably 100 nm to 3 μm. In particular, the thickness is desirably 300 nm or more. Further, in the case of a power semiconductor device with a high breakdown voltage, the thickness may be 800 nm or more. However, if the thick insulating film 3 becomes too thick, cracks and the like are generated, so that 3 μm or more is not preferable. In particular, when aiming at miniaturization, about 1.5 μm is a practical upper limit of the thickness of the thick insulating film 3.

  As will be described later in detail, the heating reaction layer 5 is a heating reaction generated by subjecting the high-concentration impurity region 2 (or SiC substrate 1) and the electrode base material to a heating solid phase reaction (first heat treatment) at a relatively low temperature. The reaction electrode layer is formed by reheating (second heat treatment) the layer precursor at a higher temperature, and the main component thereof is composed of conductive carbide, silicide, or carbide carbide of the electrode base material. As an electrode base material, use a metal film, an alloy film, a compound film, or a composite film or a laminated film thereof containing an element that generates a conductive silicide or carbide by reacting with SiC at a temperature of 1200 ° C. or lower. Can do. For example, in addition to Ni and Co, one or more metals such as titanium (Ti), chromium (Cr), tantalum (Ta), niobium (Nb), tungsten (W), molybdenum (Mo), and Al are included. A metal film, an alloy film, a compound film, or a composite film or a laminated film thereof. The heating reaction layer 5 is spread over the entire SiC exposed region at the bottom of the contact window 4 and does not necessarily require a contact window side wall gap as shown in Patent Document 1 of the conventional example (the structure of the present invention). Second difference different from the conventional example of Patent Document 1). This means that the space of the side wall gap can be omitted, and the miniaturization of the contact structure can be promoted accordingly. Thus, it can be said that the structure of the ohmic electrode structure according to the present invention solves the problem of the prior art that the existence of the side wall gap has hindered the miniaturization of the contact. Naturally, the heating reaction layer 5 is arranged such that the contact surface between the heating reaction layer 5 and the SiC substrate 1 is shallower than the depth of the high-concentration impurity region 2.

The wiring conductor 6 is a conductive material having a specific resistance smaller than that of the unreacted electrode base material. For example, aluminum (Al), aluminum-silicon (Al-Si) eutectic, aluminum-copper-silicon (Al -Cu-Si) eutectic, copper (Cu), titanium-tungsten (Ti-W) alloy, or the like can be used. The wiring conductor 6 is a wiring member that connects the ohmic contact shown in FIGS. 1 to 3 to other parts, and functions as a main electrode wiring of the semiconductor device. In order to ensure reliability, a structure in which the contact window 4 is disposed so as to cover it is desirable. In the power device, comb-tooth-shaped, hexagonal, square, or circular unit cells are arranged on the SiC substrate 1 and connected in parallel by the same wiring conductor 6 to ensure current capacity.
The third difference between the structure of the ohmic structure of the present invention and that of the conventional example of Patent Document 1 is that the high-resistance unreacted electrode base material is not on the heating reaction layer 5 and is directly connected to the wiring conductor 6. This is the point where low resistance is achieved. In other words, the structure of the ohmic electrode structure according to the present invention is the cause of the unreacted electrode base material (electrode film referred to in the prior art) having a high specific resistance boosting the net contact resistance of the contact in Patent Document 1 of the conventional example. It solves the problem of becoming.

<< Method for Producing Ohmic Electrode Structure >>
Next, the manufacturing process of the ohmic electrode structure of FIG. 1 according to the first embodiment of the present invention will be described with reference to the process cross-sectional views shown in FIGS. 4 (a) to 6 (k).
(A) First, a SiO ₂ film having a thickness of about 1.5 μm is deposited on the entire surface of the SiC substrate 1 by the CVD method, and the SiO ₂ film deposited on the region where the high-concentration impurity region is to be formed is formed by a known photo process. An ion implantation mask film 33 as shown in FIG. 4A is formed by selective removal by lithography and dry etching techniques.
(B) Then, as shown in FIG. 4B, an ion implantation through film 34 made of a thin SiO ₂ film is again deposited on the entire surface of the ion implantation mask film 33 by the CVD method, and impurity ions 35 are implanted. I do. The ion implantation through film 34 is a film for adjusting a projection range (depth) Rp at the time of ion implantation described later. For example, under the condition of P ⁺ (phosphorus ion) implantation for forming an n-type high concentration impurity region, the thickness of the ion implantation through film 34 is 20 to 25 nm. Under the implantation conditions of the p-type high concentration impurity region Al ⁺ (aluminum ions), the thickness is 15 to 30 nm.

The ion implantation is performed so that the impurity concentration of the SiC substrate 1 becomes 1 × 10 ²⁰ / cm ³ or more and the crystallinity of the SiC substrate 1 is not impaired. For example, in the case of forming a high-concentration impurity region of the n-type in P (phosphorus) is the SiC substrate 1 heated to 500 ° C., it is preferred to inject the multiple stages while changing the dose amount [Phi / acceleration energy E _AC. An example of the dose Φ / acceleration energy _EAC condition when ³¹ P ⁺ is implanted into the SiC substrate 1 in multiple stages is as follows.
First ion implantation Φ = 5 × 10 ¹⁴ cm ⁻² / E _AC = 40 keV
Second ion implantation Φ = 5 × 10 ¹⁴ cm ⁻² / E _AC = 70 keV
Third ion implantation Φ = 1 × 10 ¹⁵ cm ⁻² / E _AC = 100 keV
Fourth ion implantation Φ = 1 × 10 ¹⁵ cm ⁻² / E _AC = 150 keV
Fifth ion implantation Φ = 2 × 10 ¹⁵ cm ⁻² / E _AC = 200 keV
Sixth ion implantation Φ = 2 × 10 ¹⁵ cm ⁻² / E _AC = 250 keV
(C) When such ion implantation is completed, the ion implantation mask film 33 and the ion implantation through film 34 are entirely removed with hydrofluoric acid (HF). Then, when a rapid heat treatment is performed at 1700 ° C. for 1 minute in an atmospheric pressure Ar atmosphere, the ion-implanted impurity ( ³¹ P ^{+ in the} above example) is activated, and as shown in FIG. A high concentration impurity region 2 having an impurity density is selectively formed. The diffusion depth of the n-type high-concentration impurity region 2 generated under the above ion implantation conditions and activation heat treatment conditions is about 350 nm.

The high concentration impurity region 2 having the structure as shown in FIG. 4C is formed by performing trench etching on a predetermined region of the SiC substrate 1 and then epitaxially growing high concentration SiC on the entire surface of the substrate including the same region to form the entire surface of the substrate. It can also be formed by polishing and removing the surface epitaxial layer (leaving only the trench portion), and this method may be selected.
(D) Then, the SiC substrate 1 is sufficiently cleaned by using a predetermined cleaning method such as an RCA cleaning method well known in the silicon (Si) process. The RCA cleaning method is a traditional method for cleaning a semiconductor Si substrate, which is performed by combining immersion treatment with a H ₂ O ₂ + NH ₄ OH mixed solution (SC-1) and a H ₂ O ₂ + HCl mixed solution (SC-2). . Then, a thick insulating film 3 is formed on the surface of the SiC substrate 1 that has been sufficiently cleaned. Here, an example of a thick insulating film composed of a laminate of a thin thermal oxide film and a thick CVD oxide film, which is suitable for forming a low-resistance contact, will be described. The present invention describes such a thick insulating film. It is not limited to the configuration of First, the SiC substrate 1 is thermally oxidized in a dry oxygen atmosphere of 1000 ° C. to 1150 ° C., and a thermal oxide film 31 having a thickness of 5 to 40 nm is grown on the surface as shown in FIG. An atmosphere containing water vapor may be used instead of the dry oxygen atmosphere. In dry oxygen, a thermal oxide film 3 having a thickness of 35 to 40 nm can be obtained by thermal oxidation at a heat treatment temperature of 1150 ° C. for 3 hours. If thermal oxidation is performed at 1150 ° C. for 2 hours in a wet atmosphere using water vapor, a thermal oxide film 3 of 30 to 35 nm can be obtained. In the case of thermal oxidation in a wet atmosphere using water vapor, it is then preferable to anneal at 1150 ° C. for about 30 minutes in argon (Ar). In order to reduce the thickness of the thermal oxide film 3 to 20 nm or less, the oxidation temperature may be lowered or the oxidation time may be shortened.

(E) Next, as shown in FIG. 5E, a CVD oxide film 32 having a thickness of, for example, 400 nm is deposited on the thermal oxide film 31 by an atmospheric pressure CVD method to form a thick insulating film having a two-layer structure. 3 is formed.
(F) Next, a contact window 4 is formed in a predetermined region of the thick insulating film 3 as shown in FIG. 5F by using a well-known photolithography method and dry etching technique. As the dry etching, for example, various means such as a reactive ion etching (RIE) method using CHF ₃ or C ₂ F ₆ as an etchant and electron cyclotron resonance ion etching (ECR ion etching) can be used. In the case of forming an ultra-low resistance contact, it is preferable to perform dry etching first and switch to wet etching using a buffered hydrofluoric acid solution when the field insulating film 3 is left several tens of nm thick. Is obtained. A surfactant or the like may be added to the wet etching solution.
(G) Thereafter, the surface of the substrate 1 contaminated with a residue of photoresist or the like is cleaned by the RCA cleaning described above and dried in a short time. After drying, the SiC substrate 1 is quickly installed in the chamber of the sputtering apparatus and immediately evacuated. The standing time in the atmosphere from contact window opening etching to evacuation is an extremely important factor that determines the magnitude of the contact resistance ρc. If the standing time in the atmosphere is long, a natural oxide film is formed on the surface of the SiC substrate 1 in the opening, or unwanted foreign matter adheres. For this reason, it becomes a big obstacle to the uniform generation of the heating reaction layer, which will be described later, and as a result, the contact resistance ρc is dramatically increased. When the base pressure in the apparatus becomes less than 1.3 × 10 ⁻⁵ Pa, Ar gas is introduced, and a predetermined electrode base material 17 is formed on the entire surface of the SiC substrate 1 as shown in FIG. Film. When forming a low-resistance contact in the n-type region, Ni or Co having a thickness of 20 nm to 100 nm may be deposited. Further, when a low resistance contact is formed in the p-type region, a desirable result can be obtained by using a Ti—Al alloy film. In order to form the electrode base material 17, a chemical vapor deposition means such as vacuum vapor deposition or CVD such as electron beam vapor deposition may be used.

(H) Subsequently, the SiC substrate 1 on which the electrode base material 17 is formed on the entire surface is subjected to a “relatively gentle heat treatment (first heat treatment)” in an inert gas atmosphere such as high-purity Ar or N ₂ . A heating reaction layer precursor layer 18 (FIG. 5H) is formed between electrode base material 17 and SiC substrate 1. The heating reaction layer precursor layer 18 referred to here refers to a lower metal silicide, metal carbide or metal carbide silicide having a high metal composition ratio. When Ni is selected as the electrode base material 17, Ni silicides such as Ni ₃ Si, Ni ₂ Si, Ni ₃ 1Si ₁₂ , and NiSi correspond to this. In addition, “relatively gentle heat treatment” means that an effective heating reaction layer precursor layer 18 is generated between the electrode base material 17 and the SiC substrate 1, while the electrode base material 17 and the thick insulating film 3. Refers to heat treatment that does not cause harmful solid phase reactions. The temperature and time of the first heat treatment that satisfies these two requirements depend on the type of electrode base material 17 and the film forming conditions, and thus cannot be defined unconditionally. The temperature is generally in the range of 350 ° C. to 850 ° C., and the time is in the range of 5 minutes to 12 hours. As an example of an appropriate heat treatment condition of 50 nm Ni deposited with a DC magnetron sputtering apparatus as the electrode base material 17, the heat treatment temperature was 600 ° C. and the heat treatment time was 3 hours. Since the heating reaction layer precursor layer 18 is generated from a solid phase reaction that occurs only in contact with the SiC substrate 1, the precursor layer 18 is automatically aligned with the bottom of the contact window 4. The

  (I) When the first heat treatment is completed, when the SiC substrate 1 is immersed in a predetermined etching solution that dissolves only the electrode base material 17, the unreacted electrode base material 17 is wiped from the substrate surface of the SiC substrate 1, and the contact A structure as shown in FIG. 6I is obtained in which only the heating reaction layer precursor layer 18 is left at the bottom of the window 4. The etching solution used here can be selected as appropriate in accordance with the chemical properties of the electrode base material 17, but when a suitable etchant is not found, sulfuric acid and hydrogen peroxide solution are mixed at a volume ratio of 4: 1. It is convenient to use an etchant. This is because this etchant kept at 100 ° C. dissolves most electrode base materials well and hardly dissolves metal silicides and metal carbides. If the selectivity of the electrode base material 17 with respect to the heating reaction layer precursor layer 18 and the thick insulating film can be sufficiently ensured, the unreacted electrode base material 17 may be removed by using dry etching.

(N) After completely removing the unreacted electrode base material 17, the SiC substrate 1 is again heat-treated at a temperature higher than the temperature of the first heat treatment, and the heated reaction layer precursor layer 18 formed in all steps By promoting the solid-phase reaction of the SiC substrate 1, the heating reaction layer precursor layer 18 is converted into the heating reaction layer 5 whose main component is a thermodynamically stable phase as shown in FIG. Second heat treatment). The atmosphere of the heat treatment is a high purity inert atmosphere similar to the first heat treatment. The temperature and time of the second heat treatment are set in the range of 700 ° C. to 1200 ° C. and 30 seconds to 100 minutes, respectively. In the case of the Ni electrode system precursor described above, a very good result is obtained when the temperature is 950 ° C. to 1050 ° C. and the time is 30 seconds to 2 minutes. When heat treatment is performed under such conditions, lower silicide precursors such as Ni ₃ Si, Ni ₂ Si, Ni ₃₁ Si ₁₂ , and NiSi take in the Si element of the SiC substrate 1 and are the most chemically stable and It changes into a heating reaction layer mainly composed of NiSi _{2 from} which a low resistance contact can be obtained.
(L) When the formation of the heating reaction layer 5 is completed, a wiring conductor film such as Al is formed on the entire surface of the SiC substrate 1 by magnetron sputtering. Then, by patterning with a photolithographic method and an etching technique such as RIE to form the wiring conductor 6 as shown in FIG. 1, the ohmic electrode structure according to the first embodiment is completed.

  As is clear from the above detailed description, the ohmic electrode structure manufacturing method of the present invention is a new self-alignment process (FIG. 5) that does not use any photoresist to dispose the heating reaction layer 5 at the bottom of the contact window. 5 (g) to FIG. 6 (j)) are used. Therefore, the method for manufacturing an ohmic electrode structure according to the present invention is (1) contact miniaturization, which is a problem of the prior art of Patent Document 1 caused by the lift-off method using a photoresist or the like. As the area of the opening becomes smaller, it becomes increasingly difficult to clean the substrate, resulting in poor contact and high cleaning costs. (2) Evaporation apparatus for Si integrated circuit process that resists resist contamination It cannot be shared, and it can be said that it has fundamentally solved the problem that a vapor deposition apparatus dedicated to the same process and a dedicated clean room space for installing the vapor deposition apparatus must be prepared.

Next, a method for manufacturing the ohmic electrode structure of the present invention shown in FIG. 2 will be described with reference to process cross-sectional views shown in FIGS.
(A ′) First, as shown in FIG. 7A, a high-concentration impurity having a predetermined thickness obtained by adding a high-concentration impurity (dopand) to the entire surface of the SiC substrate 1 by a known normal pressure CVD epitaxial growth method. Epitaxial layer 41 is grown. As the type of impurity, N (nitrogen) or P (phosphorus) is suitable for n-type, and Al (aluminum) or B (boron) is suitable for p-type, but other impurity elements may be used. The impurity concentration of this high-concentration impurity layer, here the high-concentration impurity epitaxial layer 41, is made as high as possible unless the crystallinity is impaired. At least 1 × 10 ¹⁹ / cm ³ or more, preferably 1 × 10 ²⁰ / cm ³ is desirable. Instead of providing a high-concentration impurity layer by epitaxial growth, impurity ions are implanted at a high concentration with multistage energy with different acceleration voltages on the entire surface of the SiC substrate 1, and then the impurity is activated to be equivalent to the epitaxial layer. A method of forming a high concentration impurity layer may be adopted.

(B ′) Subsequently, an SiO ₂ film having a thickness of about 2 μm is deposited on the entire surface of the SiC substrate 1 by a CVD method to leave the SiO ₂ film on the region where the high concentration impurity region is to be formed. The mesa etching mask film 42 as shown in FIG. 7B is formed by selective removal using the photolithography method and the dry etching technique.
(C ') Then, the mesa etching mask 42 is used to remove the exposed portion of the surface of the epitaxial layer (= SiC) 41 by well-known ICP (Inductively Coupled-Plasma) etching. When the etching mask 42 is removed with a buffered hydrofluoric acid solution, a convex high concentration impurity region 2 as shown in FIG. 7C is formed.
The manufacturing process up to completion (FIG. 2) after forming the high-concentration impurity region 2 is not different from the processes described in detail in the above (d) to (n), and therefore the description thereof is omitted.

Next, a method for manufacturing the ohmic electrode structure of the present invention shown in FIG. 3 will be described with reference to process cross-sectional views shown in FIGS.
(Ii) First, an SiO ₂ film having a thickness of about 2 μm is deposited on the entire surface of the SiC substrate 1 by a CVD method so that the SiO ₂ film on the region where the high concentration impurity region is to be formed is removed. The photolithography method and the dry etching technique are selectively removed to form a trench etching mask film 45. Subsequently, when the trench etching mask film 45 is used as a mask, the surface of the SiC substrate 1 is etched to a predetermined depth. 8A, a concave high-concentration impurity region planned region 46 is formed, and dry etching such as well-known ICP or RIE (reactive ion etching) is most suitable as a trench etching means.

(B ") After the trench etching is completed, the used trench etching mask film 45 is removed with a buffered hydrofluoric acid solution, and the SiC substrate 1 is sufficiently cleaned using RCA cleaning. A high-concentration impurity layer 47 having a predetermined thickness to which an impurity (dopand) is added is grown by a known atmospheric pressure CVD epitaxial growth method (FIG. 8 (b)). (Phosphorus) Al (aluminum) or B (boron) is suitable for the p-type, but other impurity elements may be used, and the impurity concentration of the high-concentration impurity layer 47 is at least 1 × 10 ¹⁹ / cm ³ or more, preferably 1 × ¹⁰ 20 / cm ³ is desirable. Alternatively, instead of providing a high concentration impurity layer 47 by epitaxial growth, impurities ions on the entire surface of the SiC substrate 1 Implanted at a high concentration in the multi-stage energy, and then to activate the impurity, it may take a method of forming a high-concentration impurity layer 47 equivalent to the epitaxial layer.

Then, the surface of the SiC substrate 1 is subjected to chemical mechanical polishing (CMP) in parallel to remove the high-concentration impurity layer 47 deposited other than the recesses, and the surface of the original SiC substrate 1 is exposed. When the polishing is stopped, as shown in Fig. 8C, the high-concentration impurity region 2 is selectively formed in the recess of the SiC substrate 1. Thereafter, the SiC substrate 1 is sufficiently cleaned by the RCA cleaning described above.
The subsequent manufacturing process is exactly the same as the process described in detail in the above (d) to (n), and thus the description thereof is omitted.

  As apparent from the above description of the manufacturing process, the method for manufacturing the ohmic electrode structure according to the present invention shown in FIGS. 2 and 3 uses no photoresist to dispose the heating reaction layer 5 at the bottom of the contact window 4. Since a new self-alignment process (FIGS. 5 (g) to 6 (j)) that is not used is used, it is caused by the lift-off method using a photoresist or the like, similar to the manufacturing method of the structure of FIG. (1) When the miniaturization of the contact is advanced and the area of the opening is reduced, the cleaning of the substrate becomes increasingly difficult and the contact failure occurs. (2) I don't like resist contamination, and I can't share the vapor deposition equipment for Si integrated circuit process. I have a vapor deposition equipment dedicated to the same process and a clean room space dedicated to installing it. Na Must Re, can be said to be fundamentally solve the problem.

The ohmic electrode structure manufactured in such a configuration exhibits a practically low contact resistance. In order to show this, the results of the contact evaluation for the n-type region of the structure of FIG. 2 using a 50 nm thick Ni electrode as the electrode base material 17 will be introduced. The SiC substrate 1 is p-type 4H—SiC. The high concentration impurity region 2 is an epitaxially grown layer having a thickness of 800 nm to which N (nitrogen) is added at 1.5 × 10 ¹⁹ / cm ³ . The thick insulating film 3 is a laminated film of a dry thermal oxide film having a thickness of 20 nm formed at 1100 ° C. and a PSG film having a thickness of 400 nm formed by atmospheric pressure CVD. The temperature and time of the first and second heat treatments are 550 ° C., 2 hours and 1000 ° C., and 2 minutes, respectively. The wiring conductor 6 is made of Al having a thickness of 350 nm.

In order to accurately measure contact resistance and the like, a straight TLM contact group based on a linear transmission line model was prepared. The length of the short side of the n-type SiC region of this contact group is 208 μm. That is, a contact group pattern in which a plurality of electrode patterns made of small rectangles whose long side directions are orthogonal to the rectangular shape is prepared along the long side direction of the rectangular n-type SiC region. The length of the long side (ohmic contact width) of this small rectangle is 200 μm, and the length of the short side is 100 μm. Here, the contact group pattern is arranged in a horizontal line along the long-side direction of the n-type SiC region while sequentially changing the distance (contact distance) between the contacts (metal / semiconductor junctions) made of small rectangular patterns. Has been. The contact interval L is L = 6, 10, 15, 20, 25, 30 μm. When the resistance is obtained from the current-voltage characteristics between two adjacent contacts of this contact group, the resistance is arranged as a function of the contact interval, and the analysis is performed by linearly approximating the resistance, the precise contact resistance ρc and the transmission line length it is possible to obtain the L _T.

All the current-voltage characteristics measured between the contacts were all straight lines passing through the origin. This indicates that a good ohmic contact is obtained between the heating reaction layer 5 and the high concentration impurity region 2 of all contacts. FIG. 9 (TLM plot) shows the relationship between the resistance and distance between the ohmic contact electrodes determined from the slope of the current-voltage characteristics. The data has little variation and is plotted on a straight line. When TLM analysis was performed based on this linear approximation, an excellent value as very small as contact resistance ρc = 5.13 × 10 ⁻⁷ Ωcm ² was obtained. It can be seen that this value is comparable to the contact resistance ρc = 5.35 × 10 ⁻⁷ Ωcm ² of the sample of the structure based on the prior art described in Patent Document 1 manufactured at the same time.

When other conditions are the same and titanium (Ti) having a thickness of 100 nm is used instead of Ni as the electrode base material, a contact resistance of ρc = 4.2 × 10 ⁻⁶ Ωcm ² is obtained. When tungsten (W) having a thickness of 150 nm is used as the first conductor film, a contact resistance of 6.7 × 10 ⁻⁶ Ωcm ² is obtained.

One Hei 8-64801 discloses other prior art, in the structure as shown in FIG. 5 (g), the by forming a Ni electrode film on the silicon oxide film such as a contact window and SiO _2, When high-temperature heat treatment is performed at 1000 ° C. to 1200 ° C., (1) the silicon oxide film is reduced and eroded at the contact portion with the silicon oxide film, and the thickness of the silicon oxide film is reduced. If the thickness of the silicon oxide film is originally thin, the silicon oxide film may be penetrated and insulation may be lost. (2) Further, the boundary between the two parts (the contact window side wall and the SiC substrate surface At the point of intersection), it is thought that a reaction different from usual occurs between the ternary system of the n-type region, the silicon oxide film, and the Ni film, although the details are unknown. It points out that there is a serious problem that current cannot flow. However, such a problem does not occur in the method for manufacturing the ohmic electrode structure of the present invention (including the structures of FIGS. 1 to 3 and the structure described later). This is because the first heat treatment in forming FIG. 5G to obtain the structure of FIG. 5H is a sufficiently low temperature (350 ° C. to 850 ° C.) at which such a reaction does not occur, and ( When performing a second heat treatment step exceeding 1000 ° C. (which may cause a problem), as is apparent from the structures (i) and (j) of FIG. This is because the configuration does not exist. That is, it can be said that the structure of the ohmic electrode of the present invention and the manufacturing method thereof also solve the above problems (1) and (2) pointed out in the above-mentioned Japanese Patent Application Laid-Open No. 8-64801. Actually, the result of the electrical characteristics of the ohmic electrode structure using Ni described with reference to FIG. 9 clearly shows this.

  As described above, the method of manufacturing the ohmic electrode structure according to the first embodiment includes the step of bringing the electrode base material 17 into contact with the high concentration impurity region 22 on the surface of the SiC (silicon carbide) substrate 1, the electrode base A first heat treatment step of heat-treating the SiC substrate 1 in contact with the material 17 to form a heating reaction layer precursor layer 18 between the electrode base material 17 and the SiC substrate 1 including the high-concentration impurity region 2; A step of removing the unreacted electrode base material 17 left on the heating reaction layer precursor layer 18 and a heat treatment of the SiC substrate 1 after the unreacted electrode base material 17 is removed to heat the inner bottom of the contact window 4 The second heat treatment step for converting the heating reaction layer precursor layer 18 to the heating reaction layer 5 and the resistivity on the upper part of the heating reaction layer precursor layer 18 after removing the unreacted electrode base material 17 from the electrode base material 17. And a step of disposing a low wiring conductor 6Note that the second heat treatment process is performed at a temperature equal to or higher than the temperature of the first heat treatment process.

  More specifically, a step of selectively forming the high concentration impurity region 2 on the surface of the SiC substrate 1, a step of forming a thick insulating film 3 on the surface of the SiC substrate 1 including the high concentration impurity region 2, A step of opening a contact window 4 in the thick insulating film 3 so as to expose the surface of the high-concentration impurity region 2; a step of forming a predetermined electrode base material 17 on the entire surface of the SiC substrate 1 having the contact window 4 opened; A first heat treatment step of heat-treating the SiC substrate 1 on which the electrode base material 17 is formed to form a heating reaction layer precursor layer 18 between the electrode base material 17 and the SiC substrate 1 including the high-concentration impurity region 2; The step of removing the unreacted electrode base material 17 left on the thick insulating film 3 and the heating reaction layer precursor layer 18 by chemical means, and the SiC substrate 1 from which the unreacted electrode base material 17 has been removed Is it the same temperature as the first heat treatment step? Heat treatment at a temperature higher than this temperature, and a second heat treatment step for converting the heating reaction layer precursor layer 18 at the bottom of the contact window 4 into the heating reaction layer 5, and the surface of the heating reaction layer 5 at the bottom of the contact window 4 Forming a wiring conductor 6 in contact with and extending over the thick insulating film 3.

The ohmic electrode structure according to the first embodiment is placed on the SiC substrate 1, the high-concentration impurity region 2 selectively formed on the surface of the SiC substrate 1, and the SiC substrate 1. A thick insulating film 3, a contact window 4 opened to expose the surface of the high-concentration impurity region 2 in the thick insulating film 3, and a heating reaction layer 5 disposed in a self-aligned manner at the inner bottom of the contact window 4 And a wiring conductor 6 in contact with the surface of the heating reaction layer 5 in the contact window 4 and extended to the upper part of the thick insulating film 3.
The heating reaction layer 5 is made of a material mainly composed of at least one of metal silicide and metal carbide. Further, at least the lowermost end of the heating reaction layer 5 is formed by a solid-phase thermal reaction between the electrode base material 17 and the SiC substrate 1, and the unreacted electrode base material 17 remaining on the upper portion is removed. Has a history formed. In addition, the thick insulating film 3 is an insulating film having a history in which the electrode base material 17 according to claim 8 is once placed, heat treated at a low temperature, and then removed.

In addition to the above chemical reactions involving reduction and erosion, there are other considerations that must be taken into account when performing heat treatment by placing an electrode base material such as a metal or semiconductor on a SiO ₂ insulating material such as NSG or PSG. There are still important points. It is the diffusion of the matrix element. This diffusion occurs during the first heat treatment and when the base material element once taken into the lower insulating film by the first heat treatment is re-diffused in the subsequent thermal process. In most cases, the first heat treatment of the manufacturing process of the present invention described in FIGS. 5 (g) to (h) is not a problem at a negligible level. Therefore, re-diffusion due to the subsequent heat process is also a problem. Never become. However, with a certain technical intention, when it is necessary to deliberately select an electrode base material that is relatively easy to diffuse as an electrode base material of an ohmic electrode structure, or when a device using the structure has extremely few diffusion impurities. It can sometimes be a problem if it is sensitively affected, or if the device using the structure is in a special application where it is used for a long time at high temperatures. The ohmic electrode structure manufacturing method of the present invention and the ohmic electrode structure manufactured thereby are two means that can cope with such a very special case, that is, the second embodiment and the third embodiment. It has the form of These will be described in order below.

(Second Embodiment)
The first means is a method for structurally solving the diffusion of the matrix element. The structure of FIGS. 10-12 has shown 2nd Embodiment of the ohmic electrode structure of this invention. In these drawings, the elements having the same numbers as those in FIGS. 1 to 3 are the same, and redundant description will be omitted in order to eliminate redundant description.

Reference numeral 7 in FIGS. 10 to 12 denotes a diffusion blocking insulating film having a function of stopping the diffusion of the electrode base material element. It is incorporated in the lower part (12) in layers. Other parts of the thick insulating film 3 except the diffusion blocking insulating film 7 are the same as the thick insulating film of FIGS. 1 to 3 (material, thickness, forming method, etc.). Here, “diffusion prevention” means that the diffusion coefficient is sufficiently small compared to other portions of the thick insulating film. Examples of the insulating film having this property include a Si ₃ N ₄ film, an Al ₂ O ₃ film, an additive-free SiC film, a laminated film thereof, and a composite film formed by LPCVD or sputtering. Is not to be done. The thickness is suitably 10 nm to 150 nm, but may be thicker.

Next, the manufacturing method of FIG. 10, which is the second embodiment of the ohmic electrode structure of the present invention, will be described with reference to the sectional process diagrams of FIGS. 13 (e2) to (h2).
(E) First, the high-concentration impurity region 2 is selectively formed on the SiC substrate 1 through the same steps as in FIGS. 4 (a) to 4 (c). When the high-concentration impurity region 2 is completed, a pre-structure of the thick insulating film 3 mainly made of SiO ₂ material is formed in the same process as in FIGS. 4D to 5E. Subsequently, when the diffusion prevention insulating film 7 is deposited on the previous structure, a completely thick insulating film 3 is formed, and the cross-sectional structure shown in FIG. 13 (e2) is obtained. As the diffusion blocking insulating film 7, for example, a 100 nm Si ₃ N ₄ (silicon nitride) film can be used by LPCVD using dichlorosilane and ammonia as raw materials. Here, a laminated structure of a thin thermal oxide film 31 and a CVD oxide film 32 (suitable for forming this low-resistance contact) is used in the thick insulating film 3 portion excluding the diffusion prevention insulating film 7. Is a measure considering the continuity with the description of the first embodiment and the manufacturing process, and the second embodiment is of course not limited to such a laminated structure.

(F2) Next, as shown in FIG. 13 (f2), a contact window 4 is formed in a predetermined region of the thick insulating film 3 by using a well-known photolithography method and dry etching technique. As the dry etching, for example, various means such as a reactive ion etching (RIE) method using CHF ₃ or C ₂ F ₆ as an etchant and electron cyclotron resonance ion etching (ECR ion etching) can be used. This should be noted when the etching rate and appropriate etching means of the diffusion blocking insulator 7 and other thick insulating film portions are different. In the former case, it is necessary to proceed with dry etching carefully considering this. In the latter case, even if it is troublesome, when etching the diffusion prevention insulator, an etching means (dry etching method or etchant gas) suitable for this is selected. In the case of forming an ultra-low resistance contact, first, dry etching is performed, and when the field insulating film 3 is left several tens of nm thick, switching to wet etching using a buffered hydrofluoric acid solution is performed. The preferable result is obtained as in the first embodiment.

(G2) Thereafter, a predetermined electrode base material 17 is formed on the entire surface of SiC substrate 1 in the same manner as in FIG. FIG. 13 (g2) shows a cross-sectional structure of the ohmic electrode structure at this time.
(H 2) Subsequently, performing a first heat treatment described above in an inert gas atmosphere such as a SiC substrate 1 entirely deposited electrode base material 17 of high purity Ar and N _2, FIG. 13 (h2) As described above, the heating reaction layer precursor layer 18 is formed between the electrode base material 17 and the SiC substrate 1. The temperature and time of the first heat treatment depend on the type of electrode base material and the film forming conditions, and thus cannot be defined uniformly. However, according to experiments conducted so far by the inventors, the temperature is approximately 350 ° C. The range of ˜850 ° C. and the time range of 5 minutes to 12 hours. Since the heating reaction layer precursor layer 18 is generated from a solid phase reaction that occurs only in contact with the SiC substrate 1, the precursor layer 18 is automatically aligned with the bottom of the contact window 4. The
The manufacturing process after the completion of the first heat treatment is not changed from that shown in FIGS.

As described above, in the method of manufacturing the ohmic electrode structure according to the second embodiment, the step of forming the thick insulating film 3 on the surface of the SiC substrate 1 including the high-concentration impurity region 2 includes the electrode base material. 17 including a step of forming a diffusion blocking insulating film 7 for blocking 17 diffusion.
In addition, the ohmic electrode structure according to the second embodiment includes a diffusion prevention insulating film 7 that prevents diffusion of the electrode base material 17 on the upper part, the lower part, or the inside of the thick insulating film 3.

In the second embodiment, the diffusion prevention insulating film 7 disposed as a part of the upper portion of the thick insulating film is in the first heat treatment step (FIG. 13 (h2)), and the upper electrode mother is formed. Since the diffusion of the material 17 is stopped, it is possible to solve the problem that the electrode base material element diffuses downward in the same process and the subsequent heat process and affects the characteristics of the device. Based on the present invention the second embodiment, to prepare a Ni-based TLM contact of the same specifications as those described in the first embodiment, was to evaluate the contact resistance, 10 ^-7 [Omega] cm ² units The first half contact resistance was obtained.

  The structure of another second embodiment shown in FIGS. 11 and 12 is only shown in that the position of the diffusion prevention insulating film 7 is inside the thick insulating film 3 (FIG. 11) and below (FIG. 12). This is different from the 10 structure. However, this is only the difference between the top, the inside, and the bottom of the thick insulating film where the diffusion is blocked. The function that blocks the diffusion of the electrode matrix element and the effect brought about by it are clearly the same. Therefore, detailed description of the structure is omitted. Also, in the manufacturing process, the diffusion prevention insulating film 7 is formed at the end of the other part of the thick insulating film 3 (FIG. 12) or in the middle (FIG. 11), or is formed first. (FIG. 10) is different, and the other steps are the same, so the description will be omitted.

(Third embodiment)
A second means for removing the influence of the diffusion of the base material element is a method that solves the problem by a device method. This method is particularly effective when the direct diffusion of the electrode base material element that occurs in the first heat treatment step is contained in the surface layer of the thick insulating film 3.
Since the structure of the ohmic electrode structure / third embodiment of the present invention is the same as that of FIG. 1, FIG. 2, or FIG. 3, description of the structure is omitted.

  Next, the manufacturing method of the 3rd Embodiment of the ohmic electrode structure of this invention is demonstrated using the cross-sectional process drawing of FIG.14 (g3)-(i32).

  (G3) First, the SiC in which the contact window 4 is opened in the thick insulating film 3 through the process similar to that shown in FIGS. 4A to 5G in the manufacturing process described in the first embodiment. A predetermined electrode base material 17 is formed on the entire surface of the substrate 1. However, there is one small difference. That is, as shown in FIG. 14 (g3), the thickness when the thick insulating film 3 is formed is slightly thicker than the final required thickness. The portion thicker than the final thickness is referred to herein as “sacrificial layer 8”. The thickness of the sacrificial layer 8 is determined so as to be larger than the distance over which the base electrode element is thermally diffused in the next first heat treatment.

(H 3) in the electrode base material 17 Following entire deposition, performing mild first heat treatment such as described above the SiC substrate 1 in high purity inert gas atmosphere such as Ar or N _2. By this heat treatment, the heating reaction layer precursor layer 18 is formed in a self-aligned manner between the electrode base material 17 and the SiC substrate 1 as shown in FIG. At this time, the electrode base material element enters the sacrificial layer 8 portion of the thick insulating film 3 by thermal diffusion. The temperature and time of the first heat treatment depend on the type of electrode base material and the film forming conditions, and thus cannot be defined uniformly. Range.

  (Ri) When the first heat treatment is completed, when the SiC substrate 1 is immersed in a predetermined etching solution that dissolves only the electrode base material, the unreacted electrode base material is wiped off from the substrate surface, and the bottom of the contact window 4 is formed. A structure as shown in FIG. 14 (i 31) is obtained in which only the heating reaction layer precursor layer 18 is left. The etching solution used here can be appropriately selected according to the chemical properties of the electrode base material. However, if an appropriate etchant cannot be found, an etchant in which sulfuric acid and hydrogen peroxide solution are mixed at a volume ratio of 4: 1. Can be used. This etchant maintained at 100 ° C. dissolves most electrode base materials well, and hardly dissolves metal silicides and metal carbides. If the selectivity of the electrode base material 17 with respect to the heating reaction layer precursor layer 18 and the thick insulating film can be sufficiently ensured, the unreacted electrode base material may be removed by Doiray etching.

(Re32) Next, when the SiC substrate from which the electrode base material 17 has been removed is immersed in dilute hydrofluoric acid or buffered hydrofluoric acid solution for a certain period of time, rinsed and dried, the sacrificial layer 8 of the SiC substrate is removed, and FIG. ) Is possible. If there is another etchant that dissolves the sacrificial layer 8 and does not dissolve the heated reaction precursor layer 18, it may be used. Further, the sacrificial layer 8 may be removed by dry etching instead of wet etching.
(No. 3) Since the manufacturing process after the completion of the first heat treatment is exactly the same as that shown in FIGS.

As described above, the method of manufacturing the ohmic electrode structure according to the third embodiment is a temporary process for forming the thick insulating film 3 on the surface of the SiC substrate 1 including the high concentration impurity region 2. A step of forming the sacrificial sacrificial layer 8 and removing the unreacted electrode base material 17 left on the subsequent thick insulating film 3 and the heated reaction layer precursor layer 18 by chemical means, A step of removing the temporary sacrificial layer 8 is added between the subsequent second heat treatment step.
In the ohmic electrode structure according to the third embodiment, the thick insulating film 3 has a temporary sacrificial layer 8 in the upper layer portion after the film formation until the ohmic electrode structure is completed. Have a history to do. Further, the sacrificial layer 8 in the upper layer portion of the thick insulating film 3 is made of an insulator or a semiconductor, or a composite, mixture, or laminate thereof. Furthermore, the sacrificial layer 8 on the upper layer of the thick insulating film 3 has a diffusion preventing function.

As is clear from the above description, in the third embodiment of the present invention, the electrode base material 17 generated in the first heat treatment step is formed on the sacrificial layer 8 disposed as a part of the thick insulating film. Since the diffusion of the element is absorbed and the sacrificial layer 8 is completely removed before re-diffusion in the next high-temperature heat treatment, that is, the second heat treatment, the first heat treatment and the subsequent heat process are performed. Thus, the problem that the electrode base material element diffuses downward and affects the characteristics of the device can be solved. Based on the third embodiment of the present invention, a Ni-based TLM contact having the same specifications as described in the first embodiment was fabricated, and the contact resistance was evaluated. As a result, 10 ⁻⁷ Ωcm ^2. The contact resistance in the first half of the table was obtained.

In the description of the third embodiment, the example applied to the ohmic electrode structure having the flat high-concentration impurity region 2 as shown in FIG. 1 has been described. However, the convex shape as shown in FIGS. Of course, the present embodiment can also be applied to a structure having a concave high-concentration impurity region 2.
In the third embodiment, the sacrificial layer 8 is made of the same material as the other parts of the thick insulating film 3, but the sacrificial layer 8 is not actually subject to any such restrictions. Absent. Other insulating materials and semiconductor materials may be used as long as they have similar functions.
Furthermore, the diffusion blocking insulating film 7 in the second embodiment may be used as the sacrificial layer 8. In this case, of course, the diffusion prevention insulating film 7 is removed before the second heat treatment is performed.
Now that the embodiments of the ohmic electrode structure according to the present invention have been described, two “embodiments” in which the structure is applied to an actual device will be described below.

(Fourth embodiment)
It is the example which applied 1st Embodiment regarding the ohmic electrode structure of this invention, and its manufacturing method to SiC-MESFET (SiC metal-semiconductor structure field effect transistor) used for amplification of a high frequency.

  Hereinafter, the fourth embodiment of the present invention will be described with reference to the drawings. However, the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are actual. It should be noted that they are different. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

  FIG. 15 is a cross-sectional view of a principal part of a MESFET using a SiC substrate according to the present invention.

Reference numeral 51 denotes a semi-insulating or n-type single crystal SiC bulk substrate (hereinafter simply referred to as a substrate). For example, a (0001) _Si face 8 ° off-cut 4H-SiC substrate doped with nitrogen (donor) at a concentration N _D = 1 × 10 ⁺¹⁹ cm ⁻³ can be mentioned, but if high-quality epitaxial growth is possible, [0001] Other than the _Si face, the crystal polymorph may be 6H, 3C, 15R, etc. instead of 4H. On the substrate 51, a p-type first epitaxial layer 52 and an n-type second epitaxial layer 53 serving as a channel are stacked. The thickness of the first epitaxial layer 52 is preferably at least t _A1 = 1 μm or more, and the acceptor concentration is preferably at least N _A1 = 5 × 10 ⁺¹⁶ cm ⁻³ . The thickness t _D2 and the donor concentration N _D2 of the second epitaxial layer 53 are appropriately selected according to the operation specifications of the MESFET to be manufactured, but usually 0.2 μm <t _D2 <0.8 μm and 5 × 10 ⁺¹⁶ cm ^{− respectively.} It is a value in the range of ³ <N _D2 <5 × 10 ⁺¹⁸ cm ⁻³ . When a semi-insulating substrate is used as 51, the first epitaxial layer 2 can be omitted.

  Reference numeral 54 denotes an element region formed by isolating (element isolation) the second epitaxial layer 53. The MESFET is formed in this region. The element isolation may be realized by mesa etching the n-type second epitaxial layer 53 around the element region 54 as shown in FIG. 15, or the first isolation may be performed around the element region 54 using an ion implantation technique. It may be realized by forming a p-type region reaching the epitaxial layer 52 and surrounding the element region 54. When an n-type substrate is used as the substrate 51, the mesa etching is prevented from penetrating the first p-type epitaxial layer 2. This is because the thermal oxide film grown in the subsequent field insulating film process tends to be a positively charged film in the p-type region, and this charge causes an inversion layer in the p-type cross-sectional region of the mesa etching sidewall. This is because there is a risk that the n-type bulk substrate and the channel region 58a are electrically connected to each other and element isolation is impaired.

Reference numerals 56 and 57 denote n ⁺ -type source and drain regions provided in the element region 54. The donor concentration of the source region 56 and the drain region 57 is at least N _D > 5 × 10 ⁺¹⁹ cm ⁻³ , preferably N _D > 1 × 10 ⁺²⁰ cm ⁻³ on the outermost surface. An n-type region (= a part of the second epitaxial layer 3) sandwiched between the source region 56 and the drain region 55 is a channel region 58a. The channel region 58a has a surface and a surface layer with few metal contamination, fine undulations, and a crystal irregular layer.

A thick insulating film 58 is formed on the surface of the substrate on which the mesa structure and the source 55 and drain region 57 are formed. The thick insulating film 58 includes a thin thermal oxide film 59 grown by thermal oxidation of the SiC substrate surface and an upper insulating film 60 deposited by a method other than thermal oxidation (such as atmospheric pressure CVD), such as a PSG (phosphosilicate glass) film or It is composed of a laminated film of SiO ₂ film. The thickness of the thermal oxide film 9 is less than 50 nm, preferably 5 to 20 nm, and the total thickness of the thick insulating film 5 is 100 nm to 3 μm, preferably 300 nm or more. Of the thermal oxide film 59, the portion located in the upper part of the channel is formed by thermally oxidizing the above-mentioned metal contamination, fine undulations, and the channel surface layer with few crystal irregular layers, so that it has high quality with less defect incorporation. It is an oxide film.

  A source window 61, a drain window 62, and a gate window 63 are opened in the hot insulating film 58 on the source region 56, the drain region 57, and the channel region 58a, respectively. Heat reaction layers 64 and 65 are selectively and sealed at the bottom of the source / drain windows to form a source contact (= ohmic) and a drain contact (= ohmic). . On the other hand, at the bottom of the gate window 63, the gate electrode 66 and the channel region 58a are in contact with each other to form a gate (Schottky) contact. Note that the interface between the gate electrode 66 and the SiC substrate 51 is a staircase type steep junction. Examples of the material of the gate electrode include a laminated film of Ti and TiN (Ti is in contact with the substrate 51), but other materials may be used. The thicknesses of Ti and TiN are, for example, 50 nm and 150 nm.

  67, 68, and 69 are wiring conductors (pads) of a source contact, a drain contact, and a gate contact, respectively, disposed on the thick insulating film 55 and made of thick Al or the like. A conductor such as Ti, TiN, or TaN is inserted between the wiring conductors 67 and 68 and the source / drain heating reaction layers 64 and 65 in order to improve adhesion, contact resistance, and heat resistance of both conductors. You can also. As shown in FIG. 15, the gate contact (= electrode) lead-out wiring may not be configured to contact the gate electrode 66 above the channel region 58a, but may be configured to contact the region outside the channel region 58a. .

  As is apparent from the above description, the MESFET having the source / drain ohmic structure on one main surface of the SiC substrate according to the present invention has an unreacted resistance between the wiring conductors 67 and 68 and the heating reaction layers 64 and 65. Since the high electrode base material is not interposed, the contact resistance of the source / drain contact can be reduced as compared with the conventional contact technology in which the unreacted electrode base material is interposed. Can be reduced. In the MESFET having the source / drain ohmic electrode structure according to the present invention, the gap between the heating reaction layers 64 and 65 and the side walls of the source window (contact window) / drain window (contact window) 56a and 57a is eliminated. As a result, the size of the source / drain contact can be reduced correspondingly, and as a result, the size of the MESFET can be reduced.

  Next, a method for manufacturing the MESFET shown in FIG. 15 will be described with reference to FIGS. Here, for ease of understanding, description will be made with specific manufacturing conditions as much as possible, but this does not mean that the present invention is limited to these conditions.

(A) First, after nitrogen (donor) is doped to a concentration of N _D = 1 × 10 ⁺¹⁹ cm ⁻³ (0001) _Si surface 8 ° off-cut 4H—SiC substrate 51 is sufficiently cleaned by the above-described RCA cleaning or the like. Then, a p-type first epitaxial layer 52 (t _A1 = 4.5 μm, N _A1 = 5 × 10 ⁺¹⁵ cm ⁻³ ) is formed on the surface of the substrate 51 by a known high-temperature CVD method (growth temperature 1500 ° C.) using silane and propane as raw materials. ) And an n-type second epitaxial layer 53 (t _D2 = 0.4 μm, 1.5 × 10 ⁺¹⁷ cm ⁻³ ). The p-type dopant is trimethylaluminum, and the n-type dopant is nitrogen. Since a low-quality epitaxial layer adheres to the back surface of the substrate 51, a thick SiO ₂ film is deposited and protected on the surface of the substrate 51 by CVD using silane and oxygen, and then the epitaxial layer on the back surface is mechanically bonded. After removal by polishing and removal of the protective film after completion, the structure shown in FIG. 16A is obtained. (B) Next, the surface of the substrate 51 is subjected to reactive ion etching (RIE) using an oxide film mask to obtain a mesa. An element region 54 having a structure is formed. In this embodiment, since the n-type substrate 51 is used, care should be taken not to penetrate the first epitaxial layer 52 during mesa etching. An oxide film mask (not shown) used for etching is formed by depositing CVD-SiO ₂ having a thickness of 2 μm and patterning it by photolithography and RIE. When the mesa etching is completed, the used oxide film mask is removed with a buffered hydrofluoric acid solution (BHF) as shown in FIG.
(C) Next, an oxide film mask (CVD-SiO ₂ , 2 μm thickness, not shown) for selectively ion-implanting the source region 56 and the drain region 57 as the high-concentration impurity regions is formed. . After patterning of the oxide film mask (that is, opening the source / drain regions) by photolithography and RIE, the resist is removed, and the depth of ion implantation is adjusted to the surface of the substrate 1 sufficiently cleaned by RCA cleaning or the like. A through film (CVD-SiO ₂ , not shown) having a thickness of 25 nm is formed and implanted toward the substrate surface at 500 ° C. with phosphorus ions. An example of the multistage acceleration voltage and the dose is as follows.

30 keV, 5.0 × 10 ¹⁴ cm ⁻²
50 keV, 6.0 × 10 ¹⁴ cm ⁻²
70 keV, 6.0 × 10 ¹⁴ cm ⁻²
100 keV, 9.0 × 10 ¹⁴ cm ⁻²
130 keV, 2.4 × 10 ¹⁵ cm ⁻²
If implantation is performed under these conditions, a donor distribution (impurity concentration of 3.0 × 10 ²⁰ cm ⁻³ ) that is substantially uniform in the depth direction from the surface of the substrate 51 is realized in the source region 56 / drain region 57. When phosphorus ion implantation is completed, the oxide film mask and the through film are completely removed with BHF, and the substrate surface is RCA cleaned. After the surface is cleaned, the substrate 1 is subjected to a heat treatment at 1700 ° C. for 1 minute in a high-purity Ar atmosphere to activate phosphorus ions implanted into the source region 56 / drain region 57 (FIG. 16C). It has been confirmed by measurement of the Hall effect that the phosphorus ions heat-treated under such conditions are activated by 95% or more.

  The next step is a process for forming an ohmic electrode structure that best characterizes the present invention, and will be described in more detail.

  (D) When the formation of the source region 56 / drain region 57 is completed, a transient oxide film (1100 ° C., dry oxidation) of about 20 to 40 nm is grown on the substrate surface cleaned by RCA cleaning, and the grown oxide The membrane is immediately removed with dilute hydrofluoric acid solution (DHF). By this step, the crystal irregular layer, implantation damage layer, various contamination layers, and carbonized layer generated on the surface of the SiC substrate 1 by ion implantation and activation heat treatment can be effectively removed. After the temporary thermal oxide film is removed by DHF, the substrate 51 is sufficiently washed, and a thermal oxide film (1100 ° C., WET oxidation) 59 having a thickness of about 20 nm is again formed on the surface of the substrate 51 as shown in FIG. Then, an upper insulating film 60 made of an oxide film having a thickness of 800 nm is deposited thereon by atmospheric pressure CVD. Thus, a thick insulating film 58 composed of the thermal oxide film 59 and the upper insulating film 60 is formed.

(E) Next, a photoresist having a thickness of 1 to 2 [mu] m is applied to the surface of the thick insulating film 58, exposed, and developed to remove the photoresist in regions corresponding to the source window 56a and the drain window 57a. Then, reactive ion etching (RIE) of the thick insulating film 58 is performed using CHF ₃ gas plasma or the like. If the lowest possible contact resistance is desired, the RIE is stopped when the thick insulating film 58 is left several hundreds of nanometers, and switching to wet etching using BHF is performed. When the etching is finished, the resist is removed, and the SiC substrate 51 is sufficiently cleaned by RCA cleaning or the like, whereby the structure of FIG.

  (F) When the source window 56a and the drain window 57a are opened, the base electrode 70 is formed on the entire surface of the SiC substrate 51 in the same manner as in the manufacturing steps (g) to (h) of the first embodiment of the present invention. After the film formation, a first heat treatment is applied to generate heating reaction layer precursor layers 71 and 72 between the electrode base material 70 and the source region 56 and drain region 57, respectively. As an electrode base material, an appropriate heat treatment condition of Ni in the case of a thickness of 50 nm formed by electron beak deposition is given as a specific example. The heat treatment temperature is 600 ° C. and the heat treatment time is 2 hours. Since the heating reaction layer precursor layers 71 and 72 are solid-phase reactions that occur in direct contact with the SiC substrate 51, the precursors result in the source region 56 and the drain region 57 as shown in FIG. It is selectively arranged in automatic alignment with the contact surface.

(G) Next, after the unreacted electrode base material 79 is completely removed by the acid-based etchant described in the first embodiment in the first heat treatment step, the SiC substrate 51 is washed, and then the first By heating the SiC substrate at a temperature higher than the temperature of the heat treatment (second heat treatment) to promote the solid phase reaction between the heating reaction layer precursor layers 71 and 72 and the SiC substrate 51, the heating reaction layer precursor is heated. The layers 71 and 72 are converted into heating reaction layers 64 and 65 mainly composed of a thermodynamically stable phase. The atmosphere of the heat treatment is a high purity inert atmosphere similar to the first heat treatment. FIG. 18G illustrates the structure at this stage. The temperature and time of the second heat treatment are set in the range of 700 ° C. to 1200 ° C. for 30 seconds to 100 minutes, respectively. In the case of the Ni electrode system precursor described above, a very good result is obtained when the temperature is 950 ° C. to 1050 ° C. and the time is 30 seconds to 2 minutes. When heat treatment is performed under such conditions, lower silicide precursors such as Ni ₃ Si, Ni ₂ Si, Ni ₃₁ Si ₁₂ , and NiSi take in the Si element of the SiC substrate 1 and are the most chemically stable and A heat-reactive layer mainly composed of NiSi _{2 from} which a low resistance contact can be obtained is obtained.

(H) When the heat reaction layers 64 and 65 are formed, a gate is formed on the thick insulating film 58 using well-known photolithography and wet etching or dry etching (such as RIE) as shown in FIG. The window 63 is opened. When opening is performed by dry etching, good transistor characteristics can be obtained by using wet etching together. That is, dry etching is first performed, and when the thick insulating film 58 is left several tens of nm, switching to wet etching is performed. If the gate window 63 is penetrated by dry etching, acceleration plasma damage is caused on the channel surface, and the reverse bias leakage current of the gate-Schottky contact is increased. When it is necessary to form a gate window 63 that is so fine that it is difficult to use wet etching together, it is important to use dry etching means with little plasma damage, such as ECR (electron cyclotron resonance) plasma etching.
The photoresist used for the etching is removed, and the SiC substrate 51 is sufficiently washed and dried. In general, a cleaning method such as RCA cleaning having a high cleaning effect can be used for cleaning, with a special exception. This is because the heating reaction layers 64 and 65 exhibit strong resistance to the acid / alkali cleaning liquid. FIG. 18H shows the structure thus formed. (I) When the cleaning is completed, a (Schottky) gate electrode material and a wiring conductor material having a predetermined thickness are deposited on the entire surface of the SiC substrate 51 by electron beam evaporation. Or it forms into a film using means, such as DC magnetron sputtering. Note that it is desirable to continuously form the gate electrode material and the wiring conductor material. Ti can be cited as a typical gate electrode material, and Al can be cited as a wiring conductor material. However, the present invention is not limited to this. When the MESFET is used at a high temperature, it is possible to improve the heat resistance by providing a barrier metal for preventing mutual diffusion between the gate electrode material and the wiring conductor material. Examples of the barrier metal suitable for this purpose include TiN and TaN.
The standing time and atmosphere between the gate window opening etching and the gate electrode material deposition are extremely important determinants which determine the quality of transistor characteristics. If this time is long, a natural oxide film is formed at the bottom of the gate window 63, or hydrocarbon is reattached, and the Schottky characteristic of the gate electrode 66 is deteriorated, which causes deterioration of transistor characteristics. For this reason, it is necessary to deposit the gate electrode material as soon as possible after the opening of the gate window 63.
Thereafter, when the gate electrode material and the wiring conductor material are simultaneously patterned using known photolithography and wet etching or dry etching (RIE, etc.), as shown in FIG. The wiring conductors 67, 68, 69 of the gate are formed, and the SiC MESFET based on the SiC semiconductor device of the present invention is completed.

  As described above, the method of manufacturing the semiconductor device according to the fourth embodiment selectively forms the source region 56 and the drain region 57 as the high concentration impurity region on the surface of the SiC substrate 51, and the source region. 56, a step of forming a thick insulating film 58 on the surface of the SiC substrate 51 including the drain region 57, and a source window as an ohmic contact window on the thick insulating film 58 so as to expose the surfaces of the source region 56 and the drain region 57. 56a, a step of opening the drain window 57a, a step of forming a predetermined electrode base material 70 on the entire surface of the SiC substrate 51 having the source window 56a and the drain window 57a open, and an SiC substrate 51 on which the electrode base material 70 is formed. Is heated to form heating reaction layer precursor layers 71 and 72 between the electrode base material 70 and the SiC substrate 51 including the source region 56 and the drain region 57. 1, a step of removing the unreacted electrode base material 70 left on the thick insulating film 58 and the heat reaction layer precursor layers 71 and 72 by chemical means, and an unreacted electrode base material 70. The SiC substrate 51 from which the heat treatment has been removed is heat-treated at a temperature equal to or higher than the temperature of the first heat treatment step, and the heating reaction layer precursor layers 71 and 72 on the inner bottoms of the source window 56a and the drain window 57a are heated reaction layers. A second heat treatment step for converting to 64, 65, a step of opening the gate window 63 as a Schottky contact window of the SiC substrate 51 that has undergone the second heat treatment step, and a Schottky at least at the bottom of the gate window 63 The step of disposing the gate electrode 66 as an electrode material made of an electrode material, or the surface of the electrode material provided at the same time as the gate electrode 66 provided on the surface of the heating reaction layers 64 and 65 When the electrode material is not provided in the window 56a and the drain window 57a, the surface of the source window 56a, the heating reaction layers 64 and 65 in the bottom of the drain window 57a), and the surface of the gate electrode 66 provided in the bottom of the gate window 63 And forming a wiring conductor 67, 68, 69 extended to the upper part of the thick insulating film 58.

  More specifically, a step of selectively forming a source region 56 and a drain region 57 in which conductive impurities are added at a high concentration on the surface of the SiC substrate 51, and a surface of the SiC substrate 51 including the source region 56 and the drain region 57. A step of forming a thick insulating film 58, a step of opening the source window 56a and the drain window 57a in the thick insulating film 58 so as to expose the surfaces of the source region 56 and the drain region 57, and a source window 56a and a drain window. A step of forming a predetermined electrode base material 70 on the entire surface of the SiC substrate 51 having openings 57a, and a heat treatment of the SiC substrate 51 on which the electrode base material 70 is formed to form the electrode base material 70, the source region 56, and the drain region 57 A first heat treatment step for forming the heating reaction layer precursor layers 71 and 72 between the SiC substrate 51 and the upper part of the thick insulating film 58 and the heating reaction layer precursor layer 7. , 72 to remove the unreacted electrode base material 70 left on the upper portion by chemical means, and to remove the SiC substrate 51 from which the unreacted electrode base material 70 has been removed from the temperature of the first heat treatment step. A second heat treatment step in which heat treatment is performed again at the same or higher temperature to convert the heat reaction layer precursor layers 71 and 72 in the bottom of the source window 56a and the drain window 57a into heat reaction layers 64 and 65; A step of opening the gate window 63 of the SiC substrate 51 after the heat treatment step, a step of disposing an electrode material made of a Schottky electrode material at least at the bottom of the gate window 63, and an inner bottom of the source window 56a and the drain window 57a A thick insulating film in contact with the surface of the electrode material provided on the surface of the heating reaction layers 64 and 65 or the surface of the electrode material provided on the surface of the heating reaction layers 64 and 65 and the surface of the electrode material provided on the bottom of the gate window 63 58 Comprising the steps of forming a wiring conductor 67, 68, 69 which distracted to the top.

  The semiconductor device according to the fourth embodiment is a silicon carbide semiconductor device having a Schottky electrode structure and an ohmic electrode structure on one main surface of SiC substrate 51, and the ohmic electrode structure is The ohmic electrode structure of the first embodiment is used. Further, in the silicon carbide / metal-semiconductor field effect semiconductor device formed on one main surface of the SiC substrate 51, at least one of the source contact and the drain contact is constituted by the ohmic electrode structure according to the first embodiment. Has been. Further, the silicon carbide / metal-semiconductor field effect semiconductor device is the same as the gate / Schottky contact between the heat reaction layers 64 and 65 of the source contact or drain contact and the wiring conductors 67 and 68 of the contact. And the electrode material formed simultaneously is clamped.

  As apparent from the above detailed description, the SiC semiconductor device (MESFET) manufacturing method according to the present invention is a new method that does not use any photoresist to dispose a heating reaction layer at the bottom of the source window and drain window. Since the self-alignment process (FIGS. 17 (e) to 18 (h) is used, the problem of the prior art of Patent Document 1 caused by the lift-off method using a photoresist or the like in the same step. Points: (1) Contact failure occurs and cleaning costs increase, (2) Resist contamination is disliked, and a deposition apparatus for the Si integrated circuit process cannot be shared, and a dedicated deposition apparatus for the process is installed It can be said that it solves the problem of having to prepare a dedicated clean room space at the same time.

Further, in the fourth embodiment, in addition to the effects common to the entire present invention, there are effects unique to the present embodiment as described below.
A widely used method for manufacturing a gate electrode structure of an SiC-MESFET is described in the literature “S. Sriram, RR Siergiej, RC Clarke, AK Agarwal, CD Brandt, physica status solidi (a), Vol. 162 p441 ( 1997) ”is an electrode lift-off method using a photoresist (or electron beam exposure resist). In addition, the gate length of the SiC-MESFET is very fine on the submicron scale. That is, even in the conventional SiC-MESFET gate electrode structure, the same problems (1) and (2) as in the method of manufacturing the source and drain ohmic electrode structures have occurred. However, as is apparent from the description of FIGS. 18G to 18I, the MESFET manufacturing method of the present invention has a configuration in which the lift-off method is not used even in the gate electrode formation step. ) Contact failure occurs and cleaning cost is high, (2) Vapor deposition equipment for Si integrated circuit process cannot be shared, and dedicated vapor deposition equipment for the same process and clean room space dedicated to installing it must be prepared The problem of having to be solved can be solved at the same time.
In the fourth embodiment, a conductive film for forming the gate electrode 66 is used as an adhesion reinforcing film or a barrier film between the source / drain wiring conductors 67 and 68 and the source / drain heating reaction layers 64 and 65. In addition, since the structure is also used together with the gate electrode 66, there is no waste, and there is an effect that the conductor material and the manufacturing time can be saved.

  As an example, the MESFET (gate length) shown in FIG. 15 using Ni having a thickness of 50 nm as the electrode base material 70 of the source / drain heating reaction layers 64 and 65 and Ti / TiN (Ti is in contact with the SiC substrate 51) as the gate electrode 66. 3μm) results are introduced. The conditions for forming the first and second epitaxial layers and the conditions for ion implantation and impurity activation are as exemplified in the above manufacturing process.

FIG. 19 is a diagram showing a TLM plot when determining the contact resistance of the source / drain region. Since the plots are on a straight line, it can be seen that the contact resistance and the sheet resistance of the source / drain region (high concentration impurity region) are uniform. From the TLM analysis, it was found that the contact resistance of the source / drain was a very low value of ρC = 1.7 × 10 ⁻⁶ Ωcm ² . Figure 20 is the drain current of the MESFET - a diagram showing the drain voltage _(I d _{-V ds)} characteristic. The parameter is the gate voltage Vg. The fact that I _d −V _ds extends linearly from the origin suggests that a good ohmic contact is obtained at the source / drain. Since the static characteristics of a typical transistor are obtained, it is confirmed that a high-quality Schottky contact is formed not only on the source / drain ohmic contact but also on the gate electrode.

(Fifth embodiment)
The fifth embodiment relating to the ohmic electrode structure and the manufacturing method thereof according to the present invention is applied to a vertical MOSFET (metal-oxide-semiconductor structure field effect transistor) in which the source and the drain are on the front and back of the SiC substrate, respectively. This is an example.
Hereinafter, the fifth embodiment of the present invention will be described with reference to the drawings. However, the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are actual. It should be noted that they are different. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

FIG. 21 shows a cross section of a principal part of a unit cell 170 of a MOSFET using a SiC substrate according to the present invention. The unit cell is the smallest unit of the element region. In the power element, a large number of unit cells are arranged in parallel in the vertical and horizontal directions to increase the current. In the following description, 170 is used to mean both the element region and the unit cell.
Reference numeral 171 denotes an n (n ⁺ ) type single crystal SiC substrate doped with impurities at a high concentration, and an n type epitaxial layer having a surface (upper surface side main surface) with a thickness of 10 μm and nitrogen added at 1 × 10 ¹⁶ / cm ^3. 173 is homoepitaxially grown. All crystal substrates such as 4H, 6H, 3C, and 15R (H is hexagonal, C is cubic, and R is rhombohedral) can be used. In predetermined regions of the surface layer of the n-type epitaxial layer 173, p-type base layers 73a and 73b to which a p-type impurity is added in a higher impurity concentration than the n-type epitaxial layer 173 are formed apart from each other.
N-type source regions (= corresponding to high-concentration impurity regions) 74a and 74b, which are shallower than the p-type base regions 73a and 73b and doped with high-concentration impurities, are formed in the surface layer predetermined regions of the p-type base regions 73a and 73b. ing. p ⁺ -type base regions 75a and 75b, which are part of the p-type base regions 73a and 73b and are doped with p-type impurities at a high concentration, are disposed on the outer surface layers of the n-type source regions 74a and 74b. Has been. The impurity concentrations of the n-type epitaxial layer 173, the p-type base regions (73a and 73b), and the n-type source regions (74a and 74b) are set to increase in this order.

A gate oxide film 75 is provided on the surface of the SiC substrate 171 on which the impurity regions are formed. A conductive polycrystalline silicon gate electrode 76 is provided on the gate oxide film 75. A polycrystalline silicon oxide film 77 is disposed on the side and top surfaces of the gate electrode 76. An interlayer insulating film 78 is formed on the gate oxide film 75 and the polycrystalline silicon oxide film 77.
79a and 79b are source windows opened in the interlayer insulating film 78 and penetrating through the n-type source regions 74a and 74b and the p-type base regions 73a and 73b on the surface of the SiC substrate 171. Conductive heating reaction layers 80a and 80b are placed on the bottoms of the source windows 79a and 79b. The heating reaction layers 80a and 80b are generated by heating an electrode base material such as Ni in two stages and causing a solid phase reaction with SiC. The heating reaction layers 80a and 80b have a function of simultaneously providing ohmic contact to both polarities of the n-type source regions 74a and 74b and the p-type base regions 73a and 73b. This is the same as in the first to fourth embodiments. This is a function not found in the ohmic electrode structure of the embodiment. 81 on the back surface of the SiC substrate 171 is another heating reaction layer that plays a role of providing an ohmic contact to the drain of the MOSFET.
A wiring conductor 82 connects the n-type source regions 74a and 74b and the p-type base regions 73a and 73b to an external circuit or another circuit element on the same substrate. Between the wiring conductor 82 and the source / drain heating reaction layers 80a and 80b, a conductor such as Ti, TiN, or TaN having a function of improving the adhesion, contact resistance, and heat resistance of both conductors is inserted. You can also.

  As described above, the method of manufacturing the semiconductor device according to the fifth embodiment includes the steps of growing the epitaxial layer 173 formed on one main surface of the SiC substrate 171 and the predetermined region of the surface layer portion of the epitaxial layer 173. Forming two base regions 73a and 73b that are spaced apart from each other, and forming two source regions 74a and 74b so as to be located in a predetermined region of the surface layer of the two base regions 73a and 73b. And adding a higher concentration impurity than the two base layers 73a and 73b in the surface layer portion of the two base regions 73a and 73b and adjacent to the outer edges of the two source regions 74a and 74b. Forming the two high-concentration impurity base regions 75a and 75b, and the two base regions 73a and 73b and the two source regions 74a and 74. And a step of forming a gate insulating film 75 on the surface of the SiC substrate 171 on which the high concentration impurity base regions 75a and 75b are formed, and a step of forming a gate electrode 76 made of polycrystalline silicon on the gate insulating film 75. A step of thermally oxidizing a part of the gate electrode 76 and covering it with an oxide film 77; and an interlayer insulating film 78 on the gate insulating film 75 and on the gate electrode 76 covered with the oxide film 77. A deposition step; two source windows 79a penetrating the interlayer insulating film 78 and the gate insulating film 75 so as to expose the two source regions 74a and 74b and the two high-concentration impurity base regions 75a and 75b; 79b, a step of forming an electrode base material 87 on the entire surface of the SiC substrate 171 in which the source windows 79a and 79b are opened, and the electrode The SiC substrate 171 having the material 87 formed thereon is subjected to a first heat treatment to form heating reaction layer precursors 88a and 88b at the bottoms of the source windows 79a and 79b, and the SiC substrate subjected to the first heat treatment. A step of removing the remaining unreacted electrode base material 87 from the surface of 171 and a second electrode base material 89 formed on the drain region of the back surface of the SiC substrate 171 from which the unreacted electrode base material 87 has been removed. And a second heat treatment at a temperature equal to or higher than the temperature of the first heat treatment step is performed on the SiC substrate 171 on which the second electrode base material 89 is formed, and two source windows are formed. 79a, 79b bottom and back surface of the drain region surface, the conductive heating reaction layers 80a, 80b are simultaneously generated, and two heating of the bottom of the source windows 79a, 79b covering the interlayer insulating film 78 And providing a wiring conductor 82 connected to the reaction layers 80a and 80b.

  The semiconductor device according to the fifth embodiment is a silicon carbide semiconductor device having a metal-insulating film-semiconductor structure and an ohmic electrode structure on one main surface of SiC substrate 171, and the ohmic electrode The structure is configured by the ohmic electrode structure according to the first embodiment. A silicon carbide semiconductor device having a metal-insulating film-semiconductor gate structure and an ohmic electrode structure on at least the surface of the SiC substrate 171 and an ohmic electrode structure on the other back surface. The ohmic electrode structure is constituted by the ohmic electrode structure according to the first embodiment. Further, it is a metal-insulating film-semiconductor gate structure field effect silicon carbide semiconductor device (MOSFET) or an insulated gate bipolar silicon carbide semiconductor device (IGBT). The insulating film that is a part of the ohmic electrode structure on the surface is a laminated film of a gate insulating film of the MOS gate structure and an interlayer insulating film disposed on the MOS gate structure. In addition, the SiC substrate 171, the epitaxial layer 173 formed on one main surface of the SiC substrate 171, two base regions 73 a and 73 b formed at a predetermined distance from each other in the surface layer portion of the epitaxial layer 173, Two source regions 74a and 74b provided in predetermined regions of the base regions 73a and 73b, and surface layers of the two base regions 73a and 73b, adjacent to the outer edges of the two source regions 74a and 74b, and two bases Two high-concentration impurity base regions 75a and 75b to which impurities higher in concentration than layers 73a and 73b are added, two source regions 74a and 74b, and predetermined epitaxial layer 173 between both source regions 74a and 74b A gate insulating film 75 provided in the region and a gate electrode 76 made of polycrystalline silicon provided on the gate insulating film 75. A gate electrode oxide film 77 formed by thermally oxidizing a part of the gate electrode 76, an interlayer insulating film 78 formed on the gate electrode 76 and the gate electrode oxide film 77, and two source regions 74a, 74b and 2 Two source windows 79a and 79b opened through the interlayer insulating film 78 and the gate insulating film 75 so as to expose the two high-concentration impurity base regions 75a and 75b, and the entire bottom portions of the source windows 79a and 79b are covered. The conductive two heating reaction layers 80a and 80b, the wiring conductor 82 covering the interlayer insulating film 78 and connected to the two heating reaction layers 80a and 80b, and the back surface of the SiC substrate 171 are provided. And a second heating reaction layer 81.

  As is apparent from the above description, the vertical MOSFET according to the present invention has a configuration in which an unreacted high-resistance electrode base material is not interposed between the wiring conductor 82 and the source heating reaction layers 80a and 80b. Thus, the contact resistance of the source contact can be reduced as compared with the conventional contact technique in which the unreacted electrode base material is interposed, and as a result, the source-drain resistance of the transistor can be reduced. In the source vertical MOSFET according to the present invention, the gap between the heating reaction layers 80a and 80b and the side walls of the source windows 79a and 79b can be deleted. The contact size can be reduced, and the size of the MOSFET can be reduced.

Next, a method of manufacturing a MOSFET using the 4H—SiC substrate having the configuration shown in FIG. 21 will be described with reference to FIGS. 22 (A) to 24 (G).
(A) First, after a high-resistance n-type epitaxial layer 173 is grown on a low-resistance n-type 4H—SiC substrate 171 by an atmospheric pressure CVD method, selective ion implantation described in the first embodiment of the present invention is performed. Then, p-type base regions (73a and 73b), n-type source regions (74a and 74b), and p ⁺ -type base regions (75a and 75b) are formed by high-temperature activation annealing. FIG. 22A shows the substrate structure thus formed. An example of the ion implantation conditions for each region is as follows.

◎ Ion implantation conditions for p-type base regions 73a and 73b Ion species Al ⁺
Injection temperature 750 ° C
Acceleration conditions 360 keV, 5.0 × 10 ¹³ / cm ²
◎ Ion implantation conditions for p ⁺ type base regions 75a and 75b Ion species Al ⁺
Injection temperature 750 ° C
Acceleration conditions 30 keV, 1.0 × 10 ¹⁵ / cm ²
50 keV, 1.0 × 10 ¹⁵ / cm ²
70 keV, 2.0 × 10 ¹⁵ / cm ²
100 keV, 3.0 × 10 ¹⁵ / cm ²
◎ Ion implantation conditions for n-type source regions 74a and 74b Ion species P ⁺ (phosphorus)
Injection temperature 500 ° C
Acceleration conditions 40 keV, 5.0 × 10 ¹⁴ / cm ²
70 keV, 6.0 × 10 ¹⁴ / cm ²
100 keV, 1.0 × 10 ¹⁵ / cm ²
160 keV, 2.0 × 10 ¹⁵ / cm ²
In the following description, unless otherwise specified, an SiC substrate 171 having an n-type epitaxial layer 173, each region formed by ion implantation, an insulating film, or an electrode is referred to as an SiC substrate or simply a substrate. Yes.

  (A) Next, the substrate sufficiently cleaned by RCA cleaning or the like is thermally oxidized in a dry oxygen atmosphere to grow a thermal oxide film on the front surface and back surface of the substrate, and immediately removed using a buffered hydrofluoric acid solution. The thickness of the sacrificial oxide film is less than 50 nm, preferably 5 to 20 nm. After the sacrificial oxidation is completed, the substrate is sufficiently cleaned again by RCA cleaning or the like, and then a thick insulating film is formed on the substrate surface by means of thermal oxidation, CVD, etc., using well-known photolithography and wet etching or dry etching. Then, a field (not shown) where the thick oxide film exists and an element region 170 where the thick oxide film is removed are formed (FIG. 22A).

Subsequently, the substrate 171 is again sufficiently cleaned by RCA cleaning or the like, and in the final stage of this cleaning, a buffered hydrofluoric acid solution is used to remove a chemical oxide film (SiO ₂ ) generated on the surface of the element region 170. After immersing for 5 to 10 seconds and completely rinsing the buffered hydrofluoric acid solution with ultrapure water, it is dried and immediately thermally oxidized, as shown in FIG. A gate oxide film 75 having a thickness of (for example, 40 nm in this case) is grown. The conditions for the gate oxidation are not limited to this, but, for example, a dry oxidation at a temperature of 1100 ° C. and a wet oxidation at 950 ° C. are preferable. The important point here is that the thermal oxidation temperature is set higher than any heat treatment temperature in all subsequent processes. Here, in order to realize ohmic contact between the front-side source electrode and the back-side drain electrode, a rapid heating treatment at a temperature of 1000 ° C. was performed later, and an oxidation temperature of 1100 ° C. higher than that was selected. Reference numeral 83 denotes a relatively thick second transient thermal oxide film that is automatically generated on the back surface of the substrate during gate oxidation.

Next, a polycrystalline silicon film 84 having a thickness of 300 to 400 nm is formed on the entire front and back surfaces of the substrate by a low pressure CVD method using a silane material (growth temperature 600 ° C. to 700 ° C.), and then phosphorous chlorate (POCl). ₃ ) P (phosphorus) is added to the polycrystalline silicon film by a known thermal diffusion method (processing temperature: 900 ° C. to 950 ° C.) using oxygen and imparts conductivity. Subsequently, an unnecessary portion of the polycrystalline silicon film on the substrate surface side is applied by applying a photoresist to the substrate surface, and using photolithography and reactive ion etching (RIE) using C ₂ F ₆ and oxygen as an etchant. When the gate electrode 76 is formed by removing the gate electrode 76, the structure shown in FIG.

  (C) Next, the etched substrate 171 is RCA cleaned and sufficiently cleaned, and then thermally oxidized in a dry oxygen atmosphere at 900 ° C., and polycrystalline is formed on the surface of the gate electrode 76 and the polycrystalline silicon film 84 on the back surface. Silicon thermal oxide films 77 and 85 are formed.

Next, as shown in FIG. 22C, an interlayer insulating film 78 is deposited on the entire surface of the substrate 171. As the interlayer insulating film 78, an SiO ₂ film (NSG) having a thickness of about 1 μm formed by atmospheric pressure CVD using silane and oxygen as raw materials, or phosphosilicate glass (PSG) further added with phosphorus, and further boron is added thereto. Boron phosphosilicate glass (BPSG) is suitable, but is not limited to this. Thereafter, the substrate is put into a generally-diffusion furnace, the temperature 950 ° C., subjected to mild heat treatment of tens of minutes at an N ₂ atmosphere, to densify the interlayer insulating film 78. The heat treatment temperature at this time is appropriately selected within a temperature lower than the formation (thermal oxidation) temperature of the gate oxide film 75, for example, in the range of 900 ° C. to 1000 ° C. Subsequently, a dedicated sacrificial layer 86 made of a Si ₃ N ₄ film having a thickness of about 200 nm is placed on the interlayer insulating film 78 by using plasma CVD. Although the Si ₃ N ₄ film sacrificial layer 86 is a temporary film, it may be used as the diffusion prevention insulating film (see 7 in FIG. 12) described in the second embodiment in the first heat treatment step. Function.

(D) Next, using known photolithography and dry / wet etching means, as shown in FIG. 23D, the sacrificial layer 86 on the surface side of the substrate 171, the interlayer insulating film 78, and the gate oxide film 75 are sourced. Windows 79a and 79b are opened. If the etchant reaches the back of the substrate 171 during the opening etching, the polycrystalline silicon oxide film 85 is also removed at the same time (FIG. 23D shows this state).
When the etching is completed, the photoresist is removed, the substrate is sufficiently cleaned by RCA cleaning or the like, and immediately, an electrode base material 87 is vapor-deposited on the entire surface of the substrate using a film forming means such as DC sputtering. As the electrode base material 87, for example, Ni or Co having a thickness of 50 nm can be used.

Subsequently, the first heat treatment is performed on the substrate 171 on which the electrode base material 87 is formed in an inert gas atmosphere such as high-purity Ar or N ₂ as described in (g) in the first embodiment. Then, as shown in FIG. 23D, the heating reaction layer precursor layers (88a, 88b) are formed between the electrode base material 87 and the SiC substrate 171. When Ni is selected as the electrode base material 17, lower silicides such as Ni ₃ Si, Ni ₂ Si, Ni ₃₁ Si ₁₂ and NiSi correspond to this. As a specific example of appropriate heat treatment conditions for an electrode base material Ni having a thickness of 50 nm formed by a DC magnetron sputtering apparatus, the heat treatment temperature is 600 ° C. and the heat treatment time is 3 hours. Since the heating reaction layer precursor layers 88a and 88b are generated from a solid-phase reaction that occurs only in contact with the substrate 171, the heating reaction layer precursor layers 88a and 88b are formed at the bottoms of the source windows (79a and 79b). Are automatically aligned with each other. FIG. 23D shows a cross-sectional structure of the element region 170 at this stage.

(E) After removing the unreacted electrode base material 87 remaining on the substrate after the first heat treatment by the method described in (i) in the first embodiment, the sacrificial layer 86 is removed by etching. The structure is as shown in FIG. Etching of the sacrificial layer 86 can be performed wet using a hot phosphoric acid solution, or by dry etching using CH ₄ or the like. The constituent elements of the electrode base material 87 that diffused slightly toward the interlayer insulating film 78 in the first heat treatment step and remained blocked by the sacrificial layer 86 are completely removed from the surface of the substrate 171 by removing the sacrificial layer 86. Excluded.

(F) Next, the substrate 171 is sufficiently washed and dried, and then a protective resist material (a photoresist may be used) having a thickness of 1 μm or more is applied to the entire surface, and dry etching using CF ₄ and O ₂ is performed. Then, as shown in FIG. 24F, the polycrystalline silicon film 84 on the back surface side is completely removed. After the polycrystalline silicon film 84 is removed from the back surface of the substrate, the temporary thermal oxide film 83 is removed with a BHF solution to expose a clean crystal surface on the back surface of the substrate.
Subsequently, the protective resist material is peeled off, and the substrate is sufficiently washed and dried. Then, the substrate 171 is quickly installed in a vapor deposition apparatus maintained at a high vacuum, and a desired electrode base material 89 is provided on the back surface of the substrate. Is vapor-deposited. As the back electrode base material 89, for example, a 150 nm thick Ni film can be used.
When the film formation of the electrode base material 89 is completed, the substrate 171 is immediately placed in a rapid heat treatment apparatus, and a second heat treatment is performed. This heat treatment is performed in a high-purity Ar atmosphere at 1000 ° C. for 2 minutes by rapid heat treatment (contact annealing). By this heat treatment, as shown in FIG. 24F, the heating reaction layer precursor layers (88a, 88b) of the source windows 79a, 79b are turned into regular heating reaction layers (80a, 80b), and the substrate 171 and electrodes A drain heating reaction layer 81 is also formed between the base material 89.

(G) When the second heat treatment is completed, when the substrate 171 is immersed in a predetermined etching solution that dissolves only the electrode base material, the unreacted electrode base material 89 is removed, and the heating reaction layer 81 is exposed on the back surface of the substrate. The structure is complete. The etching solution used here can be appropriately selected according to the chemical properties of the electrode base material. However, if an appropriate etchant cannot be found, an etchant in which sulfuric acid and hydrogen peroxide solution are mixed at a volume ratio of 4: 1. It is convenient to use This is because this etchant kept at 100 ° C. dissolves most electrode base materials well and hardly dissolves metal silicides and metal carbides. If the selectivity of the electrode base material 89 with respect to the heating reaction layer 81 can be sufficiently secured, the unreacted electrode base material may be removed using dry etching.
Then, after sufficiently cleaning with RCA cleaning or the like and forming a base material film of the wiring conductor 82, such as Al, on the entire surface of the dried SiC substrate 171 by DC magnetron sputtering or the like, a well-known photolithography and dry etching technique (RIE) is performed. And the like, and the photoresist is peeled off, washed and dried, the final structure as shown in FIG.
When a conductor such as Ti, TiN, or TaN having a function of improving the adhesion, contact resistance, and heat resistance of both conductors is inserted between the wiring conductor 82 and the source / drain heating reaction layers 80a and 80b. In this case, after forming these materials first, the base material of the wiring conductor film 82 is formed. When the wiring conductor film base material is Al, the material can usually be continuously patterned with the same etchant gas as Al.
In this way, all the manufacturing steps of the semiconductor device vertical MOSFET in the fifth embodiment of the present invention are completed.

  As is apparent from the above detailed description, the method for manufacturing a SiC semiconductor device vertical MOSFET according to the present invention is a new self-aligned process that does not use any photoresist to dispose a heating reaction layer at the bottom of the source window. (Since FIG. 22C to FIG. 24F are used, problems in the prior art caused by the lift-off method using a photoresist or the like in the same process, (1) the element structure If it becomes finer, contact failure will occur and cleaning cost will increase, (2) resist resist contamination, vapor deposition equipment for Si integrated circuit process can not be shared, dedicated vapor deposition equipment for the same process and dedicated installation of it It can be said that the problem of having to prepare a clean room space is solved at the same time.

In fact, according to the manufacturing method described above, a 50 nm thick Ni is used as the electrode base material 87 of the source / drain heating reaction layers 80 a, 80 b, 81 and a 350 nm thick polycrystalline silicon is used as the gate electrode 76, as shown in FIG. A vertical MOSFET (gate length 2 μm) was manufactured. The impurity concentration of the n-type epitaxial layer 173, the p-type base layers (73a and 73b), the n-type source regions (74a and 74b), and the ion implantation conditions for the p ⁺ -type base regions (75a and 75b) are exemplified in the above manufacturing process. It is as follows. The gate oxide film 75 is a dry oxide film (film thickness of about 40 nm) grown at 1100 ° C. In addition, it has a blocking voltage reinforcement | strengthening structure in the outer peripheral part of an element area | region.

FIG. 25 is a diagram showing a TLM plot (relationship between contact distance and total resistance between contacts) of contacts in n-type source regions (74a and 74b). Since the plots are in a straight line, it can be seen that the contact resistance and the sheet resistance of the source region ((74a and 74b) = high concentration impurity region) are uniform. From the TLM analysis, it was found that the contact resistance of the source was a very low value of ρ _C = 3.6 × 10 ⁻⁶ Ωcm ² . It was found that ohmic contact was obtained from the current-voltage characteristics even in the p ⁺ type base regions (75a, 75b). FIG. 26 shows a TLM plot of the p ⁺ base region (75a, 75b). From this data, the contact resistance of the p ⁺ base region (75a, 75b) was obtained as ρ _C = 2.4 × 10 ⁻³ Ωcm ² . Thus, in the fifth embodiment of the present invention, when at least Ni is used as an electrode base material, n-type source regions (74a and 74b) and p ⁺ -type base regions (75a) having different conductivity types are used. , 75b) can make an ohmic contact at the same time.

Figure 27 is the drain current of the vertical MOSFET - a diagram showing the drain voltage _(I d _{-V ds)} characteristic. The parameter is the gate voltage Vg. The fact that I _d −V _ds extends linearly from the origin suggests that a good ohmic contact is obtained at the source and drain. The blocking voltage of this MOSFET was found to be about 830V. The fact that such a typical transistor static characteristic is obtained indicates that the vertical MOSFET manufacturing method according to the present invention is a practical manufacturing method.
The embodiment described above is described in order to facilitate understanding of the present invention, and is not described in order to limit the present invention. Therefore, each element disclosed in the above embodiment includes all design changes and equivalents belonging to the technical scope of the present invention.

It is sectional drawing which shows the structure of the ohmic electrode structure of the 1st Embodiment of this invention. It is sectional drawing which shows another structure of the ohmic electrode structure of the 1st Embodiment of this invention. It is sectional drawing which shows another structure of the ohmic electrode structure of the 1st Embodiment of this invention. It is sectional process drawing which shows the manufacturing method of the ohmic electrode structure shown in FIG. 1 of the 1st Embodiment of this invention. It is sectional process drawing which shows the manufacturing method of the ohmic electrode structure shown in FIG. 1 of the 1st Embodiment of this invention. It is sectional process drawing which shows the manufacturing method of the ohmic electrode structure shown in FIG. 1 of the 1st Embodiment of this invention. FIG. 5 is a cross-sectional process diagram illustrating a method for manufacturing the ohmic electrode structure shown in FIG. 2 according to the first embodiment of the present invention. It is a cross-sectional process drawing which shows the manufacturing method of the ohmic electrode structure shown in FIG. 3 of the 1st Embodiment of this invention. It is a figure which shows the relationship between the resistance between ohmic contact electrodes calculated | required from the inclination of the current-voltage characteristic of the ohmic electrode structure of the 1st Embodiment of this invention. It is sectional drawing which shows the structure of the ohmic electrode structure of the 2nd Embodiment of this invention. It is sectional drawing which shows another structure of the ohmic electrode structure of the 2nd Embodiment of this invention. It is sectional drawing which shows another structure of the ohmic electrode structure of the 2nd Embodiment of this invention. It is sectional process drawing which shows the manufacturing method of the ohmic electrode structure shown in FIG. 10 of the 2nd Embodiment of this invention. It is sectional process drawing which shows the manufacturing method of the ohmic electrode structure shown in FIG. 10 of the 3rd Embodiment of this invention. It is principal part sectional drawing of SiC-MESFET of the 4th Embodiment of this invention. FIG. 16 is a cross-sectional process diagram illustrating a method of manufacturing the MESFET illustrated in FIG. 15 according to the fourth embodiment of the present invention. FIG. 16 is a cross-sectional process diagram illustrating a method of manufacturing the MESFET illustrated in FIG. 15 according to the fourth embodiment of the present invention. FIG. 16 is a cross-sectional process diagram illustrating a method of manufacturing the MESFET illustrated in FIG. 15 according to the fourth embodiment of the present invention. It is a figure which shows the TLM plot when determining the contact resistance of the source / drain area | region in MESFET of the 4th Embodiment of this invention. The drain current of the MESFET according to the fourth embodiment of the present invention - is a diagram showing the drain voltage _(I d _{-V ds)} characteristic. It is principal part sectional drawing of the SiC-vertical MOSFET of the 5th Embodiment of this invention. FIG. 22 is a sectional process diagram showing a method of manufacturing the vertical MOSFET shown in FIG. 21 according to the fifth embodiment of the present invention. FIG. 22 is a sectional process diagram showing a method of manufacturing the vertical MOSFET shown in FIG. 21 according to the fifth embodiment of the present invention. FIG. 22 is a sectional process diagram showing a method of manufacturing the vertical MOSFET shown in FIG. 21 according to the fifth embodiment of the present invention. It is a figure which shows the TLM plot (relationship between contact distance and total resistance between contacts) of the contact of the n-type source region in the vertical MOSFET according to the fifth embodiment of the present invention. It is a figure which shows the TLM plot of p ⁺ base area | region in the vertical MOSFET of the 5th Embodiment of this invention. Drain current at a vertical MOSFET according to the fifth embodiment of the present invention - is a diagram showing the drain voltage _(I d _{-V ds)} characteristic.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... SiC substrate 2 ... High concentration impurity area | region 3 ... Thick insulating film 4 ... Contact window 5 ... Heating reaction layer 6 ... Wiring conductor 7 ... Diffusion prevention insulating film 8 ... Sacrificial layer 17 ... Electrode base material 18 ... Heating reaction layer precursor Layer 31 ... Thermal oxide film 32 ... CVD oxide film 33 ... Ion implantation mask film 34 ... Ion implantation through film 35 ... Impurity ion 41 ... High concentration impurity epitaxial layer 42 ... Mesa etching mask 45 ... Trench etching mask 46 ... High concentration impurity region Predetermined region 47 ... high-concentration impurity layer 51 ... SiC substrate 52 ... first epitaxial layer 53 ... second epitaxial layer 54 ... element region 55 ... gate window 56 ... source region 56a ... source window 57 ... drain region 57a ... drain window 58 ... Thick insulating film 58a ... channel region 59 ... thermal oxide film 60 ... upper insulating film 63 ... gate window 64 ... additional Thermal reaction layer 65 ... Heating reaction layer 66 ... Gate electrode 67 ... Wiring conductor 68 ... Wiring conductor 69 ... Wiring conductor 70 ... Electrode base material 71 ... Heating reaction layer precursor layer 72 ... Heating reaction layer precursor layer 73a ... p-type base Region 73b ... p-type base region 74a ... n-type source region 74b ... n-type source region 75 ... Gate oxide film 75a ... p ⁺ -type base region 75b ... p ⁺ -type base region 76 ... gate electrode 77 ... polycrystalline silicon oxide film 78 ... Interlayer insulating film 79a ... Source window 79b ... Source window 80a ... Heat reaction layer 80b ... Heat reaction layer 81 ... Heat reaction layer 82 ... Wiring conductor 83 ... Thermal oxide film 84 ... Polycrystalline silicon film 85 ... Polycrystalline silicon oxide film 86 ... Sacrificial layer 87 ... Electrode base material 88a ... Heating reaction layer precursor layer 88b ... Heating reaction layer precursor layer 89 ... Electrode base material 170 ... Element region 171 ... SiC substrate 17 ... n-type epitaxial layer

Claims (24)

Contacting the electrode base material with the high concentration impurity region on the surface of the silicon carbide substrate;
First heat treatment for heat-treating the silicon carbide substrate in contact with the electrode base material to form a heating reaction layer precursor layer between the electrode base material and the silicon carbide substrate including the high-concentration impurity region. Process,
Removing the unreacted electrode base material left on the heating reaction layer precursor layer;
A second heat treatment step of heat-treating the silicon carbide substrate after removing the unreacted electrode base material to convert the heat-reactive layer precursor layer at the bottom of the contact window into the heat-reactive layer;
Disposing a wiring conductor on the heating reaction layer precursor layer after removing the unreacted electrode base material;
The manufacturing method of the ohmic electrode structure characterized by including.   2. The method for manufacturing an ohmic electrode structure according to claim 1, wherein the second heat treatment step is heat-treated at a temperature equal to or higher than a temperature of the first heat treatment step. Selectively forming the high concentration impurity region on the surface of the silicon carbide substrate;
Forming an insulating film on the surface of the silicon carbide substrate including the high concentration impurity region;
Opening the contact window 4 in the insulating film so as to expose the surface of the high concentration impurity region;
Depositing the predetermined electrode base material on the entire surface of the silicon carbide substrate having the contact window opened;
The first heat treatment for heat-treating the silicon carbide substrate on which the electrode base material is formed to form the heating reaction layer precursor layer between the electrode base material and the silicon carbide substrate including the high-concentration impurity region. Process,
Removing the unreacted electrode base material left on the insulating film upper portion and the heating reaction layer precursor layer by chemical means;
The silicon carbide substrate from which the unreacted electrode base material has been removed is heat-treated at a temperature equal to or higher than the temperature of the first heat treatment step, and the heating reaction layer precursor layer at the bottom of the contact window is heated. A second heat treatment step for converting into a reaction layer;
Forming a wiring conductor in contact with the surface of the heating reaction layer at the bottom of the contact window and extending to the top of the insulating film;
The method for producing an ohmic electrode structure according to claim 1, comprising:   4. The step of forming the insulating film on the surface of the silicon carbide substrate including the high-concentration impurity region includes a step of forming a diffusion blocking insulating film that prevents diffusion of the electrode base material. The manufacturing method of the ohmic electrode structure of description. The step of forming the insulating film on the surface of the silicon carbide substrate including the high concentration impurity region includes a step of forming a temporary sacrificial layer,
And the step of removing the unreacted electrode base material left on the subsequent insulating film upper portion and the heated reaction layer precursor layer upper portion by chemical means,
4. The method for manufacturing an ohmic electrode structure according to claim 3, wherein a step of removing the temporary sacrificial layer is added between the subsequent second heat treatment step.   A silicon carbide substrate, a high-concentration impurity region selectively formed on the surface of the silicon carbide substrate, an insulating film placed on the silicon carbide substrate, and the high-concentration impurity region in the insulating film A contact window opened to expose the surface; a heating reaction layer disposed in a self-aligned manner on the bottom of the contact window; and in contact with the surface of the heating reaction layer in the contact window; An ohmic electrode structure comprising: a wiring conductor extended to the top.   The ohmic electrode structure according to claim 6, wherein the heating reaction layer is made of a material mainly containing at least one of a metal silicide and a metal carbide.   At least the lowest end of the heating reaction layer is formed by solid phase thermal reaction between the electrode base material and the silicon carbide substrate, and is formed by removing the unreacted electrode base material remaining on the upper part. 8. The ohmic electrode structure according to claim 6, wherein the ohmic electrode structure has a history.   9. The insulating film according to claim 6, wherein the insulating film is an insulating film having a history after the electrode base material is once mounted, heat-treated at a low temperature, and then removed. Ohmic electrode structure.   The ohmic electrode structure according to any one of claims 6 to 9, wherein the insulating film includes a diffusion blocking insulating film for blocking diffusion of the electrode base material at an upper portion, a lower portion, or an inside thereof.   11. The insulating film has a history of having a temporary sacrificial layer in an upper layer part during a period from film formation to completion of the ohmic electrode structure. The ohmic electrode structure as described.   12. The ohmic electrode structure according to claim 11, wherein the sacrificial layer in the upper part of the insulating film is made of an insulator, a semiconductor, a composite, a mixture, or a laminate thereof.   The ohmic electrode structure according to claim 11 or 12, wherein the sacrificial layer of the upper part of the insulating film has a diffusion preventing function. Selectively forming a high-concentration impurity region on the surface of the silicon carbide substrate;
Forming an insulating film on the surface of the silicon carbide substrate including the high concentration impurity region;
Opening an ohmic contact window in the insulating film to expose the surface of the high-concentration impurity region;
Forming a predetermined electrode base material on the entire surface of the silicon carbide substrate having the ohmic contact window opened;
A first heat treatment step of heat-treating the silicon carbide substrate on which the electrode base material is formed to form a heating reaction layer precursor layer between the electrode base material and the silicon carbide substrate including the high-concentration impurity region. When,
Removing the unreacted electrode base material left on the insulating film upper portion and the heating reaction layer precursor layer by chemical means;
The silicon carbide substrate from which the unreacted electrode base material has been removed is heat-treated at a temperature equal to or higher than the temperature of the first heat treatment step, and the heating reaction layer precursor layer at the bottom of the contact window is heated. A second heat treatment step for converting into a reaction layer;
Opening the Schottky contact window of the silicon carbide substrate after the second heat treatment step;
Disposing an electrode material made of a Schottky electrode material at least at the bottom of the Schottky contact window;
The surface of the heating reaction layer at the bottom of the ohmic contact window or the surface of the electrode material provided on the surface of the heating reaction layer, and the surface of the electrode material provided at the bottom of the Schottky contact window, And forming a wiring conductor extended to the top of the insulating film;
A method for manufacturing a semiconductor device, comprising: Selectively forming the source and drain regions to which conductive impurities are added at a high concentration on the surface of the silicon carbide substrate;
Forming the insulating film on the surface of the silicon carbide substrate including the source and drain regions;
Opening a source window and a drain window in the insulating film so as to expose a surface of the source and drain regions;
Forming a predetermined electrode base material on the entire surface of the silicon carbide substrate having the source window and the drain window opened;
A first heat treatment step of heat-treating the silicon carbide substrate on which the electrode base material is formed to form a heating reaction layer precursor layer between the electrode base material and the silicon carbide substrate including the source and drain regions;
Removing the unreacted electrode base material left on the insulating film upper portion and the heating reaction layer precursor layer by chemical means;
The silicon carbide substrate from which the unreacted electrode base material has been removed is heat-treated again at a temperature equal to or higher than the temperature of the first heat treatment step, and the heated reaction layer precursor at the bottom of the source window and drain window A second heat treatment step for converting the layer into the heat reaction layer;
Opening the gate window of the silicon carbide substrate after the second heat treatment step;
Disposing an electrode material made of a Schottky electrode material at least at the bottom of the gate window;
The surface of the heating reaction layer at the bottom of the source window or drain window or the surface of the electrode material provided on the surface of the heating reaction layer, and the surface of the electrode material provided at the bottom of the Schottky contact window And forming a wiring conductor extended to the top of the insulating film;
The method of manufacturing a semiconductor device according to claim 14, comprising: A silicon carbide semiconductor device having a Schottky electrode structure and an ohmic electrode structure on one main surface of a silicon carbide substrate,
A semiconductor device comprising the ohmic electrode structure according to claim 6. A silicon carbide / metal-semiconductor field effect semiconductor device formed on one main surface of a silicon carbide substrate,
7. A semiconductor device, wherein at least one of a source contact or a drain contact is constituted by the ohmic electrode structure according to claim 6.   A silicon carbide / metal-semiconductor field-effect semiconductor device comprising a source contact or drain contact heating reaction layer and an electrode material formed simultaneously and simultaneously with a gate / Schottky contact between the contact and a wiring conductor 18. The semiconductor device according to claim 17, wherein Growing an epitaxial layer formed on one main surface of the silicon carbide substrate;
Forming two base regions spaced apart from each other in a predetermined region of the surface portion of the epitaxial layer;
Forming two source regions so as to be located in a predetermined region of the surface layer portion of the two base regions;
Forming two high-concentration impurity base regions which are surface layer portions of the two base regions and are adjacent to the outer edges of the two source regions and to which an impurity having a higher concentration is added than the two base layers; When,
Forming a gate insulating film on the surface of the silicon carbide substrate on which the two base regions, the two source regions, and the two high-concentration impurity base regions are formed;
Forming a gate electrode made of polycrystalline silicon on the gate insulating film;
Thermally oxidizing a portion of the gate electrode and coating with an oxide film;
Depositing an interlayer insulating film on the gate insulating film and on the gate electrode covered with the oxide film;
Forming two source windows penetrating the interlayer insulating film and the gate insulating film so as to expose the two source regions and the two high-concentration impurity base regions;
Forming an electrode base material on the entire surface of the silicon carbide substrate having the source window opened;
Applying a first heat treatment to the silicon carbide substrate on which the electrode base material is formed, and forming a heating reaction layer precursor on the bottom of the source window;
Removing the remaining unreacted electrode base material from the surface of the silicon carbide substrate subjected to the first heat treatment;
Forming a second electrode base material in the drain region on the back surface of the silicon carbide substrate from which the unreacted electrode base material has been removed;
The silicon carbide substrate on which the second electrode base material is formed is subjected to a second heat treatment at a temperature equal to or higher than the temperature of the first heat treatment step, and the two source window bottoms and the drains on the back surface Simultaneously producing a conductive heat-reactive layer on the surface of the region;
Providing a wiring conductor covering the interlayer insulating film and connected to the two heating reaction layers at the bottom of the source window;
A method for manufacturing a semiconductor device, comprising: A silicon carbide semiconductor device comprising a metal-insulating film-semiconductor structure and an ohmic electrode structure on one main surface of a silicon carbide substrate,
A semiconductor device comprising the ohmic electrode structure according to claim 6. A silicon carbide semiconductor device comprising a metal-insulating film-semiconductor gate structure and an ohmic electrode structure on at least the surface of a silicon carbide substrate, and comprising an ohmic electrode structure on the other back surface,
The semiconductor device according to claim 6, wherein the ohmic electrode structure on the surface is constituted by the ohmic electrode structure according to claim 6.   The semiconductor device according to claim 21, which is a field effect silicon carbide semiconductor device having a metal-insulating film-semiconductor gate structure or an insulated gate bipolar silicon carbide semiconductor device.   The insulating film which is a part of the ohmic electrode structure on the surface is composed of a laminated film of a gate insulating film of a MOS gate structure and an interlayer insulating film disposed on the top of the MOS gate structure. Item 22. The semiconductor device according to Item 21. A silicon carbide substrate;
An epitaxial layer formed on one main surface of the silicon carbide substrate;
Two base regions formed apart from each other in a predetermined region in the surface layer portion of the epitaxial layer;
Two source regions provided in a predetermined region of the two base regions;
Two high-concentration impurity base regions, which are surface layer portions of the two base regions, adjacent to the outer edges of the two source regions, and doped with a higher concentration of impurities than the two base layers;
A gate insulating film provided in a predetermined region on the epitaxial layer on the two source regions and between the two source regions;
A gate electrode made of polycrystalline silicon provided on the gate insulating film;
A gate electrode oxide film formed by thermally oxidizing a part of the gate electrode;
An interlayer insulating film formed on the gate electrode and the gate electrode oxide film;
Two source windows opened through the interlayer insulating film and the gate insulating film so as to expose the two source regions and the two high-concentration impurity base regions;
Two conductive heating reaction layers provided to cover the entire bottom surface of the source window;
A wiring conductor covering the interlayer insulating film and connected to the two heating reaction layers;
A second heating reaction layer provided on the back surface of the silicon carbide substrate;
The semiconductor device according to claim 21, further comprising:

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