JP7286450B2 - 電子装置及び電子装置の製造方法 - Google Patents
電子装置及び電子装置の製造方法 Download PDFInfo
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/492—Bases or plates or solder therefor
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4825—Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49537—Plurality of lead frames mounted in one device
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
- H01L23/49582—Metallic layers on lead frames
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Lead Frames For Integrated Circuits (AREA)
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Description
102 ソルダーレジスト層
103 外部端子
110 第1金属層
110a 第1金属板
110b、120b 枠
110c 溝
111、121 電解めっき層
112 部品載置部
113、114 他層支持部
115 端子部
120 第2金属層
120a 第2金属板
122 接続部
123 電極パッド部
124 給電部
130 ICチップ
140 電極
150 絶縁性樹脂
210 回路基板
220 受動部品
Claims (9)
- 第1金属層と、
前記第1金属層上に設けられた電子部品と、
前記第1金属層上及び前記電子部品上に設けられた第2金属層と、
前記第1金属層と前記第2金属層との間を充填し、前記電子部品を被覆する絶縁樹脂とを有し、
前記第2金属層は、
互いに対向して配置される矩形面状の第1電極パッド部及び矩形面状の第2電極パッド部と、
前記第1電極パッド部の周縁の前記第2電極パッド部とは反対側の一辺に沿って前記第1電極パッド部から前記第1金属層の方向へ突出し、前記第2金属層を前記第1金属層と電気的に接続し、前記一辺に沿う方向の長さが前記一辺の長さよりも短い第1接続部と、
前記第2電極パッド部の周縁の前記第1電極パッド部とは反対側の一辺に沿って前記第2電極パッド部から前記第1金属層の方向へ突出し、前記第2金属層を前記第1金属層と電気的に接続し、前記一辺に沿う方向の長さが前記一辺の長さよりも短い第2接続部と
を有する
ことを特徴とする電子装置。 - 前記第1接続部及び前記第2接続部の各々の高さは、
前記電子部品の高さよりも高い
ことを特徴とする請求項1記載の電子装置。 - 前記第1電極パッド部及び前記第2電極パッド部は、
前記電子部品と重なる位置に設けられ、前記絶縁樹脂から露出する面を有する
ことを特徴とする請求項1記載の電子装置。 - 前記第1金属層は、
前記電子部品を載置する載置部と、
前記第1接続部及び前記第2接続部に接触して前記第2金属層を支持する支持部と、
前記載置部に載置された前記電子部品の端子から自装置の外周まで延びる端子部と
を有することを特徴とする請求項1記載の電子装置。 - 自装置の外周において露出する前記端子部の端面を被覆するめっき層
をさらに有することを特徴とする請求項4記載の電子装置。 - 前記めっき層は、
前記支持部の前記第1接続部及び前記第2接続部に接触する面に隣接する側面であって自装置の外周において露出する側面を被覆する
ことを特徴とする請求項5記載の電子装置。 - 前記端子部は、
互いに分離する複数の金属板を有し、
前記第2金属層は、
前記第1電極パッド部及び前記第2電極パッド部の周囲に、前記複数の金属板にそれぞれ接続する複数の給電部を有する
ことを特徴とする請求項4記載の電子装置。 - 自装置の外周において、前記第1金属層の周囲の前記絶縁樹脂の側面が、前記第2金属層の周囲の前記絶縁樹脂の側面よりも自装置の外周から内側に後退して位置し、
前記端子部の側面は、自装置の外周から内側に後退した位置で、前記第1金属層の周囲の前記絶縁樹脂の側面から露出する
ことを特徴とする請求項4記載の電子装置。 - 電子部品の搭載部を備える第1金属層を形成する工程と、
互いに対向して配置される矩形面状の第1電極パッド部及び矩形面状の第2電極パッド部と、前記第1電極パッド部の周縁の前記第2電極パッド部とは反対側の一辺に沿って前記第1電極パッド部から突出し、前記一辺に沿う方向の長さが前記一辺の長さよりも短い第1接続部と、前記第2電極パッド部の周縁の前記第1電極パッド部とは反対側の一辺に沿って前記第2電極パッド部から前記第1金属層の方向へ突出し、前記一辺に沿う方向の長さが前記一辺の長さよりも短い第2接続部とを備える第2金属層を形成する工程と、
前記第1金属層に前記電子部品を搭載する工程と、
前記電子部品を挟むように前記第1金属層上に前記第2金属層を積層し、前記第1接続部及び前記第2接続部を前記第1金属層に接合する工程と、
前記第1金属層及び前記第2金属層の間に、前記電子部品、前記第1接続部及び前記第2接続部を被覆する絶縁樹脂を充填する工程と
を有することを特徴とする電子装置の製造方法。
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JP2019128795A JP7286450B2 (ja) | 2019-07-10 | 2019-07-10 | 電子装置及び電子装置の製造方法 |
US16/922,614 US11227813B2 (en) | 2019-07-10 | 2020-07-07 | Electronic apparatus |
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US20220189858A1 (en) * | 2020-12-11 | 2022-06-16 | Microchip Technology Incorporated | Semiconductor device packages including multiple lead frames and related methods |
Citations (5)
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US20080054438A1 (en) | 2006-08-30 | 2008-03-06 | Semiconductor Components Industries, Llc | Semiconductor package structure having multiple heat dissipation paths and method of manufacture |
JP2008258411A (ja) | 2007-04-05 | 2008-10-23 | Rohm Co Ltd | 半導体装置および半導体装置の製造方法 |
US20110285009A1 (en) | 2010-05-24 | 2011-11-24 | Chi Heejo | Integrated circuit packaging system with dual side connection and method of manufacture thereof |
JP2018125403A (ja) | 2017-01-31 | 2018-08-09 | 株式会社加藤電器製作所 | 電子デバイス及び電子デバイスの製造方法 |
JP2018137466A (ja) | 2012-03-23 | 2018-08-30 | 日本テキサス・インスツルメンツ株式会社 | モジュールとして構成されるマルチレベルリードフレームを有するパッケージングされた半導体デバイス |
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US8035221B2 (en) * | 2007-11-08 | 2011-10-11 | Intersil Americas, Inc. | Clip mount for integrated circuit leadframes |
US8883567B2 (en) * | 2012-03-27 | 2014-11-11 | Texas Instruments Incorporated | Process of making a stacked semiconductor package having a clip |
CN207217523U (zh) | 2014-11-12 | 2018-04-10 | 株式会社村田制作所 | 复合电子部件、电路模块以及dcdc转换器模块 |
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- 2019-07-10 JP JP2019128795A patent/JP7286450B2/ja active Active
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- 2020-07-07 US US16/922,614 patent/US11227813B2/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080054438A1 (en) | 2006-08-30 | 2008-03-06 | Semiconductor Components Industries, Llc | Semiconductor package structure having multiple heat dissipation paths and method of manufacture |
JP2008258411A (ja) | 2007-04-05 | 2008-10-23 | Rohm Co Ltd | 半導体装置および半導体装置の製造方法 |
US20110285009A1 (en) | 2010-05-24 | 2011-11-24 | Chi Heejo | Integrated circuit packaging system with dual side connection and method of manufacture thereof |
JP2018137466A (ja) | 2012-03-23 | 2018-08-30 | 日本テキサス・インスツルメンツ株式会社 | モジュールとして構成されるマルチレベルリードフレームを有するパッケージングされた半導体デバイス |
JP2018125403A (ja) | 2017-01-31 | 2018-08-09 | 株式会社加藤電器製作所 | 電子デバイス及び電子デバイスの製造方法 |
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