JP7243737B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP7243737B2 JP7243737B2 JP2020557047A JP2020557047A JP7243737B2 JP 7243737 B2 JP7243737 B2 JP 7243737B2 JP 2020557047 A JP2020557047 A JP 2020557047A JP 2020557047 A JP2020557047 A JP 2020557047A JP 7243737 B2 JP7243737 B2 JP 7243737B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/564—Details not otherwise provided for, e.g. protection against moisture
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3178—Coating or filling in grooves made in the semiconductor body
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
- H10D62/8325—Silicon carbide
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/111—Field plates
- H10D64/112—Field plates comprising multiple field plate segments
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3192—Multilayer coating
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
- H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]
- H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
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- H—ELECTRICITY
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- General Physics & Mathematics (AREA)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Description
図1は、実施の形態1に係る半導体装置を示す平面図である。半導体基板1の中央部は電流が流れる有効領域2である。有効領域2にトランジスタ又はダイオードが設けられている。有効領域2の周りを囲むように半導体基板1の上面に複数のガードリング3が設けられている。
図3は、実施の形態2に係る半導体装置を示す断面図である。終端領域7において酸化膜4と有機絶縁膜6の間に複数の密着膜9が選択的に設けられている。密着膜9と有機絶縁膜6の密着性は有機絶縁膜6と酸化膜4の密着性よりも高い。密着膜9と酸化膜4の密着性は有機絶縁膜6と酸化膜4の密着性よりも高い。この密着膜9を設けることで有機絶縁膜6と酸化膜4の密着性が向上する。そして、密着膜9により水分の進展する界面が凸状になり、水分が最外周のガードリング3に達するまでの沿面距離が長くなる。この結果、耐湿性を更に向上することができる。
Claims (8)
- 半導体基板と、
前記半導体基板の上面に設けられた酸化膜と、
前記半導体基板の前記上面に設けられたガードリングと、
前記ガードリングと前記半導体基板の外端部との間の終端領域において前記酸化膜に直接的に接する有機絶縁膜とを備え、
前記終端領域において前記半導体基板の前記上面に溝が設けられ、
前記酸化膜が前記溝の内部に設けられ、
前記溝は前記有機絶縁膜で埋め込まれていることを特徴とする半導体装置。 - 半導体基板と、
前記半導体基板の上面に設けられた酸化膜と、
前記半導体基板の前記上面に設けられたガードリングと、
前記ガードリングと前記半導体基板の外端部との間の終端領域において前記酸化膜に直接的に接する有機絶縁膜と、
前記終端領域において前記酸化膜と前記有機絶縁膜の間に設けられた密着膜とを備え、
前記終端領域において前記半導体基板の前記上面に溝が設けられ、
前記溝は前記有機絶縁膜で埋め込まれ、
前記密着膜と前記有機絶縁膜の密着性は前記有機絶縁膜と前記酸化膜の密着性よりも高く、
前記密着膜と前記酸化膜の密着性は前記有機絶縁膜と前記酸化膜の密着性よりも高いことを特徴とする半導体装置。 - 前記密着膜の一部は前記有機絶縁膜から前記半導体基板の外側方向に突き出していることを特徴とする請求項2に記載の半導体装置。
- 前記密着膜は複数設けられていることを特徴とする請求項2又は3に記載の半導体装置。
- 前記密着膜はテトラエトキシシラン膜であることを特徴とする請求項2~4の何れか1項に記載の半導体装置。
- 前記ガードリングを覆う絶縁保護膜を更に備え、
前記密着膜は前記絶縁保護膜と同じ材料からなることを特徴とする請求項2~4の何れか1項に記載の半導体装置。 - 前記有機絶縁膜はポリイミドであることを特徴とする請求項1~6の何れか1項に記載の半導体装置。
- 前記半導体基板はワイドバンドギャップ半導体からなることを特徴とする請求項1~7の何れか1項に記載の半導体装置。
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PCT/JP2018/042708 WO2020105097A1 (ja) | 2018-11-19 | 2018-11-19 | 半導体装置 |
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JPWO2020105097A1 JPWO2020105097A1 (ja) | 2021-09-27 |
JP7243737B2 true JP7243737B2 (ja) | 2023-03-22 |
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US (1) | US12087706B2 (ja) |
JP (1) | JP7243737B2 (ja) |
CN (1) | CN113039649B (ja) |
DE (1) | DE112018008147T5 (ja) |
WO (1) | WO2020105097A1 (ja) |
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US20230369392A1 (en) * | 2020-11-27 | 2023-11-16 | Rohm Co., Ltd. | Semiconductor device |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2007246807A (ja) | 2006-03-17 | 2007-09-27 | Toppan Printing Co Ltd | 積層フィルムの製造方法 |
WO2008044801A1 (en) | 2006-10-13 | 2008-04-17 | Sanyo Electric Co., Ltd. | Semiconductor device and method for manufacturing the same |
JP2009152457A (ja) | 2007-12-21 | 2009-07-09 | Sanyo Electric Co Ltd | メサ型半導体装置及びその製造方法 |
JP2010147065A (ja) | 2008-12-16 | 2010-07-01 | Hitachi Ltd | 縦型半導体装置及びその製造方法 |
JP2014220463A (ja) | 2013-05-10 | 2014-11-20 | 住友電工デバイス・イノベーション株式会社 | 半導体装置 |
JP2015032664A (ja) | 2013-08-01 | 2015-02-16 | 住友電気工業株式会社 | ワイドバンドギャップ半導体装置 |
WO2016166808A1 (ja) | 2015-04-14 | 2016-10-20 | 三菱電機株式会社 | 半導体装置 |
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JP2009021526A (ja) * | 2007-07-13 | 2009-01-29 | Toshiba Corp | 電力用半導体装置及びその製造方法 |
JP5955963B2 (ja) * | 2012-07-19 | 2016-07-20 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP6231377B2 (ja) * | 2013-12-25 | 2017-11-15 | トヨタ自動車株式会社 | 半導体装置及び半導体装置の製造方法 |
JP6274968B2 (ja) | 2014-05-16 | 2018-02-07 | ローム株式会社 | 半導体装置 |
JP6627445B2 (ja) * | 2015-11-16 | 2020-01-08 | 富士電機株式会社 | 半導体装置 |
JP6545288B2 (ja) * | 2016-01-21 | 2019-07-17 | 三菱電機株式会社 | 半導体装置 |
JP6760134B2 (ja) * | 2017-03-01 | 2020-09-23 | 株式会社豊田中央研究所 | 半導体装置 |
US10790365B2 (en) * | 2018-02-23 | 2020-09-29 | Vanguard International Semiconductor Corporation | Lateral diffused metal oxide semiconductor field effect transistor |
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2018
- 2018-11-19 US US15/734,477 patent/US12087706B2/en active Active
- 2018-11-19 JP JP2020557047A patent/JP7243737B2/ja active Active
- 2018-11-19 DE DE112018008147.8T patent/DE112018008147T5/de active Pending
- 2018-11-19 CN CN201880099534.0A patent/CN113039649B/zh active Active
- 2018-11-19 WO PCT/JP2018/042708 patent/WO2020105097A1/ja active Application Filing
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007246807A (ja) | 2006-03-17 | 2007-09-27 | Toppan Printing Co Ltd | 積層フィルムの製造方法 |
WO2008044801A1 (en) | 2006-10-13 | 2008-04-17 | Sanyo Electric Co., Ltd. | Semiconductor device and method for manufacturing the same |
JP2009152457A (ja) | 2007-12-21 | 2009-07-09 | Sanyo Electric Co Ltd | メサ型半導体装置及びその製造方法 |
JP2010147065A (ja) | 2008-12-16 | 2010-07-01 | Hitachi Ltd | 縦型半導体装置及びその製造方法 |
JP2014220463A (ja) | 2013-05-10 | 2014-11-20 | 住友電工デバイス・イノベーション株式会社 | 半導体装置 |
JP2015032664A (ja) | 2013-08-01 | 2015-02-16 | 住友電気工業株式会社 | ワイドバンドギャップ半導体装置 |
WO2016166808A1 (ja) | 2015-04-14 | 2016-10-20 | 三菱電機株式会社 | 半導体装置 |
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Publication number | Publication date |
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CN113039649B (zh) | 2024-07-02 |
JPWO2020105097A1 (ja) | 2021-09-27 |
US20210233873A1 (en) | 2021-07-29 |
US12087706B2 (en) | 2024-09-10 |
WO2020105097A1 (ja) | 2020-05-28 |
CN113039649A (zh) | 2021-06-25 |
DE112018008147T5 (de) | 2021-07-29 |
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