JP5954140B2 - Silicon carbide semiconductor device - Google Patents

Description

  The present invention relates to a silicon carbide semiconductor device and a method for manufacturing the same.

  In order to increase the breakdown voltage of the vertical semiconductor device, a termination structure that relaxes the electric field can be used. Known termination structures include JTE (Junction Termination Extension), FLR (Field Limiting Ring) (also referred to as guard ring), and the like. For example, according to Shiro Hino et al., “SiC-MOSFET structure enabling fast turn-on and -off switching”, Material Science Forum, Vols. 717-720 (2012), pp. 1097-1100 (Non-Patent Document 1). For example, in an n-channel double injection MOSFET (Metal Oxide Semiconductor Field Effect Transistor), a p-well is provided on the silicon carbide substrate. The outer peripheral p-well is covered with a field oxide film (insulating film).

Shiro Hino et al., "SiC-MOSFET structure enabling fast turn-on and -off switching", Material Science Forum, Vols. 717-720 (2012), pp. 1097-1100

  As described above, the interface between the silicon carbide substrate and the insulating film is formed in the termination structure. The easier the current along this interface flows, the greater the leakage current of the silicon carbide semiconductor device. Therefore, a termination structure that can reduce such a leakage current is desired.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a silicon carbide semiconductor device capable of suppressing leakage current and a method for manufacturing the same.

  A silicon carbide semiconductor device according to one aspect of the present invention includes an element portion in which a semiconductor element is provided and a terminal portion surrounding the element portion. The silicon carbide semiconductor device has a silicon carbide substrate, a gate insulating film, a gate electrode, a first main electrode, a second main electrode, and a sidewall insulating film. The silicon carbide substrate is made of silicon carbide having a hexagonal single crystal structure. The silicon carbide substrate has a first main surface and a second main surface opposite to the first main surface. The first main surface has a flat surface located at the element portion, and a side wall surface that is located at the terminal portion, surrounds the flat surface, and is inclined with respect to the flat surface so as to approach the second main surface. . The silicon carbide substrate is provided on the first impurity region having the first conductivity type, the second impurity region having the second conductivity type provided on the first impurity region, and the second impurity region. And a third impurity region separated from the first impurity region by the second impurity region. Each of the first to third impurity regions has a portion located on a flat surface. The gate insulating film connects the first and third impurity regions to each other on the flat surface of the first main surface. The gate electrode is provided on the gate insulating film. The first main electrode is in contact with the third impurity region on the flat surface of the first main surface. The second main electrode is provided on the second main surface. The sidewall insulating film covers the sidewall surface of the first main surface. The side wall surface is inclined by 50 degrees or more and 80 degrees or less with respect to the {000-1} plane.

  According to the silicon carbide semiconductor device according to the above aspect, the side wall surface disposed at the terminal end is inclined at 50 degrees or more and 80 degrees or less with respect to the {000-1} plane. Thereby, the interface state density at the interface between the side wall surface of the silicon carbide substrate and the side wall insulating film can be lowered at the terminal portion. Therefore, generation of current due to the presence of the interface state is suppressed. Therefore, leakage current of the silicon carbide semiconductor device can be suppressed.

  Preferably, the side wall surface of the first main surface of the silicon carbide substrate includes a first surface having a plane orientation {0-33-8}. More preferably, the side wall surface of the first main surface of the silicon carbide substrate microscopically includes the first surface, and the side wall surface further finely defines the second surface having the plane orientation {0-11-1}. Includes visually. More preferably, the first and second surfaces of the side wall surface of the first main surface of the silicon carbide substrate constitute a composite surface having a plane orientation {0-11-2}. Thereby, the leakage current of the silicon carbide semiconductor device can be more reliably suppressed.

  A silicon carbide semiconductor device according to another aspect of the present invention has an element portion in which a semiconductor element is provided and a terminal portion surrounding the element portion. The silicon carbide semiconductor device has a silicon carbide substrate, a gate insulating film, a gate electrode, a first main electrode, a second main electrode, and a sidewall insulating film. The silicon carbide substrate is made of silicon carbide having a hexagonal single crystal structure. The silicon carbide substrate has a first main surface and a second main surface opposite to the first main surface. The first main surface has a flat surface located at the element portion, and a side wall surface that is located at the terminal portion, surrounds the flat surface, and is inclined with respect to the flat surface so as to approach the second main surface. . The silicon carbide substrate is provided on the first impurity region having the first conductivity type, the second impurity region having the second conductivity type provided on the first impurity region, and the second impurity region. And a third impurity region separated from the first impurity region by the second impurity region. Each of the first to third impurity regions has a portion located on a flat surface. The gate insulating film connects the first and third impurity regions to each other on the flat surface of the first main surface. The gate electrode is provided on the gate insulating film. The first main electrode is in contact with the third impurity region on the flat surface of the first main surface. The second main electrode is provided on the second main surface. The sidewall insulating film covers the sidewall surface of the first main surface. The side wall surface has one of the plane orientations {0-33-8}, {0-11-2}, {0-11-4} and {0-11-1} when viewed macroscopically.

  According to the silicon carbide semiconductor device according to the other aspect described above, the side wall surface disposed at the terminal portion is macroscopically viewed from the plane orientation {0-33-8}, {0-11-2}, {0- 11-4} and {0-11-1}. Thereby, the interface state density at the interface between the side wall surface of the silicon carbide substrate and the side wall insulating film can be lowered at the terminal portion. Therefore, generation of current due to the presence of the interface state is suppressed. Therefore, leakage current of the silicon carbide semiconductor device can be suppressed.

  Preferably, a sidewall impurity region having the second conductivity type and connected to the third impurity region is provided on the sidewall surface of the first main surface of the silicon carbide substrate. Thereby, the withstand voltage of the silicon carbide semiconductor device can be increased by reducing the electric field concentration.

  Preferably, the first main surface of the silicon carbide substrate has a bottom surface surrounding the side wall surface at the terminal end, and the bottom surface has a smaller inclination with respect to the flat surface than the inclination of the side wall surface with respect to the flat surface. . Thereby, a structure for relaxing electric field concentration can be provided on the bottom surface of the terminal portion.

  Preferably, a guard ring region is provided on the bottom surface of the first main surface of the silicon carbide substrate and has the second conductivity type and is separated from the side wall surface and surrounds the side wall surface. Thereby, the withstand voltage of the silicon carbide semiconductor device can be increased by reducing the electric field concentration.

  A method for manufacturing a silicon carbide semiconductor device of the present invention is a method for manufacturing a silicon carbide semiconductor device having an element portion provided with a semiconductor element and a terminal portion surrounding the element portion, and includes the following steps: . A silicon carbide substrate made of silicon carbide having a hexagonal single crystal structure is prepared. The silicon carbide substrate has a first main surface and a second main surface opposite to the first main surface. The first main surface has a flat surface located at the element portion, and a side wall surface that is located at the terminal portion, surrounds the flat surface, and is inclined with respect to the flat surface so as to approach the second main surface. . The silicon carbide substrate is provided on the first impurity region having the first conductivity type, the second impurity region having the second conductivity type provided on the first impurity region, and the second impurity region. And a third impurity region separated from the first impurity region by the second impurity region. Each of the first to third impurity regions has a portion located on a flat surface. The step of preparing the silicon carbide substrate is performed by heating the silicon carbide substrate while bringing a gas containing a halogen element into contact with a part of the first main surface of the silicon carbide substrate. A step of forming a side wall surface by removing a part of the film by etching. A gate insulating film that connects the first impurity region and the third impurity region to each other is formed on the flat surface of the first main surface. A sidewall insulating film is formed to cover the sidewall surface of the first main surface. A gate electrode is formed on the gate insulating film. A first main electrode in contact with the third impurity region is formed on the flat surface of the first main surface. A second main electrode is formed on the second main surface.

  According to the manufacturing method, the side wall surface is formed by thermal etching. By using thermal etching, the surface orientation of the side wall surface can be made suitable for suppressing the interface state between the side wall surface and the side wall insulating film. Therefore, generation of current due to the presence of the interface state is suppressed. Therefore, leakage current of the silicon carbide semiconductor device can be suppressed.

  According to the present invention, the leakage current of the silicon carbide semiconductor device can be suppressed as described above.

1 is a plan view schematically showing a configuration of a silicon carbide semiconductor device in one embodiment of the present invention. FIG. 2 is a schematic partial cross-sectional view taken along line II-II in FIG. 1. FIG. 2 is a partially enlarged view of FIG. 1. FIG. 4 is a plan view of a silicon carbide substrate corresponding to the visual field of FIG. 3. FIG. 6 is a partial cross sectional view schematically showing a first step of the method for manufacturing the silicon carbide semiconductor device of FIG. 2. FIG. 6 is a partial cross sectional view schematically showing a second step of the method for manufacturing the silicon carbide semiconductor device of FIG. 2. FIG. 11 is a partial cross sectional view schematically showing a third step of the method for manufacturing the silicon carbide semiconductor device of FIG. 2. FIG. 10 is a partial cross sectional view schematically showing a fourth step of the method for manufacturing the silicon carbide semiconductor device of FIG. 2. FIG. 10 is a partial cross sectional view schematically showing a fifth step of the method for manufacturing the silicon carbide semiconductor device of FIG. 2. FIG. 12 is a partial cross sectional view schematically showing a sixth step of the method for manufacturing the silicon carbide semiconductor device of FIG. 2. FIG. 12 is a partial cross sectional view schematically showing a seventh step of the method for manufacturing the silicon carbide semiconductor device of FIG. 2. FIG. 12 is a partial cross sectional view schematically showing an eighth step of the method for manufacturing the silicon carbide semiconductor device of FIG. 2. FIG. 12 is a partial cross sectional view schematically showing a ninth step of the method for manufacturing the silicon carbide semiconductor device of FIG. 2. It is a fragmentary sectional view showing roughly the example of the fine structure of the side wall surface of the silicon carbide substrate which a silicon carbide semiconductor device has. It is a figure which shows the crystal structure of the (000-1) plane in the hexagonal crystal of polytype 4H. It is a figure which shows the crystal structure of the (11-20) plane which follows the line XVI-XVI of FIG. It is a figure which shows the crystal structure in the surface vicinity of the composite surface of FIG. 14 in (11-20) plane. It is the figure which looked at the compound surface of Drawing 14 from the (01-10) plane. It is a figure which shows the modification of FIG.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated. In the crystallographic description in this specification, individual planes are indicated by (), and aggregate planes are indicated by {}. In addition, in order to indicate that the index of the surface is negative, a negative sign is attached in front of the numeral instead of adding “-” (bar) above the numeral.

(Configuration of silicon carbide semiconductor device)
As shown in FIG. 1 and FIG. 2, MOSFET 100 (silicon carbide semiconductor device) has an element portion CL provided with a transistor element (semiconductor element) and a termination portion TM surrounding element portion CL. is there. The MOSFET 100 includes an epitaxial substrate 10 (silicon carbide substrate), an insulating film 21, an interlayer insulating film 29, a gate electrode 30, a source electrode 31 (first main electrode), and a drain electrode 42 (second main electrode). ), A gate runner 50, a wiring layer 51, and a gate pad 59.

  Epitaxial substrate 10 is made of silicon carbide having a hexagonal single crystal structure. The single crystal structure preferably has polytype 4H. Epitaxial substrate 10 has an upper surface P1 (first main surface) and a back surface P2 (second main surface opposite to the first main surface). Upper surface P1 has flat surface FT, side wall surface ST, and bottom surface BT. The flat surface FT is located in the element part CL. Side wall surface ST and bottom surface BT are located at terminal end TM. Side wall surface ST surrounds flat surface FT and is inclined with respect to flat surface FT so as to approach back surface P2. The bottom surface BT surrounds the side wall surface ST at the terminal end TM. The bottom surface BT has a smaller inclination with respect to the flat surface FT than the inclination of the side wall surface ST with respect to the flat surface FT. Here, “smaller inclination” is a concept including no inclination, that is, including parallelism. Therefore, the bottom surface BT may be substantially parallel to the flat surface FT, as shown in FIG.

  The flat surface FT of the upper surface P1 is preferably substantially parallel to the {000-1} plane. Specifically, the inclination of the flat surface FT with respect to the {000-1} plane is preferably within 10 degrees, and more preferably within 5 degrees.

  Side wall surface ST of upper surface P1 is inclined by 50 degrees or more and 80 degrees or less with respect to the {000-1} plane.

  The side wall surface ST of the upper surface P1 is one of the plane orientations {0-33-8}, {0-11-2}, {0-11-4}, and {0-11-1} when viewed macroscopically. You may have. The plane orientation {0-33-8} has an off angle of 54.7 degrees from the {000-1} plane. The plane orientation {0-11-1} has an off angle of 75.1 degrees from the {000-1} plane. Accordingly, the plane orientations {0-33-8}, {0-11-2}, {0-11-4}, and {0-11-1} correspond to off-angles of 54.7 to 75.1 degrees. Considering that a manufacturing error of about 5 degrees is assumed for the off angle, the side wall surface ST of the upper surface P1 is processed so as to be inclined at about 50 degrees to 80 degrees with respect to the {000-1} plane. The macroscopic orientation of the side wall surface ST is easily set to any one of {0-33-8}, {0-11-2}, {0-11-4}, and {0-11-1}.

  The side wall surface ST as described above tends to have a “special surface”. Details of the special surface will be described later.

  The epitaxial substrate 10 includes a single crystal substrate 19, an n drift region 11 (first impurity region), a p body region 12 (second impurity region), an n source region 13 (third impurity region), JTE region 14 (side wall impurity region), guard ring region 15, field stop region 16, and p contact region 17 are provided.

  Single crystal substrate 19 has n-type conductivity. N drift region 11 has n type (first conductivity type). P body region 12 is provided on n drift region 11 and has p type (second conductivity type different from the first conductivity type). N source region 13 is provided on body region 12 and is separated from n drift region 11 by p body region 12. Each of n drift region 11, p body region 12, n source region 13, and p contact region 17 has a portion located on flat surface FT of upper surface P1. The p contact region 17 is connected to the p body region 12. The impurity concentration of p contact region 17 is higher than the impurity concentration of p body region 12.

  JTE region 14 has a p-type. JTE region 14 is provided on side wall surface ST of upper surface P <b> 1 and is connected to p body region 12. The impurity concentration of JTE region 14 is lower than the impurity concentration of p body region 12. Guard ring region 15 has a p-type. The guard ring region 15 is provided on the bottom surface BT of the upper surface P1 of the epitaxial substrate 10, is separated from the side wall surface ST, and surrounds the side wall surface ST. Field stop region 16 has an n type and has an impurity concentration higher than that of n drift region 11. Field stop region 16 surrounds side wall surface ST.

  The insulating film 21 includes a gate insulating film 21G and a sidewall insulating film 21S. The gate insulating film 21G connects the n drift region 11 and the n source region 13 to each other on the flat surface FT of the upper surface P1. As a result, a channel surface is formed on the flat surface FT. The side wall insulating film 21S covers the side wall surface ST and the bottom surface BT of the upper surface P1.

  The gate electrode 30 is provided on the gate insulating film 21G. The gate runner 50 and the gate pad 59 (FIG. 1) are provided on the gate electrode 30 and are made of a conductor. The source electrode 31 is an ohmic electrode in contact with the n source region 13 and the p contact region 17 on the flat surface FT of the upper surface P1. The wiring layer 51 is provided on the source electrode 31 and the interlayer insulating film 29. The drain electrode 42 is an ohmic electrode provided on the back surface P2. The gate runner 50 is for suppressing a potential difference in the gate electrode 30.

  As shown in FIG. 3, the boundary between the element part CL and the terminal part TM in a plan view may include a zigzag shape. In this zigzag shape, the angle DC of the part protruding from the element part CL to the terminal part TM is preferably 60 degrees. In this zigzag shape, the angle DT of the portion protruding from the terminal portion TM to the element portion CL is preferably 60 degrees. 60 degrees is preferable because the epitaxial substrate 10 has a hexagonal crystal structure and this crystal structure has sixfold symmetry. As shown in FIG. 4, side wall surface ST is preferably arranged along the zigzag shape, and bottom surface BT is provided so as to be adjacent to the zigzag shape via side wall surface ST.

(Method for manufacturing silicon carbide semiconductor device)
Next, a method for manufacturing MOSFET 100 (FIG. 2) will be described.

Referring to FIG. 5, n drift region 11 forming upper surface P <b> 1 is formed by epitaxial growth of silicon carbide on single crystal substrate 19. Thereby, epitaxial substrate 10 having single crystal substrate 19 and n drift region 11 is formed. Epitaxial growth can be performed by a CVD (Chemical Vapor Deposition) method. At this time, hydrogen gas may be used as the carrier gas. As the source gas, for example, a mixed gas of silane (SiH ₄ ) and propane (C ₃ H ₈ ) can be used. At this time, for example, nitrogen (N) or phosphorus (P) is preferably introduced as an impurity for imparting n-type to silicon carbide.

  Next, a mask layer 71 is formed on the upper surface P1. Preferably, mask layer 71 is a thermal oxide film formed on upper surface P <b> 1 of epitaxial substrate 10. Next, a photoresist layer 72 having a pattern is formed on the mask layer 71. This pattern is transferred to the mask layer 71 by etching using the photoresist layer 72 (FIG. 6).

  As shown in FIG. 7, thermal etching using the mask layer 71 is performed on the upper surface P1. Specifically, by heating the epitaxial substrate 10 while bringing a gas containing a halogen element into contact with a part of the upper surface P1 of the epitaxial substrate 10, a part of the upper surface P1 of the epitaxial substrate 10 is removed by etching. As a result, the side wall surface ST and the bottom surface BT are formed on the upper surface P1 of the epitaxial substrate 10. By using such thermal etching, a special surface is self-formed on the side wall surface ST. Details of the thermal etching will be described later. Next, the mask layer 71 is removed (FIG. 8).

  As shown in FIG. 9, a p body region 12, an n source region 13, a JTE region 14, a guard ring region 15, a field stop region 16, and a p contact region 17 are formed by ion implantation of conductive impurities. Next, an activation heat treatment for activating the impurities is performed. For example, heating is performed for 30 minutes at a temperature of about 1700 ° C. in an argon atmosphere.

  As shown in FIG. 10, the insulating film 21 is formed by thermal oxidation of the upper surface P <b> 1 of the epitaxial substrate 10. The insulating film 21 includes a portion that becomes the gate insulating film 21G and a portion that becomes the sidewall insulating film 21S. Thermal oxidation is performed, for example, by heating the epitaxial substrate 10 in air or oxygen at a temperature of about 1200 ° C. for about 30 minutes.

Next, nitrogen annealing is performed. Thereby, the nitrogen concentration is adjusted so that the maximum value of the nitrogen concentration in the region within 10 nm from the interface between the epitaxial substrate 10 and the insulating film 21 is about 1 × 10 ²¹ / cm ³ or more. For example, heating is performed for about 120 minutes at a temperature of about 1100 ° C. in an atmosphere of a nitrogen-containing gas such as nitrogen monoxide gas. After the nitrogen annealing treatment, annealing treatment may be performed in an inert gas atmosphere. For example, heating is performed for about 60 minutes at a temperature of about 1100 ° C. in an argon atmosphere. Thereby, high channel mobility can be realized with good reproducibility.

  Referring to FIG. 11, gate electrode 30 is formed on gate insulating film 21G. Next, an interlayer insulating film 29 is formed. Next, a photoresist layer 73 having a pattern is formed on the interlayer insulating film 29. Next, openings are formed in the interlayer insulating film 29 and the insulating film 21 by etching using the photoresist layer 73 as a mask. Next, the source electrode 31 is formed in the opening, and the photoresist layer 73 is removed (FIG. 12). At this time, a so-called lift-off method may be used. Further, the drain electrode 42 is formed on the back surface P2 of the epitaxial substrate 10 (FIG. 13). The source electrode 31 and the drain electrode 42 are ohmic electrodes by silicidation by heat treatment.

  Referring to FIG. 2 again, MOSFET 100 is obtained by forming another configuration.

(Thermal etching)
Thermal etching is performed by exposing an object to be etched to an etching gas at a high temperature, and has substantially no physical etching action. The thermal etching process gas contains a halogen element. More preferably, the halogen element is chlorine or fluorine. Specifically, a process gas containing at least one of Cl ₂ , BCl _3, CF ₄ , and SF ₆ can be used as the process gas, and in particular, Cl ₂ can be preferably used.

  The process gas preferably further contains oxygen gas. The process gas may contain a carrier gas. The carrier gas is, for example, nitrogen gas, argon gas or helium gas.

  The heat treatment temperature for thermal etching is preferably 700 ° C. or higher and 1200 ° C. or lower. The lower limit of this temperature is more preferably 800 ° C, and still more preferably 900 ° C. As a result, the etching rate can be set to a sufficiently practical value. Further, the upper limit of this temperature is more preferably 1100 ° C., still more preferably 1000 ° C. When the heat treatment temperature is set to 700 ° C. or higher and 1000 ° C. or lower, the etching rate of SiC is, for example, about 70 μm / hour.

(Function and effect)
According to MOSFET 100 of the present embodiment, side wall surface ST arranged at termination portion TM is inclined at 50 degrees or more and 80 degrees or less with respect to the {000-1} plane. Thereby, the surface orientation of the side wall surface ST can be made suitable for suppression of the interface state between the side wall surface ST and the side wall insulating film 21S. Thereby, in the termination | terminus part TM, the interface state density in the interface of side wall surface ST of the epitaxial substrate 10 and the side wall insulating film 21S can be made low. Therefore, generation of current due to the presence of the interface state is suppressed. Therefore, the leakage current of MOSFET 100 can be suppressed. Further, the side wall surface ST can easily have a “special surface”, and in this case, the leakage current is further suppressed. When side wall surface ST has a surface orientation {0-33-8}, {0-11-2}, {0-11-4}, and {0-11-1} when viewed macroscopically Is almost the same.

  A JTE region 14 is provided on the side wall surface ST of the upper surface P1. Thereby, the withstand voltage of the MOSFET 100 can be increased by reducing the electric field concentration.

  Further, the upper surface P1 is provided with a bottom surface BT having a smaller inclination with respect to the flat surface FT than the inclination of the side wall surface with respect to the flat surface FT. Thereby, a structure for relaxing electric field concentration can be easily provided on the bottom surface BT. Specifically, the guard ring region 15 is provided on the bottom surface BT. Thereby, the withstand voltage of the MOSFET 100 can be increased by reducing the electric field concentration.

  The side wall surface ST is formed by thermal etching. By using thermal etching, the plane orientation of the side wall surface ST can be made suitable for suppressing the interface state between the side wall surface ST and the side wall insulating film 21S. Specifically, a special surface can be formed on the side wall surface ST. Therefore, generation of current due to the presence of the interface state is suppressed. Therefore, the leakage current of MOSFET 100 can be suppressed.

(Special surface)
The side wall surface ST of the upper surface P1 preferably has a special surface. Such sidewall surface ST includes a surface S1 (first surface) having a plane orientation {0-33-8} as shown in FIG. The plane S1 preferably has a plane orientation (0-33-8). More preferably, the side wall surface ST microscopically includes a surface S1, and the side wall surface ST further microscopically includes a surface S2 (second surface) having a surface orientation {0-11-1}. Here, “microscopic” means that the dimensions are as detailed as at least a dimension of about twice the atomic spacing. As a microscopic structure observation method, for example, a TEM (Transmission Electron Microscope) can be used. The plane S2 preferably has a plane orientation (0-11-1).

  Preferably, the surface S1 and the surface S2 of the side wall surface ST constitute a composite surface SR having a plane orientation {0-11-2}. That is, the composite surface SR is configured by periodically repeating the surfaces S1 and S2. Such a periodic structure can be observed by, for example, TEM or AFM (Atomic Force Microscopy). In this case, the composite surface SR has an off angle of 62 degrees macroscopically with respect to the {000-1} plane. Here, “macroscopic” means ignoring a fine structure having a dimension on the order of atomic spacing. As such a macroscopic off-angle measurement, for example, a general method using X-ray diffraction can be used.

  Preferably, composite surface SR has a plane orientation (0-11-2). In this case, the composite surface SR has an off angle of 62 degrees macroscopically with respect to the (000-1) plane. Preferably, the direction CD in which the leakage current flows is along the direction in which the above-described periodic repetition is performed. The direction CD corresponds to a direction in which the thickness direction of the epitaxial substrate 10 (the vertical direction in FIG. 2) is projected onto the side wall surface ST.

Next, the detailed structure of the composite surface SR will be described.
In general, when a silicon carbide single crystal of polytype 4H is viewed from the (000-1) plane, as shown in FIG. 15, Si atoms (or C atoms) are atoms of A layer (solid line in the figure), B layer atoms (broken line in the figure) located below, C layer atoms (dotted line in the figure) located below, and B layer atoms (not shown) located below this It is provided repeatedly. That is, a periodic laminated structure such as ABCBABCBABCB... Is provided with four layers ABCB as one period.

  As shown in FIG. 16, in the (11-20) plane (cross section taken along line XVI-XVI in FIG. 15), atoms in each of the four layers ABCB constituting one period described above are (0-11-2). It is not arranged to be completely along the plane. In FIG. 16, the (0-11-2) plane is shown so as to pass through the position of the atoms in the B layer. You can see that it is shifted. For this reason, even if the macroscopic plane orientation of the surface of the silicon carbide single crystal, that is, the plane orientation when the atomic level structure is ignored is limited to (0-11-2), this surface is microscopic. Can take various structures.

  As shown in FIG. 17, in the composite surface SR, a surface S1 having a surface orientation (0-33-8) and a surface S2 connected to the surface S1 and having a surface orientation different from the surface orientation of the surface S1 are alternately provided. It is configured by being. The length of each of the surface S1 and the surface S2 is twice the atomic spacing of Si atoms (or C atoms). Note that the surface on which the surface S1 and the surface S2 are averaged corresponds to the (0-11-2) surface (FIG. 16).

  As shown in FIG. 18, the single crystal structure when the composite surface SR is viewed from the (01-10) plane periodically includes a structure (part of the surface S1) equivalent to a cubic crystal when viewed partially. Specifically, in the composite surface SR, a surface S1 having a surface orientation (001) in a structure equivalent to the above-described cubic crystal and a surface S2 connected to the surface S1 and having a surface orientation different from the surface orientation of the surface S1 are alternated. It is comprised by being provided in. Thus, a plane having a plane orientation (001) in the structure equivalent to a cubic crystal (plane S1 in FIG. 18) and a plane connected to this plane and having a plane orientation different from this plane orientation (plane in FIG. 18). It is also possible for polytypes other than 4H to constitute the surface according to S2). The polytype may be 6H or 15R, for example.

  As shown in FIG. 19, the side wall surface ST may further include a surface S3 (third surface) in addition to the composite surface SR. More specifically, the side wall surface ST may include a composite surface SQ configured by periodically repeating the surface S3 and the composite surface SR. The periodic structure can be observed, for example, by TEM or AFM. In this case, the off angle of the side wall surface ST with respect to the {000-1} plane deviates from 62 degrees that is the ideal off angle of the composite surface SR. This deviation is preferably small, and preferably within a range of ± 10 degrees. As a surface included in such an angle range, for example, there is a surface whose macroscopic plane orientation is a {0-33-8} plane.

  More preferably, the off angle of the side wall surface ST with respect to the (000-1) plane deviates from 62 degrees that is the ideal off angle of the composite surface SR. This deviation is preferably small, and preferably within a range of ± 10 degrees. As a surface included in such an angle range, for example, there is a surface whose macroscopic plane orientation is a (0-33-8) plane.

(Appendix)
The gate insulating film and the sidewall insulating film may be formed separately rather than simultaneously. The channel type of the silicon carbide semiconductor device may be a p-channel type. In this case, a configuration in which the p-type and the n-type are replaced in the above-described embodiment can be used. The silicon carbide semiconductor device may be a MISFET (Metal Insulator Semiconductor Field Effect Transistor) other than the MOSFET, or may be other than the MISFET. As a silicon carbide semiconductor device other than the MISFET, there is, for example, an IGBT (Insulated Gate Bipolar Transistor).

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the claims of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  10 epitaxial substrate (silicon carbide substrate), 11 n drift region (first impurity region), 12 p body region (second impurity region), 13 n source region (third impurity region), 14 JTE region (side wall) Impurity region), 15 guard ring region, 16 field stop region, 17 p contact region, 19 single crystal substrate, 21 insulating film, 21G gate insulating film, 21S side wall insulating film, 29 interlayer insulating film, 30 gate electrode, 31 source electrode (First main electrode), 42 drain electrode (second main electrode), 50 gate runner, 51 wiring layer, 59 gate pad, 71 mask layer, 72, 73 photoresist layer, 100 MOSFET (silicon carbide semiconductor device) , BT bottom surface, CL element portion, FT flat surface, P1 top surface (first main surface), P2 back surface (first Of the main surface), S1 surface (first surface), S2 surface (second surface), SQ, SR complex surface, ST side wall surface, TM termination.

Claims (5)

A silicon carbide semiconductor device having an element portion in which a semiconductor element is provided and a terminal portion surrounding the element portion,
A silicon carbide substrate made of silicon carbide having a hexagonal single crystal structure, the silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface; The first main surface is inclined with respect to the flat surface so as to be close to the flat surface located in the element portion and the terminal portion, and surround the flat surface and approach the second main surface. The silicon carbide substrate includes a first impurity region having a first conductivity type, and a second impurity region having a second conductivity type provided on the first impurity region. And a third impurity region provided on the second impurity region and separated from the first impurity region by the second impurity region, and each of the first to third impurity regions includes: A portion located on the flat surface, and further on the flat surface of the first main surface. A gate insulating film connecting the first and third impurity regions to each other;
A gate electrode provided on the gate insulating film;
A first main electrode in contact with the third impurity region on the flat surface of the first main surface;
A second main electrode provided on the second main surface;
A sidewall insulating film that covers the sidewall surface of the first main surface, and the sidewall surface is inclined by 50 degrees or more and 80 degrees or less with respect to the {000-1} plane,
The side wall surface of the first main surface of the silicon carbide substrate includes a first surface having a plane orientation {0-33-8},
The side wall surface of the first main surface of the silicon carbide substrate microscopically includes the first surface, and the side wall surface further includes a second surface having a plane orientation {0-11-1}. A silicon carbide semiconductor device microscopically included.   The said 1st and 2nd surface of the said side wall surface of the said 1st main surface of the said silicon carbide substrate comprises the compound surface which has a surface orientation {0-11-2}. Silicon carbide semiconductor device. The sidewall impurity region having the second conductivity type and connected to the second impurity region is provided on the sidewall surface of the first main surface of the silicon carbide substrate. the silicon carbide semiconductor device according to 1 or claim 2. The first main surface of the silicon carbide substrate has a bottom surface that surrounds the side wall surface at the terminal portion, and the bottom surface is in relation to the flat surface as compared to an inclination of the side wall surface with respect to the flat surface. The silicon carbide semiconductor device according to any one of claims 1 to 3 , wherein the silicon carbide semiconductor device has a smaller inclination. On the bottom surface of the first main surface of the silicon carbide substrate, having said second conductivity type, spaced from said side wall, a guard ring region surrounding the side wall is provided, according to claim 4 The silicon carbide semiconductor device described in 1.

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