JP6439606B2 - Silicon carbide semiconductor device - Google Patents

Description

  The present invention relates to a silicon carbide semiconductor device.

  2. Description of the Related Art In recent years, silicon carbide has been increasingly used as a material for semiconductor devices in order to enable higher breakdown voltages, lower losses, and use in high-temperature environments for semiconductor devices such as MOSFETs (Metal Oxide Field Effect Transistors). It is being For example, Japanese Unexamined Patent Application Publication No. 2014-041990 (Patent Document 1) discloses a trench MOSFET in which an electric field relaxation region is provided inside a drift layer.

JP 2014-041990 A

  By providing the electric field relaxation region in the vicinity of the trench, the electric field applied to the corner of the trench can be relaxed by the depletion layer extending from the electric field relaxation region. However, when the voltage applied between the source electrode and the drain electrode increases, the electric field strength in the electric field relaxation region increases. In particular, since the electric field tends to concentrate at the corner of the electric field relaxation region on the drain electrode side, the electric field strength at the corner tends to increase. When the electric field strength at the corner exceeds the limit value, an avalanche breakdown may occur due to electrons accelerated by a high electric field in a depletion layer formed near the corner. As a result, the source electrode and the drain electrode are short-circuited. Avalanche breakdown is a reversible phenomenon, but the device may be destroyed by overcurrent.

  An object of one embodiment of the present invention is to provide a silicon carbide semiconductor device that can alleviate electric field concentration at a corner of a trench and suppress the occurrence of avalanche breakdown.

  A silicon carbide semiconductor device according to one embodiment of the present invention includes a silicon carbide substrate and a gate insulating film. The silicon carbide substrate has a first main surface and a second main surface opposite to the first main surface. The silicon carbide substrate includes a first impurity region having a first conductivity type, a second impurity region provided on the first impurity region and having a second conductivity type different from the first conductivity type, and separated from the first impurity region. A third impurity region which is provided on the second impurity region and forms the first main surface and has the first conductivity type, and an electric field which is located in the first impurity region and has the second conductivity type. Including relaxation regions. A trench defined by a side portion penetrating through the second impurity region and the third impurity region and reaching the first impurity region and a bottom portion provided continuously with the side portion is formed in the first main surface. ing. The gate insulating film is in contact with the first impurity region at the bottom and is in contact with the first impurity region, the second impurity region, and the third impurity region at the side. The electric field relaxation region has a third main surface that faces the first main surface and a fourth main surface that faces the second main surface. The width of the third main surface in the direction parallel to the second main surface is larger than the width of the fourth main surface.

  According to one embodiment of the present invention, it is possible to provide a silicon carbide semiconductor device that can reduce an electric field concentration at a corner portion of a trench while suppressing an increase in on-resistance and can suppress occurrence of an avalanche breakdown.

It is a cross-sectional schematic diagram which shows the structure of the silicon carbide semiconductor device which concerns on embodiment. It is an enlarged view of the area | region II of FIG. 1 is a schematic perspective view showing a configuration of a silicon carbide substrate included in a silicon carbide semiconductor device according to an embodiment. 1 is a schematic plan view showing a configuration of a silicon carbide substrate included in a silicon carbide semiconductor device according to an embodiment. It is a figure which shows distribution of the dose amount in an electric field relaxation area | region. It is a cross-sectional schematic diagram which shows the structure of the 1st modification of the silicon carbide semiconductor device which concerns on embodiment. It is a cross-sectional schematic diagram which shows the structure of the 2nd modification of the silicon carbide semiconductor device which concerns on embodiment. It is a cross-sectional schematic diagram which shows the structure of the 3rd modification of the silicon carbide semiconductor device which concerns on embodiment. It is a cross-sectional schematic diagram which shows the structure of the 4th modification of the silicon carbide semiconductor device which concerns on embodiment. It is a cross-sectional schematic diagram which shows the structure of the 5th modification of the silicon carbide semiconductor device which concerns on embodiment. It is a fragmentary sectional view showing roughly the fine structure of the surface of a silicon carbide layer which a silicon carbide semiconductor device has. It is a figure which shows the crystal structure of the (000-1) plane in the hexagonal crystal of polytype 4H. It is a figure which shows the crystal structure of the (11-20) plane which follows the line XIII-XIII of FIG. It is a figure which shows the crystal structure in the surface vicinity of the composite surface of FIG. 10 in (11-20) plane. It is the figure which looked at the compound surface of Drawing 10 from the (01-10) plane. An example of the relationship between the angle between the channel plane and the (000-1) plane viewed macroscopically and the channel mobility is a graph showing each of a case where thermal etching is performed and a case where thermal etching is not performed. is there. It is a graph which shows an example of the relationship between the angle between a channel direction and the <0-11-2> direction, and channel mobility. It is a figure which shows the modification of FIG. It is a cross-sectional schematic diagram which shows the 1st process of the manufacturing method of the silicon carbide semiconductor device which concerns on embodiment. It is a cross-sectional schematic diagram which shows the 2nd process of the manufacturing method of the silicon carbide semiconductor device which concerns on embodiment. It is a cross-sectional schematic diagram which shows the 3rd process of the manufacturing method of the silicon carbide semiconductor device which concerns on embodiment. It is a cross-sectional schematic diagram which shows the 4th process of the manufacturing method of the silicon carbide semiconductor device which concerns on embodiment. And the on-resistance of the silicon carbide semiconductor _device, the experimental data showing the relationship between W _{b -W u} -W _dep. And the breakdown voltage of the silicon carbide semiconductor _device, the experimental data showing the relationship between W _{b -W u} -W _dep.

[Description of Embodiment of Present Invention]
(1) Silicon carbide semiconductor device 1 according to one aspect of the present invention includes a silicon carbide substrate 10 and a gate insulating film 15. Silicon carbide substrate 10 has a first main surface 10a and a second main surface 10b opposite to the first main surface 10a. Silicon carbide substrate 10 includes a first impurity region 12 having a first conductivity type, a second impurity region 13 provided on first impurity region 12 and having a second conductivity type different from the first conductivity type, A third impurity region 14 provided on the second impurity region 13 so as to be separated from the impurity region 12 and constituting the first main surface 10a and having the first conductivity type is located in the first impurity region 12. And the electric field relaxation region 2 having the second conductivity type. The first main surface 10a includes a side SW that penetrates through the second impurity region 13 and the third impurity region 14 and reaches the first impurity region 12, and a bottom BT provided continuously with the side SW. A defined trench TR is formed. Gate insulating film 15 is in contact with first impurity region 12 at bottom portion BT, and is in contact with first impurity region 12, second impurity region 13, and third impurity region 14 at side portion SW. The electric field relaxation region 2 has a third main surface 2a1 that faces the first main surface 10a and a fourth main surface 2b1 that faces the second main surface 10b. The width W1 of the third main surface 2a1 in the direction parallel to the second main surface 10b is larger than the width W2 of the fourth main surface 2b1.

  According to silicon carbide semiconductor device 1 according to (1) above, width W1 of third main surface 2a1 is larger than width W2 of fourth main surface 2b1. Thereby, the electric field strength in the edge part C3 of the 4th main surface 2b1 of the electric field relaxation area | region 2 can be reduced. Therefore, the occurrence of avalanche breakdown can be suppressed. Further, since the width W1 of the third main surface 2a1 of the electric field relaxation region 2 is large, the third main surface 2a1 can be disposed near the corner C1 of the trench TR. Therefore, the electric field concentration at the corner C1 of the trench TR can be reduced.

  (2) In silicon carbide semiconductor device 1 according to (1) above, outer edge 13p of second impurity region 13 is provided so as to surround electric field relaxation region 2 when viewed from the direction perpendicular to second main surface 10b. It may be done. As a result, the current path flowing through the drift region 12 can be prevented from being narrowed. As a result, the on-resistance of silicon carbide semiconductor device 1 can be reduced.

  (3) In silicon carbide semiconductor device 1 according to (1) or (2) above, silicon carbide substrate 10 is located between second impurity region 13 and electric field relaxation region 2 and has the second conductivity type. The fourth impurity region 3 may be included. Thereby, the second impurity region 13 and the electric field relaxation region 2 can be electrically connected, and the switching speed can be increased.

  (4) In silicon carbide semiconductor device 1 according to (3) above, fourth impurity region 3 may be in contact with both second impurity region 13 and electric field relaxation region 2. Thereby, electrons or holes can be easily supplied from the second impurity region 13 to the electric field relaxation region 2.

(5) In silicon carbide semiconductor device 1 according to any one of (1) to (4), second impurity region 13 has fifth main surface 13a that is a boundary surface with first impurity region 12, Half of the width of the fifth main surface 13a in the direction parallel to the second main surface 10b is W _b (μm), and half of the width of the third main surface 2a1 in the direction parallel to the second main surface 10b is W _u (μm), the impurity concentration in the first impurity region 12 is N _d (cm ⁻³ ), the impurity concentration in the electric field relaxation region 2 is N _a (cm ⁻³ ), and the vacuum dielectric constant is ε ₀ (F M ^-1 ), the dielectric constant of silicon carbide is ε _SiC (F · m ^-1 ), the elementary charge is e (C), and the diffusion potential is V _bi (V). Also good. Thereby, on-resistance can be reduced while maintaining the breakdown voltage of silicon carbide semiconductor device 1 high.

(6) In silicon carbide semiconductor device 1 according to any of (1) to (5) above, silicon carbide substrate 10 includes silicon carbide single crystal substrate 11 constituting second main surface 10b, and silicon carbide single crystal substrate. 11 and silicon carbide epitaxial layer 24 constituting first main surface 10a. The impurity dose amount of electric field relaxation region 2 is set to D _rx (cm ⁻² ), and fourth main surface 2b1, silicon carbide single crystal substrate 11 and silicon carbide epitaxial layer 24 in the direction perpendicular to second main surface 10b. When the distance to the boundary surface 11a is L _d (cm) and the impurity concentration in the first impurity region 12 is N _d (cm ⁻³ ), Expression 2 may be satisfied. Thereby, it is suppressed that the electric field relaxation region 2 is completely depleted before the depletion layer extends from the electric field relaxation region 2 to the boundary surface 11a. Thereby, a depletion layer having a sufficient length can be formed between the electric field relaxation region 2 and the boundary surface 11a. As a result, the breakdown voltage of silicon carbide semiconductor device 1 can be maintained high.

  (7) In silicon carbide semiconductor device 1 according to any of (1) to (6) above, angle θ formed by side portion SW and bottom portion BT may be greater than 90 °. When the angle θ formed by the side portion SW and the bottom portion BT is 90 °, the on-resistance when the electric field relaxation region 2 is located immediately below the side portion SW, and the electric field relaxation region 2 is more first than immediately below the side portion SW. The on-resistance when shifted slightly in the direction parallel to the main surface 10a is greatly different. On the other hand, when the angle θ formed by the side part SW and the bottom part BT is larger than 90 °, even if the position of the electric field relaxation region 2 with respect to the side part SW is slightly changed, the on-resistance is not greatly different. Therefore, when the angle θ formed by the side portion SW and the bottom portion BT is larger than 90 °, even when the position of the electric field relaxation region 2 with respect to the trench TR varies in the plane of the wafer due to, for example, an alignment error, A large change in on-resistance can be suppressed.

  (8) In silicon carbide semiconductor device 1 according to any one of (1) to (7), side SW may include first surface S1 having a plane orientation {0-33-8}. Thereby, the channel resistance in the side part SW can be reduced.

  (9) In silicon carbide semiconductor device 1 according to (8) above, side portion SW microscopically includes first surface S1, and side portion SW further has a plane orientation {0-11-1}. The second surface S2 may be included microscopically. Thereby, the channel resistance in the side part SW can be further reduced.

  (10) In silicon carbide semiconductor device 1 according to (9) above, first surface S1 and second surface S2 may constitute composite surface SR having a plane orientation {0-11-2}. Thereby, the channel resistance in the side part SW can be further reduced.

  (11) In silicon carbide semiconductor device 1 according to (10) above, side SW may macroscopically have an off angle of 62 ° ± 10 ° with respect to the {000-1} plane. Thereby, the channel resistance in the side part SW can be further reduced.

[Details of the embodiment of the present invention]
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated. In the crystallographic description in this specification, the individual orientation is indicated by [], the collective orientation is indicated by <>, the individual plane is indicated by (), and the collective plane is indicated by {}. In addition, a negative crystallographic index is usually expressed by adding a “-” (bar) above a number, but in this specification a negative sign is added before the number. Yes.

  First, the structure of MOSFET as a silicon carbide semiconductor device according to an embodiment of the present invention will be described.

  As shown in FIGS. 1 and 2, MOSFET 1 according to the present embodiment includes silicon carbide substrate 10, gate insulating film 15, gate electrode 27, interlayer insulating film 22, source electrode 16, and source wiring. 19 and the drain electrode 20 are mainly included. Silicon carbide substrate 10 includes a silicon carbide single crystal substrate 11 and a silicon carbide epitaxial layer 24 provided on silicon carbide single crystal substrate 11. Silicon carbide substrate 10 has a first main surface 10a and a second main surface 10b opposite to the first main surface 10a. Silicon carbide epitaxial layer 24 constitutes first main surface 10a, and silicon carbide single crystal substrate 11 constitutes second main surface 10b.

  The first major surface 10a is, for example, a surface that is off by 2 ° or more and 8 ° or less from the {000-1} surface or the {000-1} surface. Preferably, the first main surface 10a is on the carbon surface side, and the second main surface 10b is on the silicon surface side. The first major surface 10a is, for example, a surface that is off by 2 ° or more and 8 ° or less from the (000-1) surface or the (000-1) surface. Silicon carbide single crystal substrate 11 is, for example, polytype 4H hexagonal silicon carbide. Silicon carbide single crystal substrate 11 includes an n-type impurity such as nitrogen and has an n-type (first conductivity type) conductivity type. Silicon carbide epitaxial layer 24 includes drift region 12 (first impurity region 12), body region 13 (second impurity region 13), source region 14 (third impurity region 14), contact region 18 and electric field relaxation region. 2 mainly.

Drift region 12 includes an n-type impurity such as nitrogen and has n-type conductivity. The concentration of the n-type impurity contained in the drift region 12 is preferably 1 × 10 ¹⁵ cm ⁻³ or more and 5 × 10 ¹⁶ cm ⁻³ or less, for example, 8 × 10 ¹⁵ cm ⁻³ . The concentration of n-type impurities contained in drift region 12 may be lower than the concentration of n-type impurities contained in silicon carbide single crystal substrate 11.

Body region 13 is provided on drift region 12. Body region 13 includes a p-type impurity such as aluminum and has a p-type (second conductivity type) conductivity type. The concentration of the p-type impurity in the body region 13 is preferably 1 × 10 ¹⁷ cm ⁻³ or more and 5 × 10 ¹⁸ cm ⁻³ or less, for example, 1 × 10 ¹⁸ cm ⁻³ .

  Source region 14 is provided on body region 13 so as to be separated from drift region 12 by body region 13. Source region 14 includes an n-type impurity such as nitrogen or phosphorus and has an n-type conductivity type. Source region 14 constitutes first main surface 10a of silicon carbide substrate 10. The concentration of the n-type impurity included in the source region 14 may be higher than the concentration of the n-type impurity included in the drift region 12.

  Contact region 18 is in contact with body region 13 and source region 14. Contact region 18 contains a p-type impurity such as aluminum and has p-type conductivity. The concentration of the p-type impurity included in the contact region 18 may be higher than the concentration of the p-type impurity included in the body region 13. Contact region 18 is provided through source region 14 so as to connect body region 13 and first major surface 10a.

  As shown in FIGS. 1 and 2, the electric field relaxation region 2 is located in the drift region 12. Electric field relaxation region 2 includes a p-type impurity such as aluminum and has p-type conductivity. The electric field relaxation region 2 has a third main surface 2a1 that faces the first main surface 10a and a fourth main surface 2b1 that faces the second main surface 10b. The width W1 of the third main surface 2a1 in the direction parallel to the second main surface 10b is larger than the width W2 of the fourth main surface 2b1. The width of the electric field relaxation region 2 may decrease monotonously or may decrease stepwise in the direction from the third main surface 2a1 to the fourth main surface 2b1. Preferably, when viewed from a direction perpendicular to the second main surface 10b, the outer edge of the third main surface 2a1 surrounds the outer edge of the fourth main surface 2b1. Electric field relaxation region 2 may be separated from body region 13 by drift region 12. Electric field relaxation region 2 may be separated from silicon carbide single crystal substrate 11 by drift region 12. Preferably, the third main surface 2a1 is located between the bottom portion BT and the second main surface 10b in the direction perpendicular to the second main surface 10b.

  Trench TR is formed in first main surface 10a of silicon carbide substrate 10. Trench TR is defined by side SW and bottom BT. Side SW passes through body region 13 and source region 14 and reaches drift region 12. The bottom part BT is provided continuously with the side part SW. The bottom portion BT is located in the drift region 12. Preferably, the angle θ formed by the side part SW and the bottom part BT is greater than 90 °.

  Side view SW may be inclined so that the width of trench TR narrows in a tapered shape toward bottom portion BT in a cross-sectional view (a visual field viewed from a direction parallel to second main surface 10b of silicon carbide substrate 10). . The side SW is preferably inclined at 52 ° or more and 72 ° or less with respect to the (000-1) plane. Note that the side portion SW may be formed perpendicular to the first main surface 10a. The bottom portion BT may have a flat shape substantially parallel to the first main surface 10a. In cross-sectional view, the shape of the trench TR may be U-shaped or V-shaped. Preferably, the side part SW includes a special surface. Details of the configuration of the special surface will be described later.

  FIG. 3 shows silicon carbide substrate 10 taken out from MOSFET 1 shown in FIG. As shown in FIG. 3, source region 14, body region 13 and drift region 12 are exposed at side SW of trench TR. Drift region 12 is exposed at each of side SW and bottom BT of trench TR. A portion where bottom portion BT and side portion SW are connected constitutes corner portion C1 (see FIG. 2) of trench TR. Trench TR may extend so as to form a mesh having a honeycomb structure in a plan view (a visual field viewed from a direction perpendicular to second main surface 10b of silicon carbide substrate 10).

  As shown in FIGS. 3 and 4, first planar surface 10a of silicon carbide substrate 10 formed of source region 14 and contact region 18 has a hexagonal shape in plan view. Preferably, in plan view, body region 13, source region 14, contact region 18, and electric field relaxation region 2 have a hexagonal outer shape. Preferably, the unit cell has a hexagonal shape, more preferably a regular hexagonal shape. The shape of the unit cell may be a polygon such as a quadrangle. The shape of the body region 13, the source region 14, the contact region 18 and the electric field relaxation region 2 in plan view is preferably the same as the shape of the unit cell.

  As shown in FIG. 4, the outer edge 13 p of the body region 13 may be provided so as to surround the electric field relaxation region 2 in plan view. In plan view, the outer edge 14p at the boundary between the body region 13 and the source region 14 may be provided so as to surround the electric field relaxation region 2.

Preferably, the dose amount of the p-type impurity in the electric field relaxation region 2 is D _rx (cm ⁻² ), and the fourth main surface 2b1 and the silicon carbide single crystal substrate 11 in a direction perpendicular to the second main surface 10b. When the distance from the boundary surface 11a of the silicon carbide epitaxial layer 24 is L _d (cm) and the concentration of the n-type impurity in the drift region 12 is N _d (cm ⁻³ ), Equation 2 is satisfied. As shown in FIG. 5, the dose amount in the electric field relaxation region 2 in the direction parallel to the second main surface 10 b (X direction in FIG. 2) has a maximum value D _O at the position facing the contact region 18. However, it may be decreased toward the trenches TR on both sides. In this case, the dose amount D _rx (cm ⁻² ) in Formula 2 is the maximum value of the dose amount.

Next, the calculation direction of the width of the depletion layer formed around the electric field relaxation region 2 will be described.
First, the intrinsic carrier concentration n _i (cm ⁻³ ) is calculated by the following mathematical formula 3. Here, _{N c} is the electron density in the conduction band of the 4H-SiC at room temperature, _{N v} is the hole density of the valence band of the 4H-SiC at room temperature. E _g is the band gap of 4H—SiC at room temperature. E _g is about 3.25 eV. k _B is the Boltzmann constant and T is the absolute temperature (K). The room temperature is 300K.

Next, the diffusion potential V _bi (V) is calculated by Equation 4 below. Here, N _a is the acceptor concentration of the electric field relaxation region. N _d is the donor concentration in the drift region. n _i is the intrinsic carrier concentration (cm ⁻³ ) calculated by Equation 3 above. k _B is the Boltzmann constant and T is the absolute temperature (K).

Next, the width W _{dep of the} depletion layer DE is calculated by the following Equation 5. Here, the donor concentration in the drift region 12 is N _d (cm ⁻³ ). The acceptor concentration in the electric field relaxation region 2 is N _a (cm ⁻³ ). The dielectric constant of the vacuum is ε ₀ (F · m ⁻¹ ). The dielectric constant of silicon carbide is ε _SiC (F · m ⁻¹ ). e is an elementary charge (C). V _bi is the diffusion potential (V). In the following formula 5, it is assumed that the voltage at the pn interface between the electric field relaxation region 2 and the drift region 12 in the direction parallel to the second main surface 10b is 0V.

A boundary surface between body region 13 and drift region 12 is fifth main surface 13a. Half of the width of the fifth main surface 13a in the direction parallel to the second main surface 10b is W _b (μm), and half of the width of the third main surface 2a1 in the direction parallel to the second main surface 10b is W _{In the case of u} (μm), it is preferable that W _b (μm)> W _u (μm) + W _dep (μm) is satisfied. That is, in plan view, the fifth main surface 13a of the body region 13 includes a region in which the third main surface 2a1 of the electric field relaxation region 2 and the depletion layer DE protruding from the electric field relaxation region 2 to the drift region 12 are included. It is preferable. More preferably, W _b −W _u −W _dep is greater than 0 and less than 0.5 μm.

  Referring to FIG. 2, distance H4 between boundary surface 11a and third main surface 2a1 in the direction perpendicular to second main surface 10b is, for example, 9 μm. A distance H3 between the fifth main surface 13a and the third main surface 2a1 in the direction perpendicular to the second main surface 10b is, for example, 1 μm. The depth H5 of the trench TR is, for example, 1.4 μm. When the trench TR is shallow and the bottom portion BT of the trench TR is located in the depletion layer extending from the body region 13 toward the drift region 12, the on-resistance increases. on the other hand. When the trench TR is too deep or the distance H3 is too small, the electric field concentrates on the corner C1 of the trench TR, and the breakdown voltage decreases. From the standpoint of both reducing the on-resistance and improving the breakdown voltage, the distance between the bottom BT of the trench TR and the fifth main surface 13a in the direction perpendicular to the second main surface 10b is greater than 0.2 μm and the distance It is preferable that H3 is larger than 0.7 μm.

  As shown in FIG. 2, the electric field relaxation region 2 may include a first electric field relaxation region portion 2a and a second electric field relaxation region portion 2b in contact with the first electric field relaxation region portion 2a. Second electric field relaxation region portion 2b is located between first electric field relaxation region portion 2a and second main surface 10b. Preferably, the outer edge of the first electric field relaxation region 2a surrounds the outer edge of the second electric field relaxation region 2b when viewed from a direction perpendicular to the second main surface 10b. The first electric field relaxation region portion 2a has a corner portion C2 on the drain electrode 20 side. The second electric field relaxation region portion 2b has a corner portion C3 on the drain electrode 20 side. Therefore, the electric field in the electric field relaxation region 2 is distributed to the corner portion C2 and the corner portion C3. As a result, occurrence of avalanche breakdown can be suppressed.

The thickness H1 of the first electric field relaxation region portion 2a is, for example, not less than 0.5 μm and not more than 1.0 μm. A thickness H2 of second electric field relaxation region portion 2b is, for example, not less than 0.1 μm and not more than 1.0 μm. The concentration of the p-type impurity included in the first electric field relaxation region portion 2a is, for example, 1 × 10 ¹⁷ cm ⁻³ or more and 1 × 10 ¹⁹ cm ⁻³ or less. The concentration of the p-type impurity included in the second electric field relaxation region portion 2b is, for example, 1 × 10 ¹⁷ cm ⁻³ or more and 1 × 10 ¹⁹ cm ⁻³ or less. The concentration of the p-type impurity included in the first electric field relaxation region portion 2a may be the same as or different from the concentration of the p-type impurity included in the second electric field relaxation region portion 2b.

  As shown in FIGS. 1 and 2, gate insulating film 15 is in contact with bottom portion BT and side portion SW of trench TR and part of first main surface 10a. Gate insulating film 15 is made of, for example, a material containing silicon dioxide. The gate insulating film 15 is a thermal oxide film, for example. Gate insulating film 15 is in contact with drift region 12 at bottom BT, and is in contact with drift region 12, body region 13, and source region 14 at side SW.

  Gate electrode 27 is provided inside trench TR so as to be in contact with gate insulating film 15 inside trench TR. The gate electrode 27 is made of polysilicon containing impurities, for example. The gate electrode 27 is provided so as to face the source region 14, the body region 13, and the drift region 12.

  Source electrode 16 is in contact with each of source region 14 and contact region 18 on first main surface 10a. The source electrode 16 is made of a material containing, for example, Ti, Al, and Si. Preferably, source electrode 16 is in ohmic contact with source region 14 and contact region 18. The source wiring 19 is in contact with the source electrode 16. Source wiring 19 is made of, for example, a material containing aluminum.

  The interlayer insulating film 22 is provided in contact with the gate electrode 27 and the gate insulating film 15. Interlayer insulating film 22 is made of, for example, a material containing silicon dioxide. The interlayer insulating film 22 electrically insulates the gate electrode 27 and the source electrode 16 from each other. Drain electrode 20 is in contact with silicon carbide single crystal substrate 11 on second main surface 10 b and is electrically connected to drift region 12. The drain electrode 20 is made of a material containing, for example, NiSi or TiAlSi.

Next, the structure of the 1st modification of an electric field relaxation area | region is demonstrated.
As shown in FIG. 6, the electric field relaxation region 2 may include a first electric field relaxation region portion 2a, a second electric field relaxation region portion 2b, and a third electric field relaxation region portion 2c. The second electric field relaxation region portion 2b is located closer to the second main surface 10b than the first electric field relaxation region portion 2a. The third electric field relaxation region 2c is located closer to the second main surface 10b than the second electric field relaxation region 2b. In the direction parallel to the second major surface 10b, the width of the second electric field relaxation region 2b is smaller than the width of the first electric field relaxation region 2a. In the direction parallel to the second major surface 10b, the width of the third electric field relaxation region portion 2c is smaller than the width of the second electric field relaxation region portion 2b.

  The first electric field relaxation region 2a may be in contact with the second electric field relaxation region 2b, or may be separated from the second electric field relaxation region 2b by the drift region 12. Second electric field relaxation region 2b may be in contact with third electric field relaxation region 2c, or may be separated from third electric field relaxation region 2c by drift region 12. The first electric field relaxation region portion 2a, the second electric field relaxation region portion 2b, and the third electric field relaxation region portion 2c may be configured by ion implantation separately. The first electric field relaxation region 2a, the second electric field relaxation region 2b, and the third electric field relaxation region 2c may be connected to each other to constitute one electric field relaxation region 2 as a whole.

Next, the structure of the 2nd modification of an electric field relaxation area | region is demonstrated.
As shown in FIG. 7, silicon carbide substrate 10 may include a fourth impurity region 3 located between body region 13 and electric field relaxation region 2. Fourth impurity region 3 includes a p-type impurity such as aluminum and has p-type conductivity. The fourth impurity region 3 faces the contact region 18. The fourth impurity region 3 is provided in contact with the electric field relaxation region 2. A drift region 12 is provided between the fourth impurity region 3 and the body region 13. The width W4 of the fourth impurity region 3 in the direction parallel to the second main surface 10b may be smaller than the width W1 of the third main surface 2a1 of the electric field relaxation region 2. The width W4 of the fourth impurity region 3 may be smaller than the width W2 of the fourth main surface 2b1 of the electric field relaxation region 2.

Next, the structure of the 3rd modification of an electric field relaxation area | region is demonstrated.
As shown in FIG. 8, the fourth impurity region 3 may be separated from the body region 13 and separated from the electric field relaxation region 2. The fourth impurity region 3 may be surrounded by the drift region 12. A drift region 12 may be provided between the fourth impurity region 3 and the body region 13. A drift region 12 may be provided between the fourth impurity region 3 and the electric field relaxation region 2.

Next, the structure of the 4th modification of an electric field relaxation area | region is demonstrated.
As shown in FIG. 9, the fourth impurity region 3 may be in contact with both the body region 13 and the electric field relaxation region 2. Thereby, the electric field relaxation region 2 is electrically connected to the body region 13 through the fourth impurity region 3. The side surface of the fourth impurity region 3 may be surrounded by the drift region 12.

Next, the configuration of the fifth modification example of the electric field relaxation region will be described.
As shown in FIG. 10, the shape of the electric field relaxation region 2 may be an inverted trapezoidal shape in a cross-sectional view. The angle between the side surface 2s of the electric field relaxation region 2 and the fourth main surface 2b1 is greater than 90 °. Therefore, the electric field concentration at the corner C3 of the electric field relaxation region 2 can be relaxed. An angle ψ between the side surface 2s of the electric field relaxation region 2 and the third main surface 2a1 is, for example, not less than 20 ° and not more than 50 °. Thereby, since the width of drift region 12 sandwiched between electric field relaxation regions 2 increases from first main surface 10a to second main surface 10b, the on-resistance of silicon carbide semiconductor device 1 can be reduced.

Next, the configuration of the special surface will be described.
The side portion SW described above has a special surface, particularly in a portion on the body region 13. As shown in FIG. 11, the side portion SW having the special surface includes a surface S1 (first surface) having a surface orientation {0-33-8}. In other words, the surface including the surface S1 is provided in the body region 13 on the side portion SW of the trench TR. The plane S1 preferably has a plane orientation (0-33-8).

  More preferably, the side portion SW microscopically includes a surface S1, and the side portion SW further microscopically includes a surface S2 (second surface) having a surface orientation {0-11-1}. Here, “microscopic” means that the dimensions are as detailed as at least a dimension of about twice the atomic spacing. As a microscopic structure observation method, for example, TEM can be used. The plane S2 preferably has a plane orientation (0-11-1).

  Preferably, the surface S1 and the surface S2 of the side SW constitute a composite surface SR having a surface orientation {0-11-2}. That is, the composite surface SR is configured by periodically repeating the surfaces S1 and S2. Such a periodic structure can be observed by, for example, TEM or AFM (Atomic Force Microscopy). In this case, the composite surface SR has an off angle of 62 ° macroscopically with respect to the {000-1} plane. Here, “macroscopic” means ignoring a fine structure having a dimension on the order of atomic spacing. As such a macroscopic off-angle measurement, for example, a general method using X-ray diffraction can be used. Preferably, composite surface SR has a plane orientation (0-11-2). In this case, the composite surface SR has an off angle of 62 ° macroscopically with respect to the (000-1) plane.

  As the TEM, for example, JEM-2100F manufactured by JEOL Ltd. can be used. The sample analysis area is, for example, 10 μm × 10 μm × 0.1 μm. The acceleration voltage is 200 kV, for example. As the AFM, for example, Dimension Icon SPM System manufactured by Nippon Bico Co., Ltd. can be used. The sample analysis area is, for example, 90 μm × 90 μm. The scan rate is, for example, 0.2 Hz. The chip speed is, for example, 8 μm / second. The amplitude set point is 15.5 nm, for example. The Z range is, for example, 1 μm. The above parameters are adjusted according to the sample. As the X-ray diffractometer, for example, SmartLab manufactured by Rigaku Corporation can be used. The sample analysis region is, for example, not less than 0.3 mmφ and not more than 0.8 mmφ. The tube used is, for example, Cu. The output is, for example, 45 kV and 80 mA. For example, after confirming that the first major surface 10a is the (000-1) plane with an X-ray diffractometer, the side SW of the trench TR is measured by AFM.

  Preferably, the channel direction CD, which is the direction in which carriers flow on the channel surface, is along the direction in which the above-described periodic repetition is performed.

Next, the detailed structure of the composite surface SR will be described.
Generally, when a silicon carbide single crystal of polytype 4H is viewed from the (000-1) plane, as shown in FIG. 12, Si atoms (or C atoms) are atoms of the A layer (solid line in the figure), B layer atoms (broken line in the figure) located below, C layer atoms (dotted line in the figure) located below, and B layer atoms (not shown) located below this It is provided repeatedly. That is, a periodic laminated structure such as ABCBABCBABCB... Is provided with four layers ABCB as one period.

  As shown in FIG. 13, in the (11-20) plane (cross section taken along line XIII-XIII in FIG. 12), atoms in each of the four layers ABCB constituting one cycle described above are (0-11-2). It is not arranged to be completely along the plane. In FIG. 13, the (0-11-2) plane is shown so as to pass through the position of atoms in the B layer. You can see that it is shifted. For this reason, even if the macroscopic plane orientation of the surface of the silicon carbide single crystal, that is, the plane orientation when the atomic level structure is ignored is limited to (0-11-2), this surface is microscopic. Can take various structures.

  As shown in FIG. 14, the composite surface SR is alternately provided with a surface S1 having a surface orientation (0-33-8) and a surface S2 connected to the surface S1 and having a surface orientation different from the surface orientation of the surface S1. It is configured by being. The length of each of the surface S1 and the surface S2 is twice the atomic spacing of Si atoms (or C atoms). Note that the surface on which the surface S1 and the surface S2 are averaged corresponds to the (0-11-2) surface (FIG. 13).

  As shown in FIG. 15, the single crystal structure when the composite surface SR is viewed from the (01-10) plane periodically includes a structure (part of the surface S1) equivalent to a cubic crystal when viewed partially. Specifically, in the composite surface SR, a surface S1 having a surface orientation (001) in a structure equivalent to the above-described cubic crystal and a surface S2 connected to the surface S1 and having a surface orientation different from the surface orientation of the surface S1 are alternated. It is comprised by being provided in. Thus, a plane having a plane orientation (001) in the structure equivalent to a cubic crystal (plane S1 in FIG. 11) and a plane connected to this plane and having a plane orientation different from this plane orientation (plane in FIG. 11). It is also possible for polytypes other than 4H to constitute the surface according to S2). The polytype may be 6H or 15R, for example.

  Next, the relationship between the crystal plane of the side SW and the mobility MB of the channel plane will be described with reference to FIG. In the graph of FIG. 16, the horizontal axis indicates the angle D1 formed by the macroscopic plane orientation of the side SW having the channel surface and the (000-1) plane, and the vertical axis indicates the mobility MB. The plot group CM corresponds to the case where the side SW is finished as a special surface by thermal etching, and the plot group MC corresponds to the case where such thermal etching is not performed.

  The mobility MB in the plot group MC was maximized when the macroscopic plane orientation of the surface of the channel surface was (0-33-8). This is because when the thermal etching is not performed, that is, when the microscopic structure of the channel surface is not particularly controlled, the microscopic plane orientation is set to (0-33-8). This is probably because the ratio of the formation of the visual plane orientation (0-33-8), that is, the plane orientation (0-33-8) when considering even the atomic level is stochastically increased.

  On the other hand, the mobility MB in the plot group CM is maximized when the macroscopic surface orientation of the channel surface is (0-11-2) (arrow EX). The reason for this is that, as shown in FIGS. 14 and 15, a large number of surfaces S1 having a plane orientation (0-33-8) are regularly and densely arranged via the surface S2, so that the surface of the channel surface is fine. This is probably because the ratio of the visual plane orientation (0-33-8) is increased.

  The mobility MB has orientation dependency on the composite surface SR. In the graph shown in FIG. 17, the horizontal axis indicates the angle D2 between the channel direction and the <0-11-2> direction, and the vertical axis indicates the mobility MB (arbitrary unit) of the channel surface. A broken line is added to make the graph easier to see. From this graph, in order to increase the channel mobility MB, the angle D2 of the channel direction CD (FIG. 11) is preferably 0 ° or more and 60 ° or less, and more preferably approximately 0 °. all right.

  As shown in FIG. 18, the side portion SW may further include a surface S3 (third surface) in addition to the composite surface SR. More specifically, the side portion SW may include a composite surface SQ configured by periodically repeating the surface S3 and the composite surface SR. In this case, the off angle of the side SW with respect to the {000-1} plane deviates from 62 ° which is the ideal off angle of the composite surface SR. This deviation is preferably small and preferably within a range of ± 10 °. As a surface included in such an angle range, for example, there is a surface whose macroscopic plane orientation is a {0-33-8} plane. More preferably, the off angle of the side SW with respect to the (000-1) plane deviates from 62 °, which is the ideal off angle of the composite surface SR. This deviation is preferably small and preferably within a range of ± 10 °. As a surface included in such an angle range, for example, there is a surface whose macroscopic plane orientation is a (0-33-8) plane.

  Such a periodic structure can be observed, for example, by TEM or AFM. Specific examples of the measurement apparatus, the sample analysis region, and the measurement conditions are as described above.

Next, a method for manufacturing MOSFET 1 according to the present embodiment will be described.
First, a step of preparing a silicon carbide substrate is performed. As shown in FIG. 19, drift region 12 is formed on silicon carbide single crystal substrate 11. Specifically, for example, by a CVD (Chemical Vapor Deposition) method using a mixed gas of silane (SiH ₄ ) and propane (C ₃ H ₈ ) as a source gas and using, for example, hydrogen gas (H ₂ ) as a carrier gas. Drift region 12 is formed on silicon carbide single crystal substrate 11. In the epitaxial growth, it is preferable to introduce, for example, nitrogen (N) or phosphorus (P) as impurities. Drift region 12 has n-type conductivity.

  Next, a p-type impurity such as aluminum is ion-implanted into drift region 12 to form electric field relaxation region 2. For example, after the first electric field relaxation region portion 2a is formed, the second electric field relaxation region portion 2b is formed at a position deeper than the first electric field relaxation region portion 2a. The second electric field relaxation region portion 2b is formed with ion implantation energy higher than the ion implantation energy for forming the first electric field relaxation region portion 2a, using a mask having an opening narrower than the first electric field relaxation region portion 2a. Also good.

  Next, the drift region 12 is formed on the electric field relaxation region 2 by epitaxial growth again. Next, a body region 13 is formed by ion implantation of a p-type impurity such as aluminum into the newly formed drift region 12. Next, an n-type impurity such as phosphorus is ion-implanted into body region 13 at a depth shallower than that of body region 13 to form source region 14. Next, contact region 18 is formed by ion implantation of a p-type impurity such as aluminum into source region 14. The contact region 18 is formed so as to penetrate the source region 14 and contact the body region 13 (see FIG. 20).

  Next, activation annealing is performed to activate the impurities ion-implanted into silicon carbide substrate 10. The temperature of activation annealing is preferably 1500 ° C. or higher and 1900 ° C. or lower, for example, about 1700 ° C. The activation annealing time is, for example, about 30 minutes. The atmosphere of activation annealing is preferably an inert gas atmosphere, for example, an Ar atmosphere.

Next, a step of forming a trench is performed. For example, a mask layer (not shown) having an opening at a position where trench TR (FIG. 1) is formed is formed on first main surface 10 a configured from source region 14 and contact region 18. Using the mask layer, the source region 14, the body region 13, and a part of the drift region 12 are removed by etching. As an etching method, for example, reactive ion etching, particularly inductively coupled plasma reactive ion etching can be used. Specifically, for example, inductively coupled plasma reactive ion etching using SF ₆ or a mixed gas of SF ₆ and O ₂ as a reaction gas can be used. By etching, in a region where trench TR (FIG. 1) is to be formed, a side portion substantially perpendicular to first main surface 10a and a side portion are provided continuously and substantially parallel to first main surface 10a. A recess having a bottom is formed.

Next, thermal etching is performed in the recess. The thermal etching can be performed, for example, by heating in an atmosphere containing a reactive gas having at least one or more types of halogen atoms. The at least one or more types of halogen atom includes at least one of a chlorine (Cl) atom and a fluorine (F) atom. The atmosphere includes, for example, Cl ₂ , BCL ₃ , SF ₆ , or CF ₄ . For example, thermal etching is performed using a mixed gas of chlorine gas and oxygen gas as a reaction gas and a heat treatment temperature of, for example, 700 ° C. or more and 1000 ° C. or less. Note that the reaction gas may contain a carrier gas in addition to the above-described chlorine gas and oxygen gas. As the carrier gas, for example, nitrogen (N ₂ ) gas, argon gas, helium gas or the like can be used. During the thermal etching, the mask layer is not substantially etched during the etching of SiC because the selectivity to SiC is very large.

  As shown in FIG. 21, trench TR is formed in first main surface 10a of silicon carbide substrate 10 by the thermal etching. Trench TR is defined by side SW passing through source region 14 and body region 13 to drift region 12, and bottom BT located in drift region 12. The angle θ formed by the bottom portion BT and the side portion SW is, for example, not less than 110 ° and not more than 130 °. Preferably, the side portion SW includes the special surface described above. In a direction perpendicular to second main surface 10b, third main surface 2a1 of electric field relaxation region 2 is located between bottom portion BT and second main surface 10b.

  Next, a step of forming a gate insulating film is performed. For example, when silicon carbide substrate 10 is thermally oxidized in an oxygen atmosphere, gate insulating film 15 in contact with source region 14, body region 13, and drift region 12 is formed. Specifically, silicon carbide substrate 10 is heated at a temperature of, for example, 1300 ° C. or higher and 1400 ° C. or lower in an atmosphere containing oxygen. Thereby, the gate insulating film 15 in contact with the source region 14, the body region 13, and the drift region 12 in the side portion SW and in contact with the drift region 12 in the bottom portion BT is formed.

After thermally oxidizing silicon carbide substrate 10, heat treatment (NO annealing) may be performed on silicon carbide substrate 10 in a nitrogen monoxide (NO) gas atmosphere. In NO annealing, silicon carbide substrate 10 is held for about 1 hour under conditions of, for example, 1100 ° C. or higher and 1300 ° C. or lower. As a result, nitrogen atoms are introduced into the interface region between the gate insulating film 15 and the body region 13. As a result, the formation of interface states in the interface region is suppressed, so that channel mobility can be improved. As long as nitrogen atoms can be introduced, a gas other than NO gas (for example, N ₂ O) may be used as the atmospheric gas. Ar annealing using argon (Ar) as an atmospheric gas may be further performed after the NO annealing. The heating temperature for Ar annealing is, for example, equal to or higher than the heating temperature for NO annealing. The Ar annealing time is, for example, about 1 hour. As a result, the formation of interface states in the interface region between the gate insulating film 15 and the body region 13 is further suppressed.

  Next, a step of forming a gate electrode is performed. For example, gate electrode 27 in contact with gate insulating film 15 is formed inside trench TR. Gate electrode 27 is arranged inside trench TR and is formed on gate insulating film 15 so as to face each of side portion SW and bottom portion BT of trench TR. The gate electrode 27 is formed by, for example, LPCVD (Low Pressure Chemical Vapor Deposition).

  Next, a step of forming an interlayer insulating film is formed. For example, the interlayer insulating film 22 is formed so as to cover the gate electrode 27 and to be in contact with the gate insulating film 15. Preferably, the interlayer insulating film 22 is formed by a deposition method, more preferably a chemical vapor deposition method. Interlayer insulating film 22 is made of, for example, a material containing silicon dioxide. Next, part of interlayer insulating film 22 and gate insulating film 15 is etched so that an opening is formed on source region 14 and contact region 18. As a result, the contact region 18 and the source region 14 are exposed from the gate insulating film 15 (see FIG. 22).

  Next, a step of forming a source electrode is performed. Next, source electrode 16 in contact with source region 14 and contact region 18 is formed on first main surface 10a. The source electrode 16 is formed by, for example, a sputtering method. The source electrode 16 is made of a material containing, for example, Ti, Al, and Si. Next, alloying annealing is performed. Specifically, the source electrode 16 in contact with the source region 14 and the contact region 18 is held for about 5 minutes at a temperature of 900 ° C. or higher and 1100 ° C. or lower, for example. Thereby, at least a part of source electrode 16 reacts with silicon included in silicon carbide substrate 10 to be silicided. As a result, the source electrode 16 that is in ohmic contact with the source region 14 is formed. Preferably, the source electrode 16 is in ohmic contact with the contact region 18.

  Next, a source wiring 19 that is electrically connected to the source electrode 16 is formed. The source wiring 19 is formed on the source electrode 16 and the interlayer insulating film 22. Next, drain electrode 20 is formed in contact with second main surface 10b of silicon carbide substrate 10. Thus, MOSFET 1 (FIG. 1) according to the present embodiment is completed.

  In the above embodiment, the silicon carbide semiconductor device is described as being a MOSFET, but the silicon carbide semiconductor device is not limited to a MOSFET. The silicon carbide semiconductor device may be, for example, an IGBT (Insulated Gate Bipolar Transistor). In the above embodiment, the n-type is the first conductivity type and the p-type is the second conductivity type. However, the p-type may be the first conductivity type and the n-type may be the second conductivity type. .

Next, functions and effects of the MOSFET according to the embodiment will be described.
According to MOSFET 1 according to the embodiment, width W1 of third main surface 2a1 is larger than width W2 of fourth main surface 2b1. Thereby, the electric field strength in the edge part C3 of the 4th main surface 2b1 of the electric field relaxation area | region 2 can be reduced. Therefore, the occurrence of avalanche breakdown can be suppressed. Further, since the width W1 of the third main surface 2a1 of the electric field relaxation region 2 is large, the third main surface 2a1 can be disposed near the corner C1 of the trench TR. Therefore, the electric field concentration at the corner C1 of the trench TR can be reduced.

  Further, according to MOSFET 1 according to the embodiment, outer edge 13p of second impurity region 13 is provided so as to surround electric field relaxation region 2 when viewed from a direction perpendicular to second main surface 10b. As a result, the current path flowing through the drift region 12 can be prevented from being narrowed. As a result, the on-resistance of MOSFET 1 can be reduced.

  Furthermore, according to MOSFET 1 according to the embodiment, silicon carbide substrate 10 includes fourth impurity region 3 located between body region 13 and electric field relaxation region 2 and having the second conductivity type. Thereby, the second impurity region 13 and the electric field relaxation region 2 can be electrically connected, and the switching speed can be increased.

  Furthermore, according to MOSFET 1 according to the embodiment, fourth impurity region 3 is in contact with both body region 13 and electric field relaxation region 2. Thereby, electrons or holes can be easily supplied from the body region 13 to the electric field relaxation region 2.

Furthermore, according to MOSFET 1 according to the embodiment, body region 13 has fifth main surface 13a that is a boundary surface with drift region 12, and fifth main surface 13a in a direction parallel to second main surface 10b. Half of the width is W _b (μm), half of the width of the third main surface 2a1 in the direction parallel to the second main surface 10b is W _u (μm), and the impurity concentration in the first impurity region 12 is N and _d ^{(cm -3),} the impurity concentration in the electric field relaxation region 2 and _N a ^{(cm -3),} a dielectric constant of vacuum and ^{_{ε 0 (F · m -1)}} , the dielectric constant of the silicon carbide epsilon _SiC ( F · m ⁻¹ ), the elementary charge is e (C), and the diffusion potential is V _bi (V). As a result, the on-resistance can be reduced while keeping the breakdown voltage of the MOSFET 1 high.

Furthermore, according to MOSFET 1 according to the embodiment, silicon carbide substrate 10 is provided on silicon carbide single crystal substrate 11 constituting second main surface 10b, silicon carbide single crystal substrate 11, and first main surface 10a. And silicon carbide epitaxial layer 24 constituting the structure. The impurity dose amount of electric field relaxation region 2 is set to D _rx (cm ⁻² ), and fourth main surface 2b1, silicon carbide single crystal substrate 11 and silicon carbide epitaxial layer 24 in the direction perpendicular to second main surface 10b. When the distance from the boundary surface 11a is L _d (cm) and the impurity concentration in the drift region 12 is N _d (cm ⁻³ ), the above formula 2 is satisfied. Thereby, it is suppressed that the electric field relaxation region 2 is completely depleted before the depletion layer extends from the electric field relaxation region 2 to the boundary surface 11a. Thereby, a depletion layer having a sufficient length can be formed between the electric field relaxation region 2 and the boundary surface 11a. As a result, the breakdown voltage of MOSFET 1 can be kept high.

  Furthermore, according to MOSFET 1 according to the embodiment, angle θ formed by side SW and bottom BT is greater than 90 °. When the angle θ formed by the side portion SW and the bottom portion BT is 90 °, the on-resistance when the electric field relaxation region 2 is located immediately below the side portion SW, and the electric field relaxation region 2 is more first than immediately below the side portion SW. The on-resistance when shifted slightly in the direction parallel to the main surface 10a is greatly different. On the other hand, when the angle θ formed by the side part SW and the bottom part BT is larger than 90 °, even if the position of the electric field relaxation region 2 with respect to the side part SW is slightly changed, the on-resistance is not greatly different. Therefore, when the angle θ formed by the side portion SW and the bottom portion BT is larger than 90 °, even when the position of the electric field relaxation region 2 with respect to the trench TR varies in the plane of the wafer due to, for example, an alignment error, A large change in on-resistance can be suppressed.

  Furthermore, according to MOSFET 1 according to the embodiment, side SW may include first surface S1 having a plane orientation {0-33-8}. Thereby, the channel resistance in the side part SW can be reduced.

  Further, according to MOSFET 1 according to the embodiment, side SW includes microscopically first surface S1, and side SW further includes second surface S2 having a plane orientation {0-11-1}. May be included microscopically. Thereby, the channel resistance in the side part SW can be further reduced.

  Furthermore, according to MOSFET 1 according to the embodiment, first surface S1 and second surface S2 may constitute composite surface SR having a plane orientation {0-11-2}. Thereby, the channel resistance in the side part SW can be further reduced.

  Furthermore, according to MOSFET 1 according to the embodiment, side SW may macroscopically have an off angle of 62 ° ± 10 ° with respect to the {000-1} plane. Thereby, the channel resistance in the side part SW can be further reduced.

(Sample preparation)
First, five types of MOSFETs 1 (see FIG. 2) are prepared by changing the width W1 of the third main surface 2a1 of the electric field relaxation region 2. Specifically, the width W1 of the third major surface 2a1 is 2 μm, 2.5 μm, 3 μm, 3.5 μm, and 4.5 μm. W _p is the half value of the width W1. The width W3 (see FIG. 2) of the fifth major surface 13a of the body region 13 is 2.7 μm. W _b is a half value of the width W3. The concentration of aluminum contained in the electric field relaxation region 2 is 1 × 10 ¹⁸ cm ⁻³ . The concentration of aluminum contained in the body region 13 is 1 × 10 ¹⁸ cm ⁻³ . The concentration of nitrogen included in the drift region 12 is 6 × 10 ¹⁵ cm ⁻³ . The thickness of the drift region 12 is 10 μm. The width W _dep of the depletion layer calculated from the concentration of aluminum contained in the body region 13 and the concentration of nitrogen contained in the drift region 12 is about 0.6 μm.

(Experimental conditions)
The on-resistance and breakdown voltage of the five types of MOSFETs 1 are measured. In the on-resistance measurement, the voltage V _DS between the drain electrode 20 and the source electrode 16 is 2V. The potential difference V _GS between the gate electrode 27 and the source electrode 16 is 15V. The potential difference V _GS between the gate electrode 27 and the source electrode 16 is set to 0V. The voltage V _DS between the drain electrode 20 and the source electrode 16 is changed between 0 V and 1600 V, and the voltage V _DS when the current I _DS flowing between the drain electrode 20 and the source electrode 16 becomes 1 μA is defined as a withstand voltage.

(Experimental result)
FIG. 23 is experimental data showing the relationship between the on-resistance of the MOSFET and W _b −W _u −W _dep . As shown in FIG. 23, the on-resistance rapidly decreases under the condition of W _b −W _u −W _dep > 0 (in other words, W _b > W _u + W _dep ). When W _b −W _u −W _dep ≧ 0.5 μm, the on-resistance tends to be saturated. FIG. 24 is experimental data showing the relationship between the breakdown voltage of the MOSFET and W _b −W _u −W _dep . As shown in FIG. 24, when W _b −W _u −W _dep increases, the breakdown voltage tends to decrease. When W _b −W _u −W _dep ≧ 0.5 μm, the breakdown voltage tends to decrease rapidly. From the above results, it is understood that W _b −W _u −W _dep is preferably larger than 0 and smaller than 0.5 μm from the viewpoint of achieving both breakdown voltage and on-resistance.

  It should be understood that the embodiments and examples disclosed herein are illustrative and non-restrictive in every respect. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 Silicon carbide semiconductor device (MOSFET)
2 Electric field relaxation region 2a1 Third main surface 2a First electric field relaxation region portion 2b1 Fourth main surface 2b Second electric field relaxation region portion 2c Third electric field relaxation region portion 2s Side surface 3 Fourth impurity region 10 Silicon carbide substrate 10a First main Surface 10b Second main surface 11 Silicon carbide single crystal substrate 11a Boundary surface 12 First impurity region (drift region)
13 Second impurity region (body region)
13a 5th main surface 13p, 14p Outer edge 14 3rd impurity region (source region)
15 Gate insulating film 16 Source electrode 18 Contact region 19 Source wiring 20 Drain electrode 22 Interlayer insulating film 24 Silicon carbide epitaxial layer 27 Gate electrode BT Bottom C1, C2 Corner C3 Edge, corner CD Channel direction H1, H2 Thickness H3 H4 distance H5 depth S1 first surface S2 second surface SQ, SR composite surface SW side portion TR trench W1, W2, W3, W4 width

Claims (10)

A silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface;
The silicon carbide substrate includes a first impurity region having a first conductivity type;
A second impurity region provided on the first impurity region and having a second conductivity type different from the first conductivity type;
A third impurity region provided on the second impurity region so as to be separated from the first impurity region, constituting the first main surface, and having the first conductivity type;
An electric field relaxation region located in the first impurity region and having the second conductivity type,
The first main surface is defined by a side portion penetrating the second impurity region and the third impurity region and reaching the first impurity region, and a bottom portion provided continuously with the side portion. Trenches are formed, and
A gate insulating film in contact with the first impurity region at the bottom and in contact with the first impurity region, the second impurity region, and the third impurity region at the side;
The electric field relaxation region has a third main surface facing the first main surface and a fourth main surface facing the second main surface,
In a direction parallel to the second major surface, a width of the third main surface is much larger than the width of the fourth major surface,
The silicon carbide substrate includes a fourth impurity region located between the second impurity region and the electric field relaxation region and having the second conductivity type,
The silicon carbide semiconductor device , wherein a width of the fourth impurity region is smaller than a width of the fourth main surface in a direction parallel to the second main surface .   2. The silicon carbide semiconductor device according to claim 1, wherein an outer edge of the second impurity region is provided so as to surround the electric field relaxation region when viewed from a direction perpendicular to the second main surface. The silicon carbide semiconductor device according to claim 1 , wherein the fourth impurity region is in contact with both the second impurity region and the electric field relaxation region. The second impurity region has a fifth main surface that is a boundary surface with the first impurity region,
Half of the width of the fifth main surface in the direction parallel to the second main surface is W _b (μm), and half of the width of the third main surface in the direction parallel to the second main surface is W _u (μm), the impurity concentration in the first impurity region is N _d (cm ⁻³ ), the impurity concentration in the electric field relaxation region is N _a (cm ⁻³ ), and the vacuum dielectric constant is ε ₀ (F M- ¹ ), the dielectric constant of silicon carbide is ε _SiC (F · m ⁻¹ ), the elementary charge is e (C), and the diffusion potential is V _bi (V). The silicon carbide semiconductor device according to any one of claims 1 to 3 .

The silicon carbide substrate includes a silicon carbide single crystal substrate constituting the second main surface, and a silicon carbide epitaxial layer provided on the silicon carbide single crystal substrate and constituting the first main surface,
The fourth principal surface, the silicon carbide single crystal substrate, and the silicon carbide epitaxial layer in a direction perpendicular to the second principal surface, with an impurity dose of the electric field relaxation region being D _rx (cm ⁻² ) 5. Any one of claims 1 to 4 satisfying the following formula, where L _d (cm) is a distance from the boundary surface of the first impurity region and N _d (cm ⁻³ ) is an impurity concentration in the first impurity region. 2. The silicon carbide semiconductor device according to item 1.

The silicon carbide semiconductor device according to any one of claims 1 to 5 , wherein an angle formed between the side portion and the bottom portion is larger than 90 °. The silicon carbide semiconductor device according to any one of claims 1 to 6 , wherein said side portion includes a first surface having a plane orientation {0-33-8}. The side includes a first surface microscopically, said side further comprises a second plane having a plane orientation of {0-11-1} microscopically claim 7 Silicon carbide semiconductor device. The silicon carbide semiconductor device according to claim 8 , wherein said first surface and said second surface constitute a composite surface having a plane orientation {0-11-2}. The silicon carbide semiconductor device according to claim 9 , wherein said side portion has an off angle of 62 ° ± 10 ° macroscopically with respect to the {000-1} plane.

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