JP5355380B2 - 多層配線基板 - Google Patents
多層配線基板 Download PDFInfo
- Publication number
- JP5355380B2 JP5355380B2 JP2009294435A JP2009294435A JP5355380B2 JP 5355380 B2 JP5355380 B2 JP 5355380B2 JP 2009294435 A JP2009294435 A JP 2009294435A JP 2009294435 A JP2009294435 A JP 2009294435A JP 5355380 B2 JP5355380 B2 JP 5355380B2
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- land
- wiring
- diameter side
- wiring layer
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
- H05K1/116—Lands, clearance holes or other lay-out details concerning the surrounding of a via
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0352—Differences between the conductors of different layers of a multilayer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09372—Pads and lands
- H05K2201/094—Array of pads or lands differing from one another, e.g. in size, pitch or thickness; Using different connections on the pads
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09827—Tapered, e.g. tapered hole, via or groove
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
11…内層の配線層、
12,16…絶縁層、
13,17…ビア、
14,18…(最外層の)配線層、
15,19…ソルダレジスト層(絶縁層)、
L1,L2,L3…ランド、
Db1,Db2,Db3…(ランドサイズの)大径、
Ds1,Ds2,Ds3…(ランドサイズの)小径、
P1,P2…パッド。
Claims (5)
- 内層の配線層に対してその両面に対向する方向からビアが形成され、前記配線層においてそれぞれ当該ビアと接続される箇所に画定されるランドが、その側面がテーパ状となるように形成された構造を有する多層配線基板であって、
前記ランドは、小径側の面にビアが接続される第1のランドと、大径側の面にのみビアが接続される第2のランドからなり、前記第1のランドと前記第2のランドとは同層に形成されており、前記第2のランドの大径側の面の面積が、前記第1のランドの小径側の面の面積と同じになることを特徴とする多層配線基板。 - 内層の配線層に対してその両面に対向する方向からビアが形成され、前記配線層においてそれぞれ当該ビアと接続される箇所に画定されるランドが、その側面がテーパ状となるように形成された構造を有する多層配線基板であって、
前記ランドは、小径側の面にビアが接続される第1のランドと、大径側の面にのみビアが接続される第2のランドからなり、前記第1のランドと前記第2のランドとは同層に形成されており、前記第1のランドの大径側の面の面積の方が、前記第2のランドの大径側の面の面積よりも広いことを特徴とする多層配線基板。 - 前記内層の配線層を挟んで上下に設けられる各絶縁層は、その材料としてプリプレグが使用されていることを特徴とする請求項1又は2に記載の多層配線基板。
- 前記内層の配線層は、前記各絶縁層に設けられる配線に比べて厚く形成されていることを特徴とする請求項3に記載の多層配線基板。
- 前記多層配線基板は、前記ランドの小径側に形成された一面側と、前記ランドの大径側に形成された他面側を有しており、半導体素子搭載面が前記他面側に設けられていることを特徴とする請求項1乃至4のいずれか一項に記載の多層配線基板。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009294435A JP5355380B2 (ja) | 2009-12-25 | 2009-12-25 | 多層配線基板 |
US12/975,703 US8952270B2 (en) | 2009-12-25 | 2010-12-22 | Multilayer wiring board having lands with tapered side surfaces |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009294435A JP5355380B2 (ja) | 2009-12-25 | 2009-12-25 | 多層配線基板 |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2011134957A JP2011134957A (ja) | 2011-07-07 |
JP2011134957A5 JP2011134957A5 (ja) | 2012-12-13 |
JP5355380B2 true JP5355380B2 (ja) | 2013-11-27 |
Family
ID=44186077
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2009294435A Active JP5355380B2 (ja) | 2009-12-25 | 2009-12-25 | 多層配線基板 |
Country Status (2)
Country | Link |
---|---|
US (1) | US8952270B2 (ja) |
JP (1) | JP5355380B2 (ja) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014075515A (ja) * | 2012-10-05 | 2014-04-24 | Shinko Electric Ind Co Ltd | 配線基板及び配線基板の製造方法 |
JP2014120651A (ja) * | 2012-12-18 | 2014-06-30 | Toppan Printing Co Ltd | 積層配線板及びその製造方法 |
JP2014127623A (ja) | 2012-12-27 | 2014-07-07 | Shinko Electric Ind Co Ltd | 配線基板及び配線基板の製造方法 |
US9275925B2 (en) | 2013-03-12 | 2016-03-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | System and method for an improved interconnect structure |
JP2015082524A (ja) * | 2013-10-21 | 2015-04-27 | ソニー株式会社 | 配線基板、半導体装置 |
KR102472945B1 (ko) * | 2015-04-23 | 2022-12-01 | 삼성전기주식회사 | 인쇄회로기판, 반도체 패키지 및 그 제조방법 |
US9659853B2 (en) | 2015-04-24 | 2017-05-23 | Advanced Semiconductor Engineering, Inc. | Double side via last method for double embedded patterned substrate |
JP6816964B2 (ja) | 2016-03-10 | 2021-01-20 | 新光電気工業株式会社 | 配線基板、半導体装置及び配線基板の製造方法 |
JP6615701B2 (ja) | 2016-06-24 | 2019-12-04 | 新光電気工業株式会社 | 配線基板、半導体装置及び配線基板の製造方法 |
KR102530322B1 (ko) | 2018-12-18 | 2023-05-10 | 삼성전자주식회사 | 반도체 패키지 |
JP7512594B2 (ja) | 2020-01-10 | 2024-07-09 | Toppanホールディングス株式会社 | 回路基板 |
CN114080088B (zh) * | 2020-08-10 | 2024-05-31 | 鹏鼎控股(深圳)股份有限公司 | 电路板及其制备方法 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5199163A (en) * | 1992-06-01 | 1993-04-06 | International Business Machines Corporation | Metal transfer layers for parallel processing |
JPH08116174A (ja) * | 1994-08-25 | 1996-05-07 | Matsushita Electric Ind Co Ltd | 回路形成基板およびその製造方法 |
JP3112059B2 (ja) * | 1995-07-05 | 2000-11-27 | 株式会社日立製作所 | 薄膜多層配線基板及びその製法 |
ATE303712T1 (de) * | 1998-04-01 | 2005-09-15 | Mitsui Mining & Smelting Co | Verfahren zur herstellung einer mehrschichtigen gedruckten leiterplatte |
US6810583B2 (en) * | 2001-08-07 | 2004-11-02 | International Business Machines Corporation | Coupling of conductive vias to complex power-signal substructures |
JP2003158379A (ja) | 2001-11-19 | 2003-05-30 | Kyocera Corp | 多層配線基板 |
JP2003298240A (ja) * | 2002-04-05 | 2003-10-17 | Sohwa Corporation | 多層回路基板 |
JP2005072328A (ja) | 2003-08-26 | 2005-03-17 | Kyocera Corp | 多層配線基板 |
JP4551730B2 (ja) * | 2004-10-15 | 2010-09-29 | イビデン株式会社 | 多層コア基板及びその製造方法 |
JP5407667B2 (ja) * | 2008-11-05 | 2014-02-05 | 株式会社村田製作所 | 半導体装置 |
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2009
- 2009-12-25 JP JP2009294435A patent/JP5355380B2/ja active Active
-
2010
- 2010-12-22 US US12/975,703 patent/US8952270B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US8952270B2 (en) | 2015-02-10 |
JP2011134957A (ja) | 2011-07-07 |
US20110155442A1 (en) | 2011-06-30 |
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