JP5108496B2 - 回路基板およびその製造方法、回路装置およびその製造方法 - Google Patents
回路基板およびその製造方法、回路装置およびその製造方法 Download PDFInfo
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- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
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- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
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- H05K2201/09—Shape and layout
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09745—Recess in conductor, e.g. in pad or in metallic substrate
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- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/15—Position of the PCB during processing
- H05K2203/1572—Processing both sides of a PCB by the same process; Providing a similar arrangement of components on both sides; Making interlayer connections from two sides
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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- H05K3/44—Manufacturing insulated metal core circuits or other insulated electrically conductive core circuits
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
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- Insulated Metal Substrates For Printed Circuits (AREA)
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Description
図1を参照して、本実施の形態の回路基板10の構成を説明する。図1(A)は回路基板10を上方から見た斜視図であり、図1(B)は図1(A)のB-B’線に於ける断面図であり、図1(C)は図1(A)のC−C’線に於ける断面図である。
本実施の形態では、図4以降の図を参照して、回路基板および回路装置の製造方法を説明する。
12 金属基板
12A 第1側辺
12B 第2側辺
12C 第3側辺
12D 第4側辺
14 絶縁層
16 導電パターン
18 回路素子
20 リード
22 第1側面
24 第2側面
26 パッド
28 封止樹脂
30 混成集積回路装置
31 回路装置
32 金属基板
32A 第1側辺
32B 第2側辺
32C 第3側辺
32D 第4側辺
34 導電パターン
36 絶縁層
38 開口部
40 発光素子
42 金属細線
44 接合材
46 第1側面
48 第2側面
50 基板
52 カットソー
54 カットソー
56 刃先
58 第1溝
60 第2溝
62 第3溝
64 第4溝
66 ユニット
68 支持部
70 丸カッター
72 金型
74 上金型
76 下金型
78 キャビティ
Claims (9)
- 金属から成る金属基板と、前記金属基板の上面を被覆する絶縁層と、前記絶縁層の表面に形成された導電パターンとを備え、
前記金属基板は、対向する第1側辺および第2側辺と、前記第1側辺および前記第2側辺と交差する方向で対向する第3側辺と第4側辺とを有し、
前記金属基板の側面は、上面から連続して傾斜する第1側面と、下面から連続して傾斜する第2側面とを含み、
前記第1側辺および前記第2側辺では、前記第1側面の幅が前記第2側面よりも短く、
前記第3側辺および第4側辺では、前記第1側面の幅が前記第2側面よりも長いことを特徴とする回路基板。 - 前記導電パターンから成るパッドは、前記第1側辺または前記第2側辺に接近して設けられることを特徴とする請求項1に記載の回路基板。
- 請求項1または請求項2に記載された回路基板と、
前記回路基板に実装されて前記導電パターンに電気的に接続された回路素子と、を具備することを特徴とする回路装置。 - 前記導電パターンから成るパッドに固着されるリードを備えることを特徴とする請求項3に記載の回路装置。
- 前記回路素子を封止すると共に、前記回路基板の少なくとも上面を被覆する封止樹脂を備えることを特徴とする請求項3または請求項4に記載の回路装置。
- 各ユニットを構成する導電パターンが上面に形成され、上面に前記各ユニットの境界に沿って互いに直交する第1溝および前記第1溝よりも浅い第2溝が設けられ、前記第1溝に対向する下面に浅い第3溝が設けられ、前記第2溝に対向する下面に前記第3溝よりも深い第4溝が設けられた、多面取りが可能な基板を用意する工程と、
前記各溝が設けられた箇所にて前記基板を前記各ユニットに分離する工程と、
を備えたことを特徴とする回路基板の製造方法。 - 前記導電パターンから成るパッドが前記ユニットの長手方向の側辺に沿って設けられ、
前記ユニットの長手方向に沿って前記第2溝を設け、前記ユニットの短手方向に沿って前記第1溝を設けることを特徴とする請求項6に記載の回路基板の製造方法。 - 前記第1溝および前記第4溝の深さを、前記基板の厚さの半分以下とすることを特徴とする請求項6または請求項7に記載の回路基板の製造方法。
- 各ユニットを構成する導電パターンが上面に形成され、上面に前記各ユニットの境界に沿って互いに直交する第1溝および前記第1溝よりも浅い第2溝が設けられ、前記第1溝に対向する下面に浅い第3溝が設けられ、前記第2溝に対向する下面に前記第3溝よりも深い第4溝が設けられた、多面取りが可能な基板を用意する工程と、
前記各ユニットの前記導電パターンに回路素子を電気的に接続する工程と、
前記各溝が設けられた箇所にて前記基板を前記各ユニットに分離する工程と、
を備えたことを特徴とする回路装置の製造方法。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007334237A JP5108496B2 (ja) | 2007-12-26 | 2007-12-26 | 回路基板およびその製造方法、回路装置およびその製造方法 |
KR1020080129755A KR101077416B1 (ko) | 2007-12-26 | 2008-12-19 | 회로 기판 및 그 제조 방법, 회로 장치 및 그 제조 방법, 및 기판 |
US12/342,363 US7964957B2 (en) | 2007-12-26 | 2008-12-23 | Circuit substrate, circuit device and manufacturing process thereof |
CN2008101852906A CN101471316B (zh) | 2007-12-26 | 2008-12-24 | 电路基板及其制造方法、电路装置及其制造方法 |
CN2010102434030A CN101945536B (zh) | 2007-12-26 | 2008-12-24 | 电路基板及其制造方法、电路装置及其制造方法 |
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Application Number | Priority Date | Filing Date | Title |
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JP2007334237A JP5108496B2 (ja) | 2007-12-26 | 2007-12-26 | 回路基板およびその製造方法、回路装置およびその製造方法 |
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Publication Number | Publication Date |
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JP2009158687A JP2009158687A (ja) | 2009-07-16 |
JP5108496B2 true JP5108496B2 (ja) | 2012-12-26 |
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JP2007334237A Active JP5108496B2 (ja) | 2007-12-26 | 2007-12-26 | 回路基板およびその製造方法、回路装置およびその製造方法 |
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US (1) | US7964957B2 (ja) |
JP (1) | JP5108496B2 (ja) |
KR (1) | KR101077416B1 (ja) |
CN (2) | CN101471316B (ja) |
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US8471443B2 (en) | 2009-11-09 | 2013-06-25 | Lg Innotek Co., Ltd. | Lighting device |
US8829771B2 (en) * | 2009-11-09 | 2014-09-09 | Lg Innotek Co., Ltd. | Lighting device |
US8975535B2 (en) | 2009-12-24 | 2015-03-10 | Kyocera Corporation | Many-up wiring substrate, wiring substrate, and electronic device |
US8569894B2 (en) | 2010-01-13 | 2013-10-29 | Advanced Semiconductor Engineering, Inc. | Semiconductor package with single sided substrate design and manufacturing methods thereof |
JP5283195B2 (ja) * | 2010-09-07 | 2013-09-04 | シーシーエス株式会社 | Led配線基板及び光照射装置 |
US9406658B2 (en) | 2010-12-17 | 2016-08-02 | Advanced Semiconductor Engineering, Inc. | Embedded component device and manufacturing methods thereof |
US8487426B2 (en) * | 2011-03-15 | 2013-07-16 | Advanced Semiconductor Engineering, Inc. | Semiconductor package with embedded die and manufacturing methods thereof |
DE102011018295B4 (de) * | 2011-04-20 | 2021-06-24 | Austriamicrosystems Ag | Verfahren zum Schneiden eines Trägers für elektrische Bauelemente |
JP6006474B2 (ja) * | 2011-04-25 | 2016-10-12 | 日本特殊陶業株式会社 | 配線基板、多数個取り配線基板、およびその製造方法 |
US8649820B2 (en) | 2011-11-07 | 2014-02-11 | Blackberry Limited | Universal integrated circuit card apparatus and related methods |
DE102011056890A1 (de) * | 2011-12-22 | 2013-06-27 | Osram Opto Semiconductors Gmbh | Anschlussträger, optoelektronische Bauelementanordnung und Beleuchtungsvorrichtung |
JP5888995B2 (ja) * | 2012-01-16 | 2016-03-22 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
US8936199B2 (en) | 2012-04-13 | 2015-01-20 | Blackberry Limited | UICC apparatus and related methods |
USD703208S1 (en) | 2012-04-13 | 2014-04-22 | Blackberry Limited | UICC apparatus |
USD701864S1 (en) * | 2012-04-23 | 2014-04-01 | Blackberry Limited | UICC apparatus |
JP2014053506A (ja) * | 2012-09-07 | 2014-03-20 | Toshiba Corp | 半導体発光装置及び発光モジュール |
CN103021891B (zh) * | 2012-12-27 | 2017-04-26 | 中国电子科技集团公司第四十一研究所 | 一种混合集成电路金属化互联方法 |
GB2532869A (en) * | 2013-08-28 | 2016-06-01 | Qubeicon Ltd | Semiconductor die and package jigsaw submount |
JP6210818B2 (ja) * | 2013-09-30 | 2017-10-11 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
KR102198858B1 (ko) | 2014-07-24 | 2021-01-05 | 삼성전자 주식회사 | 인터포저 기판을 갖는 반도체 패키지 적층 구조체 |
JP6419611B2 (ja) * | 2015-03-12 | 2018-11-07 | 株式会社東芝 | プリント基板 |
JP2017010984A (ja) * | 2015-06-17 | 2017-01-12 | 日本電産サンキョー株式会社 | 回路基板 |
US10083888B2 (en) * | 2015-11-19 | 2018-09-25 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package |
JP6589631B2 (ja) * | 2015-12-25 | 2019-10-16 | 富士電機株式会社 | 半導体装置 |
CN108781502B (zh) | 2016-04-22 | 2021-11-30 | 京瓷株式会社 | 多连片布线基板、布线基板 |
US9991193B2 (en) | 2016-06-15 | 2018-06-05 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package |
CN107241857B (zh) * | 2017-06-27 | 2019-08-13 | 华为技术有限公司 | 一种印刷电路板和通信设备 |
CN110366318B (zh) * | 2019-07-16 | 2021-05-11 | 深圳市星河电路股份有限公司 | 一种减小v-cut线到导线间距的加工工艺 |
DE102019121449A1 (de) * | 2019-08-08 | 2021-02-11 | OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung | Verfahren zur vereinzelung von bauteilen aus einem bauteilverbund sowie bauteil |
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US5294826A (en) * | 1993-04-16 | 1994-03-15 | Northern Telecom Limited | Integrated circuit package and assembly thereof for thermal and EMI management |
JP2923728B2 (ja) | 1993-11-15 | 1999-07-26 | 富士通電装株式会社 | 金属ベース配線基板の製造方法 |
JPH09162507A (ja) * | 1995-12-08 | 1997-06-20 | Nippon Seiki Co Ltd | 金属ベースプリント基板 |
JP2755252B2 (ja) * | 1996-05-30 | 1998-05-20 | 日本電気株式会社 | 半導体装置用パッケージ及び半導体装置 |
JPH1022630A (ja) | 1996-06-28 | 1998-01-23 | Nippon Seiki Co Ltd | 金属ベースプリント基板の分割方法 |
JP4039881B2 (ja) | 2002-04-24 | 2008-01-30 | 三洋電機株式会社 | 混成集積回路装置の製造方法 |
JP3896029B2 (ja) * | 2002-04-24 | 2007-03-22 | 三洋電機株式会社 | 混成集積回路装置の製造方法 |
JP2004006585A (ja) * | 2002-04-24 | 2004-01-08 | Sanyo Electric Co Ltd | 混成集積回路装置の製造方法 |
JP2005123606A (ja) * | 2003-09-25 | 2005-05-12 | Sanyo Electric Co Ltd | 混成集積回路装置およびその製造方法 |
US7232957B2 (en) * | 2003-09-25 | 2007-06-19 | Sanyo Electric Co., Ltd. | Hybrid integrated circuit device and method of manufacturing the same |
JP2006100750A (ja) * | 2004-09-30 | 2006-04-13 | Sanyo Electric Co Ltd | 回路装置およびその製造方法 |
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CN101471316B (zh) | 2012-05-30 |
KR101077416B1 (ko) | 2011-10-26 |
JP2009158687A (ja) | 2009-07-16 |
CN101945536B (zh) | 2012-11-28 |
CN101471316A (zh) | 2009-07-01 |
US20090166895A1 (en) | 2009-07-02 |
CN101945536A (zh) | 2011-01-12 |
US7964957B2 (en) | 2011-06-21 |
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