JP4525896B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device having a thin silicide layer with a low resistance in a source region or a drain region, and a method for manufacturing the same.

  In recent years, with the miniaturization of semiconductor devices, shallow source regions or drain regions (hereinafter referred to as “source / drain regions”) may be formed in order to suppress punch-through that occurs due to a reduction in gate length.

In recent years, attention has been focused on a technique for forming an insulated gate transistor in an SOI layer as a semiconductor device capable of realizing high-speed operation with low power consumption. Even in such a semiconductor device having an SOI structure, the SOI layer is thinned in response to a request for further improvement in characteristics, and accordingly, a shallow source / drain region is formed. A silicide layer may be formed in the source / drain region in order to reduce the resistance, but as described above, as the source / drain region becomes shallower, the silicide layer is required to be thinner. It has become.
JP 2002-261274 A

  As described above, it is desired to reduce the thickness of the silicide layer. However, the silicidation reaction is affected by the temperature and time of heat treatment or the type and concentration of impurities introduced into the semiconductor layer in the source / drain region. Therefore, it is difficult to control the film thickness while maintaining characteristics (such as low resistance).

  An object of the present invention is to provide a semiconductor device having a low-resistance, thin-film silicide layer in a source / drain region and a method for manufacturing the same.

The semiconductor device of the present invention includes a semiconductor layer,
A gate insulating layer provided above the semiconductor layer;
A gate electrode provided above the gate insulating layer;
A silicidation reaction suppression layer provided in a predetermined region of the semiconductor layer;
A source region or a drain region provided in the semiconductor layer and the silicidation reaction suppression layer;
And a silicide layer provided above the source region or the drain region.

  According to the semiconductor device of the present invention, the silicide layer is provided above the source / drain region having the silicidation reaction suppression layer at the top. Usually, the silicide layer on the source / drain region is formed by silicidizing the upper surface of the semiconductor layer in the source / drain region. Therefore, the resistance value of the silicide layer may be different due to different conductivity types of impurities introduced into the source / drain regions. As described above, the difference in the resistance value of the drain region due to the difference in the conductivity type of the transistor may be a cause of deteriorating the characteristics of the semiconductor device. However, according to the semiconductor device of the present invention, since the silicide layer is formed on the source / drain region, the drain is not affected by the impurity introduced into the source / drain region, but depending on the conductivity type of the transistor. It is possible to prevent the resistance values of the regions from being different. As a result, a highly reliable semiconductor device can be provided.

  The semiconductor device of the present invention can further take the following aspects.

  In the semiconductor device of the present invention, the silicidation reaction suppression layer may be a silicon germanium layer.

  In the semiconductor device of the present invention, the silicide layer may be a layer having a lower impurity concentration than the source region or the drain region. According to this aspect, since the silicide layer has a lower impurity concentration than the source / drain region, the silicide layer has a stable and low-resistance silicide layer without being affected by the impurities introduced into the source / drain region. A semiconductor device can be provided. Here, the impurity concentration of the silicide layer refers not only to n-type or p-type impurities introduced into the source / drain regions, but also to elements other than silicon contained in the silicidation reaction suppression layer. This refers to the concentration of impurities contained.

  In the semiconductor device of the present invention, the silicidation reaction suppression layer can be formed above the semiconductor layer. This aspect is particularly advantageous in the case of a semiconductor device having a thin semiconductor layer. For example, when the thickness of the semiconductor layer is small, the depth of the impurity region serving as the source region or the drain region becomes shallow, and the resistance of the source region or the drain region may not be reduced. However, according to this aspect, the impurity region having a desired depth can be formed by raising the silicidation reaction suppression layer on the semiconductor layer.

  In the semiconductor device of the present invention, the upper surface of the silicidation reaction suppressing layer may be the same height as the surface of the semiconductor layer. According to this aspect, it is possible to provide a semiconductor device in which the silicidation reaction suppressing layer is embedded in the semiconductor layer.

  In the semiconductor device of the present invention, the semiconductor layer may be an SOI layer.

The method for producing a semiconductor layer of the present invention includes:
Forming a gate insulating layer on the semiconductor layer;
Forming a gate electrode on the gate insulating layer;
Forming a silicidation reaction suppression layer in a predetermined region of the semiconductor layer;
Forming a source region or a drain region in the silicidation reaction suppressing layer and the semiconductor layer;
Forming a silicon layer above the source or drain region;
Forming a silicide layer by siliciding the silicon layer.

  According to the method for manufacturing a semiconductor device of the present invention, the silicide layer is formed after the source / drain regions are formed in the semiconductor layer and the silicidation reaction suppression layer. Usually, the silicide layer is formed by forming a metal layer directly on the semiconductor layer in which the source / drain regions are formed and reacting the metal layer with the semiconductor layer. However, in the method for manufacturing a semiconductor device according to the present invention, a silicide layer is formed by forming a silicon layer on the source / drain regions and siliciding the silicon layer. Therefore, the silicidation reaction can be performed in a state where the influence of the type and concentration of impurities introduced into the semiconductor layer in the source / drain region is reduced. In addition, a silicidation reaction suppression layer is formed on the top of the source / drain region. Therefore, the thickness of the silicide layer can be easily controlled, and a thin silicide layer can be formed. As a result, a semiconductor device having a low resistance and thin silicide layer can be manufactured.

  The method for manufacturing a semiconductor device of the present invention can further take the following aspects.

  In the method for manufacturing a semiconductor device of the present invention, the silicidation reaction suppression layer can be formed above the semiconductor layer by an epitaxial growth method. This aspect is particularly advantageous in the case of a semiconductor device having a thin semiconductor layer. For example, when the thickness of the semiconductor layer is small, the depth of the impurity region that becomes the source / drain region becomes shallow, and the resistance of the source / drain region may not be lowered. However, according to this aspect, the impurity region having a desired depth can be formed by depositing the silicidation reaction suppression layer above the semiconductor layer.

  In the method for manufacturing a semiconductor device of the present invention, the silicidation reaction suppressing layer can be performed by introducing an ion species capable of suppressing silicidation into the semiconductor layer. According to this aspect, the silicidation suppression layer can be provided in the semiconductor layer.

  In the method of manufacturing a semiconductor device according to the present invention, the source region or the drain region can be formed by introducing a diffusion treatment after introducing impurities into the semiconductor layer and the silicidation reaction suppression layer. According to this aspect, the heat treatment for diffusing the impurities is performed before the silicide layer is formed. When the heat treatment for forming the source / drain regions is performed after the formation of the silicide layer, the silicidation reaction may be accelerated depending on the temperature of the heat treatment, and the thin silicide layer may not be formed. However, according to this aspect, since the silicide layer is formed after the source / drain regions are formed, it is possible to prevent such a problem from occurring.

  In the method for manufacturing a semiconductor device of the present invention, the silicon layer can be formed by an epitaxial growth method. According to this aspect, the silicon layer can be formed on the semiconductor layer by self-alignment.

  In the method for manufacturing a semiconductor device of the present invention, the silicon layer can be formed by forming a deposited silicon layer over the entire surface of the semiconductor layer and then patterning the deposited silicon layer.

  Hereinafter, an example of an embodiment of the present invention will be described.

1. Semiconductor Device A semiconductor device 100 according to the present embodiment will be described with reference to FIG. FIG. 1 is a cross-sectional view schematically showing a semiconductor device 100 according to the present embodiment. In the present embodiment, an example using the SOI substrate 10A will be described.

  As shown in FIG. 1, a gate electrode 22 is formed on a SOI substrate 10 </ b> A in which a semiconductor layer 10 is provided on a support substrate 6 and an insulating layer 8 with a gate insulating layer 20 interposed therebetween. Examples of the semiconductor layer 10 include a single crystal silicon layer. A sidewall insulating layer 24 is formed on the side surface of the gate electrode 22. An extension region 28 is provided in the semiconductor layer 10 below the sidewall insulating layer 24, and a source region or a drain region 26 is provided in the semiconductor layer 10 outside the semiconductor layer 10. In the semiconductor device 100 of the present embodiment, the source / drain region 26 is formed by introducing impurities into the semiconductor layer 10 and the silicidation reaction suppression layer 30 formed from the upper surface of the semiconductor layer 10. . The silicidation reaction suppression layer 30 may be any layer that can suppress the silicidation reaction with the metal layer. For example, a silicon germanium layer can be used. A silicide layer 40 is provided on the source / drain region 26. The silicide layer 40 is obtained by silicidizing a silicon layer into which no impurity is implanted, and is composed of a layer having a lower impurity concentration than the impurity concentration of the source / drain region 26. In the present embodiment, the impurities contained in the silicide layer 40 are contained in the silicidation reaction suppression layer 30 in addition to n-type impurities such as phosphorus and arsenic and p-type impurities such as boron. Also includes elemental species other than silicon. The low impurity concentration in the silicide layer 40 includes the case where n-type impurities, p-type impurities, germanium, and the like are not contained.

(Modification)
Next, a semiconductor device 110 according to a modification will be described with reference to FIG. FIG. 2 is a cross-sectional view schematically showing a semiconductor device according to a modification. In this modification, a case where a bulk semiconductor layer 10 is used will be described. The semiconductor device 110 according to the modification is an example in which the structure of the source / drain region 26 is different from that of the above-described embodiment.

  As described in the above embodiment, the gate insulating layer 20, the gate electrode 22, and the sidewall insulating layer 24 are provided on the semiconductor layer 10, and the semiconductor layer 10 includes the source / drain region 26 and the extension region. 28 is provided. The source / drain region 26 includes the semiconductor layer 10 and the silicidation reaction suppression layer 30, and the silicide layer 40 is provided on the source / drain region 26. The upper surface of the silicidation reaction suppression layer 30 is the same height as the surface of the semiconductor layer 10. That is, the silicidation reaction suppression layer 30 is embedded in the semiconductor layer 10. The silicide layer 40 is a layer formed by providing a silicon layer (not shown) on the source / drain region 26 and siliciding the silicon layer. Therefore, the layer has a lower impurity concentration than the source / drain region 26.

According to the semiconductor device of the present embodiment, the silicide layer 40 is provided above the source / drain region 26 having the silicidation reaction suppression layer 30 at the top. Usually, the silicide layer on the source / drain region is formed by silicidizing the upper surface of the semiconductor layer in the source / drain region. Therefore, the resistance value of the silicide layer may be different due to different conductivity types of impurities introduced into the source / drain regions. As described above, the difference in the resistance value of the drain region due to the difference in the conductivity type of the transistor may impair the characteristics of the semiconductor device. However, according to the semiconductor device 100 of the present embodiment, since the silicide layer 40 is formed on the source / drain region 26, the resistance is not affected by impurities introduced into the source / drain region 26. It is possible to prevent the values from being different. As a result, highly reliable semiconductor devices 100 and 110 can be provided.

2. Semiconductor Device Manufacturing Method Next, a semiconductor device manufacturing method according to the present embodiment will be described with reference to FIGS. In the present embodiment, a case where an SOI substrate 10A is used will be described as an example.

  (1) First, as shown in FIG. 3, the gate insulating layer 20, the gate electrode 22, and the gate electrode 22 are provided on the SOI substrate 10 </ b> A including the support substrate 6, the insulating layer 8, and the semiconductor layer 10. Sidewall insulating layers 24 and extension regions 28 are formed. An example of the process so far is shown below. First, element isolation of the semiconductor layer 10 is performed by a known element isolation technique such as the LOCOS method, the STI method, or the mesa method. A gate insulating layer 20 is formed on the semiconductor layer 10 by, for example, a thermal oxidation method or a CVD method. Next, a conductive layer (not shown) to be the gate electrode 22 is formed on the gate insulating layer 20. By patterning this conductive layer, the gate electrode 22 is formed. Next, an impurity of a predetermined conductivity type is introduced into the semiconductor layer 10 in order to form an impurity region that becomes the extension region 28 using at least the gate electrode 22 as a mask. Next, a sidewall insulating layer 24 is formed on the side surface of the gate electrode 22. The sidewall insulating layer 24 can be formed by forming an insulating layer (not shown) so as to cover the entire surface of the semiconductor layer 10, and then performing anisotropic etching to form the sidewall insulating layer 24. .

  (2) Next, as shown in FIG. 4, the silicidation reaction suppression layer 30 is formed on the exposed semiconductor layer 10. As the silicidation reaction suppression layer 30, for example, a silicon germanium layer can be formed. In the case of forming the silicon germanium layer, for example, it can be performed by an epitaxial growth method. The silicidation reaction suppression layer 30 is a layer that can suppress a silicidation reaction as compared with a case where a silicon layer and a metal layer are silicidized when a metal layer is formed on the silicidation reaction suppression layer 30 and silicidated. If it is. The state in which the silicidation reaction is suppressed specifically refers to a case where the reaction rate of the silicidation reaction is reduced. Further, the film thickness may be sufficient to suppress silicidation reaction. In the case where the thickness of the source / drain region 26 is increased by raising the silicidation reaction suppression layer 30 when the semiconductor layer is thin as in the present embodiment, It is preferable that the film thickness satisfy the purpose. In the case of a silicon germanium layer, the film thickness of the silicidation reaction suppression layer 30 can be, for example, 3 to 40 nm. Moreover, the germanium composition ratio at this time can be 10 to 50%. The silicidation reaction suppression layer 30 is not limited to a silicon germanium layer, and may be a layer in which impurities such as F, O, and N are introduced into the semiconductor layer 10.

  (3) Next, as shown in FIG. 5, impurities of a predetermined conductivity type are introduced into the semiconductor layer 10 and the silicidation reaction suppression layer 30. Next, the introduced impurity is diffused by heat treatment, whereby the source / drain region 26 is formed.

  (4) Next, as shown in FIG. 6, a silicon layer 42 is formed on the silicidation reaction suppression layer 30. The silicon layer 42 may be a single crystal silicon layer or an amorphous silicon layer. The silicon layer 42 may be formed by, for example, a method of selectively forming on the semiconductor layer by an epitaxial growth method, or a method of patterning after forming an amorphous silicon layer over the entire surface of the semiconductor layer by a CVD method or the like. it can. At this time, the film thickness of the silicon layer 42 may be, for example, 10 to 30 nm.

  (5) Next, as shown in FIG. 7, a metal layer 44 for forming silicide is formed on the entire surface of the semiconductor layer 10. Examples of the metal layer 44 include cobalt, tantalum, and titanium. Further, although not shown, the metal layer 44 may be a laminate of a metal layer and a refractory metal compound layer containing the metal. Examples of such a combination of a metal layer and a refractory metal compound layer include Ti / TiN.

  If the silicon layer 42 is a single crystal layer before the formation of the metal layer 44, at least the surface silicon layer can be amorphized. Thus, the silicidation reaction can be favorably performed by making the single crystal silicon layer amorphous before forming the metal layer 44. This step of amorphizing the single crystal silicon layer can be performed by implanting ionized Ar or Si into the silicon layer.

  Next, heat treatment for silicidation is performed. This heat treatment is performed by a two-stage heat treatment. The first heat treatment is performed at a processing temperature of 650 to 750 ° C., thereby forming the silicide layer 40 (see FIG. 1). This first stage treatment is preferably performed at a lower temperature than the heat treatment for forming the source / drain regions 26 described above. In this case, element types other than the constituent elements of the silicide layer 40 such as n-type and p-type impurities introduced into the source / drain regions 26 and germanium contained in the silicidation reaction suppression layer 30 are formed in the silicide layer. Diffusion to 40 can be suppressed. Therefore, a good silicide layer 40 can be formed.

Next, the unreacted metal layer 44 is removed. The unreacted metal layer 44 can be removed by wet etching using a mixed solution of NH ₄ OH, H ₂ O ₂ , and H ₂ O. Thereafter, a second heat treatment is performed to further reduce the resistance of the silicide layer. The second heat treatment can be performed at a temperature of 800 to 850 ° C., for example. Thereby, the semiconductor device 100 according to the present embodiment can be manufactured.

(Modification)
Next, a method for manufacturing the semiconductor device 110 according to the modification will be described with reference to FIGS. In this modification, a case where a bulk semiconductor layer 10 is used will be described. Note that detailed description of steps that can be performed in the same manner as in the above embodiment is omitted.

  (1) Similar to (1) of the above-described embodiment, the gate insulating layer 20, the gate electrode 22, the sidewall insulating layer 24, and the extension region 28 are formed on the semiconductor layer 10 ( (See FIG. 3).

  (2) Next, as shown in FIG. 8, the silicidation reaction suppression layer 30 is formed in the semiconductor layer 10. As the silicidation reaction suppression layer 30, a silicon germanium layer can be formed. In this case, the silicidation reaction suppression layer 30 can be formed by implanting germanium ions into the semiconductor layer 10. The upper surface of the silicidation reaction suppression layer 30 is formed to be the same height as the surface of the semiconductor layer 10.

  (3) Next, as shown in FIG. 9, impurities of a predetermined conductivity type are introduced into the semiconductor layer 10 and the silicidation reaction suppression layer 30. Next, the introduced impurity is diffused by heat treatment, whereby the source / drain region 26 is formed.

  (4) Next, as shown in FIG. 10, a silicon layer 42 is formed on the silicidation reaction suppression layer 30. This step can be performed in the same manner as in the above embodiment. Thereafter, the upper silicide layer 40 of the source / drain region 26 can be formed by siliciding the silicon layer 42. This silicidation step can be performed in the same manner as in the above embodiment. Through the above steps, the semiconductor device 110 according to the modification can be manufactured.

  According to the semiconductor device manufacturing method of the present embodiment, after forming the source / drain region 26 in the semiconductor layer 10 and the silicidation reaction suppression layer 30, the silicon layer 42 is formed on the source / drain region 26, By siliciding the silicon layer 42, the silicide layer 40 is formed. Since the silicidation reaction suppression layer 30 is a layer that is less susceptible to reaction with the metal layer 44 than the semiconductor layer 10, that is, silicidation reaction, the thickness of the silicide layer 40 can be easily controlled. A thin silicide layer 40 can be formed.

  Further, according to the manufacturing method of the present embodiment, the source / drain region 26 is formed before the silicon layer 42 for the silicide layer 40 is formed. Therefore, the silicon layer 42 that reacts with the metal layer 44 does not contain n-type or p-type impurities or germanium, and the silicidation reaction can be satisfactorily performed. As a result, a good silicide layer 40 with low resistance can be formed.

  Further, in the method for manufacturing the semiconductor device 100 of the present embodiment, the silicidation reaction suppression layer 30 is formed on the semiconductor layer 10, and the silicidation reaction suppression layer 30 deposited on the semiconductor layer 10. Thus, a semiconductor device having a so-called elevated structure can be manufactured. In this case, there is an advantage particularly when an SOI substrate 10A having a thin semiconductor layer 10 is applied. That is, the depth of the source / drain region 26 can be secured by the thickness of the silicidation reaction suppression layer 30. Therefore, although the film thickness of the semiconductor layer 10 in the channel region is thin, a desired film thickness can be secured in the source / drain region 26, and the resistance of the source / drain region 26 is reduced while suppressing punch-through. The semiconductor device 100 can be manufactured.

  Further, in the method of manufacturing the semiconductor device 110 according to this modification, the silicidation reaction suppression layer 30 is formed on the uppermost surface of the source / drain region 26 of the semiconductor layer 10 by ion implantation of element species that suppress the silicidation reaction. Can be formed. Therefore, when the silicide layer 40 on the source / drain region 26 is formed, it is possible to prevent the silicidation reaction from being excessively promoted, and the thin silicide layer 40 can be formed.

1 is a cross-sectional view schematically showing a semiconductor device according to an embodiment. Sectional drawing which shows typically the semiconductor device concerning a modification. Sectional drawing which shows typically the manufacturing process of the semiconductor device of this Embodiment. Sectional drawing which shows typically the manufacturing process of the semiconductor device of this Embodiment. Sectional drawing which shows typically the manufacturing process of the semiconductor device of this Embodiment. Sectional drawing which shows typically the manufacturing process of the semiconductor device of this Embodiment. Sectional drawing which shows typically the manufacturing process of the semiconductor device of this Embodiment. Sectional drawing which shows typically the manufacturing process of the semiconductor device concerning a modification. Sectional drawing which shows typically the manufacturing process of the semiconductor device concerning a modification. Sectional drawing which shows typically the manufacturing process of the semiconductor device concerning a modification.

Explanation of symbols

  6 support substrate, 8 insulating layer, 10 semiconductor layer, 10A SOI substrate, 20 gate insulating layer, 22 gate electrode, 24 sidewall insulating layer, 26 source / drain region, 28 extension region, 30 silicidation reaction suppression layer, 40 silicide Layer, 42 silicon layer, 44 metal layer, 100, 110 semiconductor device

Claims (5)

Forming a gate insulating layer on the semiconductor layer;
Forming a gate electrode on the gate insulating layer;
Forming a silicidation reaction suppression layer in a predetermined region of the semiconductor layer;
Forming a source region and a drain region in the silicidation reaction suppression layer and the semiconductor layer,
Forming a silicon layer above the source region or the drain region,
Look including a step of forming a silicide layer by siliciding the silicon layer,
The top of the source region and the drain region is the silicidation reaction suppression layer,
The method for manufacturing a semiconductor device, wherein the silicidation reaction suppression layer is performed by introducing an ion species capable of suppressing silicidation into the semiconductor layer. In claim 1,
The method for manufacturing a semiconductor device, wherein the upper surface of the silicidation reaction suppression layer is formed to be the same height as the surface of the semiconductor layer. In claim 1 or 2 ,
Formation of the source region or the drain region,
Wherein after introducing the impurity into the semiconductor layer and the silicidation reaction suppressing layer is formed by performing spreading processing, a method of manufacturing a semiconductor device. In any one of claims 1 to 3,
The silicon layer is formed by an epitaxial growth method. In any one of claims 1 to 3,
The silicon layer is formed by forming a deposited silicon layer over the entire surface of the semiconductor layer and then patterning the deposited silicon layer.

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