JP4828982B2 - Manufacturing method of semiconductor device - Google Patents

Description

The present invention is related to a method of manufacturing a semiconductor equipment.

  Conventionally, polysilicon has been widely used as a gate electrode material in MOS (Metal Oxide Semiconductor) devices. However, in such a MOS device, as miniaturization progresses, there is a concern about a decrease in driving current due to an increase in resistance of the polysilicon gate electrode and generation of a depletion layer. In recent years, attempts have been made to form a gate electrode using a metal material instead of polysilicon.

  In a metal gate electrode formed using a metal material, it is necessary to control the work function in order to control the threshold voltage. Therefore, conventionally, there has been a method of forming metal gate electrodes made of different metal materials for an n-channel MOS field effect transistor (referred to as “nMOSFET”) and a p-channel MOS field effect transistor (referred to as “pMOSFET”). Have been taken.

  In recent years, a method of modulating the work function by adding nitrogen (N) to a metal material has also been proposed (see Non-Patent Document 1). In addition, a method has been proposed in which metal gate electrodes are separately formed on nMOSFETs and pMOSFETs using metal materials having different work functions (see Non-Patent Document 2).

In addition, for example, when a CMOS (Complementary Metal Oxide Semiconductor) field effect transistor (referred to as “CMOSFET”) is formed using a metal gate electrode, a layer made of the same metal material is formed on the nMOSFET and the pMOSFET. A method has been proposed in which the work function of the metal gate electrodes of the nMOSFET and pMOSFET is made different by adding N after masking one region (see Patent Document 1). Further, after forming a layer made of the same metal material on the nMOSFET and the pMOSFET and adding N to the whole, the N is outwardly diffused from one region, and the N is outwardly diffused from the other region. There has also been proposed a method in which the work functions of the metal gate electrodes of the nMOSFET and the pMOSFET are made different from each other by covering them so that they are not made (see Patent Document 2).
“IEEE Electron Device Letters”, February 2004, Vol. 25, no. 2, p. 70 “VLSI Symposium Digest of Technology”, June 2005, pp. 199 50-51 JP 2000-31296 A JP 2005-79512 A

  However, when the metal gate electrodes of nMOSFET and pMOSFET are formed of different metal materials, it is necessary to form the metal gate electrodes of nMOSFET and pMOSFET separately, so that the manufacturing process and device structure are compared with conventional device manufacturing. Becomes complicated and increases the manufacturing cost.

  Further, when the metal gate electrodes of the nMOSFET and the pMOSFET are formed from the same metal material and the work function of both is controlled by adjusting the amount of N added, the addition of N increases the resistance of the metal gate electrode. However, there are still problems such as the manufacturing process becoming complicated.

See Kan a point such as this, and an object thereof is to provide a semiconductor device having a having and low resistance metal gate electrode a suitable work function.
Moreover, without complicating the manufacturing process, and an object thereof is to provide a method of manufacturing a semiconductor device capable of forming have a suitable work function and low resistance metal gate electrode.

According to one aspect of the present invention , in a method for manufacturing a complementary semiconductor device including a metal gate electrode, a step of forming a gate insulating film on a semiconductor layer in an nMOSFET formation region and a pMOSFET formation region, and the formed gate Forming a lower conductive layer on the insulating film; forming an upper conductive layer on the formed lower conductive layer; forming the nMOSFET formation region on the formed upper conductive layer; and introducing nitrogen so that the nitrogen concentration differs in the pMOSFET formation region, forming a low resistance layer on the upper conductive layer in the nMOSFET formation region and the pMOSFET formation region after introducing nitrogen, and After forming the resistance layer, performing a heat treatment for diffusing nitrogen from the upper conductive layer to the lower conductive layer, and In the step of forming, a hafnium nitride layer or a zirconium nitride layer having a nitrogen concentration exhibiting a work function suitable for an nMOSFET is deposited on the gate insulating film as the lower conductive layer of the nMOSFET formation region and the pMOSFET formation region. In the step of forming the upper conductive layer, a molybdenum layer is deposited as the upper conductive layer on the lower conductive layer without introducing nitrogen, and the nMOSFET forming region is formed on the upper conductive layer. In the step of introducing nitrogen so that the nitrogen concentration differs between the pMOSFET formation region, the lower layer side of the pMOSFET formation region when the heat treatment is performed later on only the upper conductive layer of the pMOSFET formation region. Nitrogen so that the conductive layer has a nitrogen concentration that exhibits a work function suitable for pMOSFETs. Introduced, after nitrogen introduction, depositing a molybdenum layer on the upper conductive layer of the nMOSFET formation region and the pMOSFET formation region as the low-resistance layer, wherein after the formation of the low-resistance layer, a semiconductor device for performing the heat treatment A manufacturing method is provided.

  According to such a method for manufacturing a semiconductor device, a conductive layer is laminated on a semiconductor layer via a gate insulating film, and the N concentration is different between the nMOSFET formation region and the pMOSFET formation region with respect to the upper conductive layer. N is introduced. Then, after introducing N, a low resistance layer is formed on the conductive layer, and then heat treatment is performed, and N is diffused and introduced from the upper conductive layer to the lower conductive layer of the stacked conductive layers. As a result, a metal gate electrode having an appropriate work function is formed in each of the nMOSFET and the pMOSFET, and N is introduced into the lower layer conductive layer by the low resistance layer formed in the uppermost layer. Even if it exists, the low resistance comes to be achieved.

According to the method disclosed, forming the work function control layer of the metal gate electrode of the nMOSFET and pMOSFET a laminated structure of conductive layers with different N concentration, that to form a low-resistance layer on the work function control layer. As a result, a metal gate electrode having an appropriate work function can be formed in each of the nMOSFET and the pMOSFET, and the resistance is reduced by the low resistance layer, so that the performance of the complementary semiconductor device having the metal gate electrode is improved. Can be achieved.

It will be described in detail with reference to FIG surface.
FIG. 1 is a diagram showing a configuration example of a CMOSFET provided with a metal gate electrode.
In the CMOSFET 1 shown in FIG. 1, an nMOSFET 10 and a pMOSFET 20 are formed in the element region defined by the element isolation region 3 of the semiconductor substrate 2.

  The nMOSFET 10 includes a metal gate electrode 12 having a three-layer structure in which a hafnium nitride (HfN) layer 12a and metal layers 12b and 12c such as molybdenum (Mo) are sequentially stacked on a semiconductor substrate 2 via a gate insulating film 11. have. Side walls 13 are formed on the side walls of the metal gate electrode 12, and LDDs 14a and source / drain regions 14 are formed in the semiconductor substrate 2 on both sides thereof.

  In the pMOSFET 20, an HfN layer 22 a, a metal layer such as Mo in which N is introduced (referred to as “N-doped metal layer”) 22 b, and a metal layer 22 c such as Mo are formed on the semiconductor substrate 2 via a gate insulating film 21. Has a metal gate electrode 22 having a three-layer structure in which are sequentially stacked. Sidewalls 23 are formed on the side walls of the metal gate electrode 22, and LDDs 24 a and source / drain regions 24 are formed in the semiconductor substrate 2 on both sides thereof.

  Here, in the nMOSFET 10, the two conductive layers of the HfN layer 12 a and the metal layer 12 b thereon function as a layer for controlling the work function of the metal gate electrode 12 (referred to as “work function control layer”). The uppermost metal layer 12c functions as a layer for reducing the resistance of the metal gate electrode 12 (referred to as “low resistance layer”). On the other hand, for the pMOSFET 20, the two conductive layers of the HfN layer 22 a and the N-doped metal layer 22 b thereon function as a work function control layer of the metal gate electrode 22, and the uppermost metal layer 22 c is the metal gate electrode 22. Functions as a low resistance layer.

  In such nMOSFET 10 and pMOSFET 20, the lowest HfN layers 12a and 22a of the metal gate electrodes 12 and 22 are configured to have different N concentrations. In the CMOSFET 1, the HfN layer 22 a of the pMOSFET 20 is formed to have a higher N concentration than the HfN layer 12 a of the nMOSFET 10. Here, as described later, the HfN layer 22a of the pMOSFET 20 has a higher N concentration than the HfN layer 12a of the nMOSFET 10 by diffusing N of the N-doped metal layer 22b, which is an upper layer, into the HfN layer 22a.

  In the CMOSFET 1, the work functions of the nMOSFET 10 and the pMOSFET 20 are controlled by making the N concentrations of the lowermost HfN layers 12 a and 22 a different from each other. Further, the middle metal layer 12b and the N-doped metal layer 22b of each metal gate electrode 12, 22 are layers that contribute indirectly to the work function control of both by adjusting the N concentration of both the HfN layers 12a, 22a. . That is, the middle metal layer 12b of the metal gate electrode 12 is a layer formed for the purpose of preventing the N concentration of the lower HfN layer 12a from increasing. On the other hand, the N-doped metal layer 22b in the middle layer of the metal gate electrode 22 is a layer formed for the purpose of increasing the N concentration by diffusing N contained therein into the lower HfN layer 22a. In order to adjust the N concentration of the HfN layer 12a of the metal gate electrode 12, the middle metal layer 12b can be an N-doped metal layer.

  By appropriately adjusting the N concentration of the HfN layers 12a and 22a, the work functions of the metal gate electrodes 12 and 22 of the nMOSFET 10 and the pMOSFET 20 can be optimally controlled. For example, the conventional polysilicon is formed by the nMOSFET 10 and the pMOSFET 20. A work function difference equivalent to that when the gate electrode is used can be obtained.

Here, FIG. 2 is a diagram showing an example of the relationship between the N concentration in the HfN layer and the work function. In FIG. 2, the horizontal axis represents the N concentration (cm ⁻³ ) in the HfN layer, and the vertical axis represents the work function (eV) of the HfN layer. FIG. 2 also shows the work function of the n-type polysilicon gate electrode and the work function of the p-type polysilicon gate electrode.

As shown in FIG. 2, the work function of the HfN layer tends to increase as the N concentration increases. In particular, the N concentration is between about 5 × 10 ²¹ cm ⁻³ and about 1 × 10 ²² cm ⁻³ . The work function changes greatly.

From FIG. 2, in CMOSFET 1, N having a concentration of about 5 × 10 ²¹ cm ⁻³ or less is contained in HfN layer 12 a of metal gate electrode 12 of nMOSFET 10, and a concentration of about 1 is contained in HfN layer 22 a of metal gate electrode 22 of pMOSFET 20. When N of 10 ²² cm ⁻³ or more is contained, the nMOSFET 10 and the pMOSFET 20 can obtain a work function difference equivalent to that when a polysilicon gate electrode is used.

  Further, in the CMOSFET 1, the metal layers 12 c and 22 c are provided on the uppermost layers of the metal gate electrodes 12 and 22 of the nMOSFET 10 and the pMOSFET 20, thereby reducing both resistances. For example, in the CMOSFET 1 having the configuration shown in FIG. 1, the metal layer 12b and the N-doped metal layer 22b are respectively formed on the HfN layers 12a and 22a without forming the metal layers 12c and 22c as the uppermost layer. Even in this case, the work function can be controlled by the HfN layers 12a and 22a, and the contact portion can be formed by the metal layer 12b and the N-doped metal layer 22b. However, in general, a metal in which N is introduced has a higher resistance than a metal in which N is not introduced, although it depends on the amount of N introduced. Therefore, as shown in FIG. 1, by providing low resistance metal layers 12c and 22c such as Mo on the uppermost layers of the metal gate electrodes 12 and 22 of the nMOSFET 10 and the pMOSFET 20, the work function is appropriately controlled in the lower layers. In addition, the resistance of the metal gate electrodes 12 and 22 can be further reduced.

  In the CMOSFET 1, the metal layer 12 b, 12 c, 22 c in the middle layer of the metal gate electrode 12 and the uppermost metal gate electrode 12, 22 includes refractory metals such as tungsten (W) and titanium (Ti) in addition to the above-described Mo. Alternatively, it is possible to use an intermetallic compound such as silicide.

  Further, in the N-doped metal layer 22b in the middle layer of the metal gate electrode 22 of the pMOSFET 20, in addition to N introduced into Mo, N introduced into a refractory metal such as W or Ti, or N introduced into silicide or the like It is also possible to use things. As described above, in order to adjust the N concentration of the HfN layer 12a in the lowest layer of the metal gate electrode 12 of the nMOSFET 10, the intermediate metal layer 12b is also an N-doped metal layer. Can be obtained by introducing N into Mo, W, Ti, silicide or the like.

  In addition, although the case where N is used for work function control is illustrated here, the same electron configuration of the outermost shell as N, such as phosphorus (P), arsenic (As), antimony (Sb), etc. It is possible to use.

The semiconductor substrate 2 can be a Si substrate or an SOI (Silicon On Insulator) substrate. In addition to silicon oxide (SiO ₂ ) and silicon oxynitride (SiON), the gate insulating films 11 and 21 have a high dielectric constant (hafnium oxide (HfO ₂ ), hafnium silicate (HfSiO), hafnium nitride silicate (HfSiON), etc. High-k) materials can also be used.

  In the above description, the case where the HfN layers 12a and 22a are used for a part (lower layer side) of the work function control layer has been described. Instead of the HfN layers 12a and 22a, an Hf layer not containing N is used. It is also possible. However, in this case, it should be noted that the Hf layer and the gate insulating films 11 and 21 may react depending on the material of the gate insulating films 11 and 21 and the thermal history of the CMOSFET 1 formation process. When the reaction between the Hf layer and the gate insulating films 11 and 21 does not occur or when there is no problem even if the reaction occurs, the Hf layer can be used as a part of the work function control layer. Examples of the Hf layer that does not react or hardly react with Hf include an insulating film containing N, such as a SiON film or a HfSiON film.

  In the above description, the case where HfN or Hf is used for a part (lower layer side) of the work function control layer has been described, but in addition to HfN and Hf, zirconium nitride (ZrN) or zirconium (Zr) is included in that part. Can also be used. Such ZrN and Zr also exhibit the same behavior as when HfN and Hf are used, and by using ZrN and Zr, it is possible to obtain the same effect as when HfN and Hf are used.

  In the above description, the case where the uppermost metal layers 12c and 22c are configured not to contain N has been described. However, when the uppermost layer is configured to contain N in advance, Even in the case of a structure containing N, a low-resistance metal gate electrode can be obtained if the uppermost layer has a lower resistance than the middle layer. When N is contained in the uppermost layer, the resistance is increased as compared with the case where N is not contained, but the oxidation resistance is improved.

Next, the CMOSFET as described above will be described more specifically.
FIG. 3 to FIG. 9 are explanatory views of each forming step of the CMOSFET. Hereinafter, with reference to FIGS. 3 to 9, a method of forming the CMOSFET and its configuration will be described in detail.

FIG. 3 is a schematic cross-sectional view of the relevant part in the process of forming the HfN layer and the Mo layer.
First, an element isolation region 31 is formed on the Si substrate 30 by using an STI (Shallow Trench Isolation) method or the like, and includes an nMOSFET formation region (nMOSFET formation region) 35 and a pMOSFET formation region (pMOSFET formation region) 36. A gate insulating film 32 having a thickness of about 2 nm is formed on the entire surface. For example, as the gate insulating film 32, a SiO ₂ film having a predetermined thickness is formed using a thermal oxidation method or the like.

After the gate insulating film 32 is formed, an HfN layer 33 having a film thickness of about 10 nm is formed thereon using a sputtering method or a CVD (Chemical Vapor Deposition) method. For example, in the case of sputtering, an Hf target is used, and an HfN layer 33 is used under the conditions of an argon (Ar) flow rate of about 28 mL / min, a nitrogen (N ₂ ) flow rate of about 2 mL / min, a power of about 250 W, and a pressure of about 0.2 Pa. Can be formed. The HfN layer 33 is formed to have an N concentration necessary for obtaining a work function of the metal gate electrode 12 of the nMOSFET 10, for example, about 5 × 10 ²¹ cm ⁻³ (see FIG. 2).

  After the HfN layer 33 is formed, a Mo layer 34 having a thickness of about 40 nm is formed thereon using a sputtering method or a CVD method. For example, in the case of sputtering, the Mo layer 34 can be formed using a Mo target under the conditions of an Ar flow rate of about 30 mL / min, a power of about 500 W, and a pressure of about 0.2 Pa. Even when W is used instead of Mo, the W layer can be formed under substantially the same sputtering conditions.

FIG. 4 is a schematic cross-sectional view of an essential part of the ion implantation process.
After the HfN layer 33 and the Mo layer 34 are formed, first, a resist 37 is formed in the nMOSFET formation region 35. Then, using the resist 37 as a mask, a predetermined amount of N is introduced into the Mo layer 34 in the pMOSFET formation region 36 using, for example, an ion implantation method. The ion implantation for introducing N is performed, for example, under conditions of an acceleration voltage of about 5 keV and a dose of about 1 × 10 ¹⁶ cm ⁻² , and a Mo layer 34 after ion implantation (an N-doped Mo layer 34a described later). The peak concentration is 1 × 10 ²² cm ⁻³ or more. By performing ion implantation under such a low acceleration voltage condition, a predetermined amount of N can be selectively introduced into the Mo layer 34 above the HfN layer 33 in the pMOSFET formation region 36. Since ion implantation is selectively performed on the Mo layer 34 in this way, damage to the interface between the Si substrate 30 and the gate insulating film 32 is effectively suppressed.

FIG. 5 is a schematic cross-sectional view of the relevant part showing a state after ion implantation.
By performing ion implantation under the above-mentioned predetermined conditions and removing the resist 37, as shown in FIG. 5, an N-doped Mo layer 34a in which a predetermined amount of N is introduced into the upper layer of the HfN layer 33 in the pMOSFET formation region 36. Is obtained.

  Here, the case where the N-doped Mo layer 34a is formed using the ion implantation method has been described. However, in order to introduce N into the Mo layer 34, a predetermined amount of N is selected as a region having a predetermined depth. Other introduction methods may be used as long as they can be introduced automatically. For example, a plasma doping method in which the Mo layer 34 is irradiated with N-containing plasma to introduce N, or a nitrogen compound (for example, an N-containing cluster) is adsorbed on the surface of the Mo layer 34 and diffused in a relatively shallow region. A method (referred to as “diffusion method”) or the like can also be used.

In the case of using the plasma doping method, the Mo layer 34 in the pMOSFET formation region 36 is processed using N ₂ as a gas raw material under conditions of an acceleration voltage of about 5 keV and a dose of about 1 × 10 ¹⁶ cm ⁻² . An N-doped Mo layer 34a is formed.

When the diffusion method is used, the Mo layer 34 in the MOSFET formation region 36 is exposed to N ₂ plasma under conditions of RF power of about 50 W, pressure of about 0.2 Torr (1 Torr = 133.32 Pa), and time of about 5 seconds. , N is adsorbed on the surface. Then, by diffusing it into the Mo layer 34, an N-doped Mo layer 34a is formed.

FIG. 6 is a schematic cross-sectional view of the relevant part in the process of forming the Mo layer.
After the N-doped Mo layer 34a is formed in the pMOSFET formation region 36, the film thickness is formed on the N-doped Mo layer 34a in the pMOSFET formation region 36 and the Mo layer 34 remaining in the nMOSFET formation region 35 by sputtering or CVD. A Mo layer 38 of about 20 nm is formed. For example, in the case of sputtering, the Mo layer 38 can be formed using a Mo target under the conditions of an Ar flow rate of about 30 mL / min, a power of about 500 W, and a pressure of about 0.2 Pa.

  Here, a molybdenum nitride (MoN) layer can be formed instead of the Mo layer 38. However, since the Mo layer 38 functions as a low resistance layer as will be described later, when a MoN layer is formed instead of the Mo layer 38, it is desirable to have a very small N content. Although the MoN layer has a higher resistance than the Mo layer 38, it is advantageous in terms of oxidation resistance.

FIG. 7 is a schematic cross-sectional view of an essential part of the gate processing and impurity introduction process.
After the stacked structure as shown in FIG. 6 is formed in the nMOSFET formation region 35 and the pMOSFET formation region 36, gate processing is performed using a photolithography technique according to a conventional method. By this gate processing, a gate pattern having a three-layer structure of the HfN layer 33 and the Mo layers 34 and 38 is formed in the nMOSFET formation region 35. At the same time, the HfN layer 33 and the N-doped Mo layer 34a are formed in the pMOSFET formation region 36. And the gate pattern of the 3 layer structure of Mo layer 38 is formed.

Next, a low-concentration impurity region to be an LDD (Lightly Doped Drain) is formed by introducing an impurity into the surface of the silicon substrate 30 at a low concentration using the three-layer gate pattern as a mask.
FIG. 8 is a schematic cross-sectional view of an essential part of the sidewall formation and impurity introduction process.

  Next, a silicon oxide film is formed on the entire upper surface of the silicon substrate 30, and this silicon oxide film is etched back. As shown in FIG. 8, the HfN layer 33, the Mo layers 34, 34a and 38, and the gate insulating film 32 are formed. A side wall 39 is formed to cover the side surfaces of the first side. Then, using the HfN layer 33, the Mo layers 34, 34a and 38 and the sidewall 39 as a mask, impurities are introduced into the surface of the silicon substrate 30 at a high concentration to form a high concentration impurity region.

FIG. 9 is a schematic cross-sectional view of the relevant part in the source / drain region forming step.
After the formation of the sidewall 39, in order to activate the impurities introduced into the Si substrate 30, for example, an RTA (Rapid Thermal Anneal) process is performed in an inert gas atmosphere at about 1000 ° C. for about 5 seconds. Thus, LDDs 40a and 41a and source / drain regions 40 and 41 are formed in the Si substrate 30 on both sides of the gate patterns of the nMOSFET formation region 35 and the pMOSFET formation region 36, respectively.

Further, during this RTA process, N diffusion occurs from the N-doped Mo layer 34a in the pMOSFET formation region 36 shown in FIG. 8 to the lower HfN layer 33, and as shown in FIG. The changed N-doped Mo layer 34b and HfN layer 33a are obtained. Thus, HfN layers 33 and 33a having different N concentrations can be obtained in the nMOSFET formation region 35 and the pMOSFET formation region 36. At this time, for example, if the N concentration of the HfN layer 33a in the pMOSFET formation region 35 is about 1 × 10 ²² cm ⁻³ or more, the N concentration of the HfN layer 33 in the nMOSFET formation region 35 is about 5 × 10 ^21. When cm ⁻³ , it becomes possible to obtain a significant work function difference between the two (see FIG. 2). Therefore, the N concentration of the HfN layer 33 before the RTA treatment, the N concentration of the N-doped Mo layer 34a (the Mo layer 34) so that such a significant work function difference can be obtained after performing the RTA treatment for impurity activation. N introduction amount), RTA processing conditions, etc. are appropriately set and controlled.

  Through the above steps, an nMOSFET having a metal gate electrode 42 composed of an HfN layer 33 and Mo layers 34, 38 is formed in the nMOSFET formation region 35, and an HfN layer 33a, an N-doped Mo layer 34b, and an Mo layer are formed in the pMOSFET formation region 36. A pMOSFET having a metal gate electrode 43 made of 38 is formed. In this case, in the metal gate electrode 42, the lowermost HfN layer 33 and the middle Mo layer 34 are work function control layers, and the uppermost Mo layer 38 is a low resistance layer. In the metal gate electrode 43, the lowermost HfN layer 33a and the middle N-doped Mo layer 34b serve as a work function control layer, and the uppermost Mo layer 38 serves as a low resistance layer.

  By such a forming method, a high-performance CMOSFET including low-resistance metal gate electrodes 42 and 43 whose work functions are appropriately controlled can be formed. Further, according to this forming method, the metal gate electrodes 42 and 43 can be formed simultaneously in the nMOSFET forming region 35 and the pMOSFET forming region 36, and the process is almost the same as that of a conventional CMOSFET having a polysilicon gate electrode. It can be formed in a process. Therefore, such a high-performance CMOSFET can be efficiently formed without complicating the process.

  In the above formation method, attention is also paid to the diffusion of N into the uppermost Mo layer 38 during the RTA process described in FIG. 9 (not shown). This is because when N is finally contained in the uppermost layer, the resistance tends to increase as compared with the case where N is not contained. Therefore, the N concentration of the HfN layer 33 before the RTA treatment, the N concentration of the N-doped Mo layer 34a (the amount of N introduced into the Mo layer 34), the RTA treatment conditions, etc. so that such resistance increase is within an allowable range. Is set and controlled appropriately. Further, in order to improve the oxidation resistance of the uppermost layer, it is possible to intentionally diffuse N into the uppermost layer within a range in which the above increase in resistance can be allowed. Also in this case, the N concentration of the HfN layer 33 before the RTA treatment, the N concentration of the N-doped Mo layer 34a (the amount of N introduced into the Mo layer 34), and the RTA treatment conditions so that the uppermost layer has a predetermined N content Etc. may be appropriately set and controlled.

Further, the formation conditions of the CMOSFET in the above description are merely examples, and can be arbitrarily changed according to the required characteristics of the CMOSFET to be formed.
As described above, here, each of the nMOSFETs of the CMOSFET and each metal gate electrode of the pMOSFET has a three-layer structure, and the work function control layer is formed by the lowermost layer and the middle conductive layer, and the lowermost layer is the lower resistance layer. Was configured.

  The lowermost conductive layer of each metal gate electrode of nMOSFET and pMOSFET controls the work function of each metal gate electrode optimally by appropriately adjusting the N concentration by nMOSFET and pMOSFET.

  The middle layer of the metal gate electrode of the pMOSFET is composed of a conductive layer containing N, and is used to adjust the N concentration of the conductive layer by diffusing the N into the lowermost conductive layer when the metal gate electrode is formed. It contributes indirectly to the work function control of the metal gate electrode. As described above, the middle layer of the metal gate electrode of the nMOSFET is also composed of a conductive layer containing N, and when the metal gate electrode is formed, the N is diffused into the lowermost conductive layer, so that the N concentration of the conductive layer is increased. You may make it use for adjustment. Even in this case, if the final N concentration of the lowermost conductive layer of each metal gate electrode of nMOSFET and pMOSFET is adjusted appropriately, the work function of each metal gate electrode can be optimally controlled.

  Further, the uppermost layer of each metal gate electrode of the nMOSFET and the pMOSFET is low enough to secure a low contact resistance of the metal gate electrode even when N is introduced into the middle conductive layer and its resistance is increased. It is composed of a resistance layer, for example, a metal layer that does not contain N or contains a trace amount of N. This makes it possible to reduce the resistance of both the nMOSFET and the pMOSFET.

  Further, the CMOSFET provided with the metal gate electrode as described above can be formed in almost the same process as the conventional CMOSFET provided with the polysilicon gate electrode. Therefore, a CMOSFET having a significant work function and having a low-resistance metal gate electrode can be efficiently formed without complicating the process.

(Supplementary Note 1) In a complementary semiconductor device including a metal gate electrode,
A work function control layer having a structure in which conductive layers are stacked and having different N concentrations in the nMOSFET and the pMOSFET,
A low resistance layer formed on the work function control layer to lower the resistance of the work function control layer;
A semiconductor device comprising a metal gate electrode having

  (Supplementary Note 2) Of the conductive layers stacked with the work function control layer, the lower conductive layer is a layer having a predetermined N concentration and a predetermined work function, and the upper conductive layer is the lower layer. The semiconductor device according to appendix 1, wherein the semiconductor device is a layer for adjusting the N concentration of the side conductive layer.

  (Supplementary Note 3) When the upper conductive layer contains N, the upper conductive layer is used for diffusing the contained N into the lower conductive layer to increase the N concentration of the lower conductive layer. The semiconductor device according to appendix 2.

(Additional remark 4) The said upper layer side conductive layer is used in order to maintain N density | concentration of the said lower layer side conductive layer, The semiconductor device of Additional remark 2 characterized by the above-mentioned.
(Appendix 5) The lower conductive layer and the upper conductive layer of the conductive layer on which the work function control layer is stacked have a higher N concentration on the pMOSFET side than on the nMOSFET side. Semiconductor device.

(Supplementary note 6) The semiconductor device according to supplementary note 1, wherein among the conductive layers on which the work function control layer is stacked, a lower conductive layer is HfN, Hf, ZrN, or Zr.
(Supplementary note 7) The semiconductor according to supplementary note 1, wherein among the conductive layers on which the work function control layer is laminated, the upper conductive layer is formed using a metal having a high melting point or an intermetallic compound. apparatus.

(Supplementary note 8) The semiconductor device according to supplementary note 1, wherein the low-resistance layer is formed using a metal or an intermetallic compound having a low resistance and a high melting point.
(Additional remark 9) In the manufacturing method of a complementary semiconductor device provided with a metal gate electrode,
forming a gate insulating film on the semiconductor layers of the nMOSFET formation region and the pMOSFET formation region;
Laminating a conductive layer on the formed gate insulating film;
Introducing N so that N concentration is different between the nMOSFET formation region and the pMOSFET formation region with respect to the upper conductive layer among the stacked conductive layers;
Forming a low-resistance layer on the upper conductive layer of the nMOSFET formation region and the pMOSFET formation region after introducing N;
A step of performing a heat treatment for diffusing N from the upper conductive layer to the lower conductive layer of the conductive layer after forming the low resistance layer;
A method for manufacturing a semiconductor device, comprising:

(Supplementary Note 10) After the step of forming the low resistance layer on the upper conductive layer of the nMOSFET formation region and the pMOSFET formation region,
Applying gate processing to the laminated conductive layer and the low-resistance layer;
Introducing an impurity of a predetermined conductivity type into the semiconductor layer after the gate processing;
Have
In the step of performing the heat treatment for diffusing N from the upper conductive layer to the lower conductive layer,
10. The method of manufacturing a semiconductor device according to appendix 9, wherein the heat treatment diffuses N from the upper conductive layer to the lower conductive layer and activates the impurities introduced into the semiconductor layer.

(Supplementary Note 11) In the step of performing the gate processing on the conductive layer and the low resistance layer that are stacked,
11. The method of manufacturing a semiconductor device according to appendix 10, wherein the gate processing is performed simultaneously on the nMOSFET formation region and the pMOSFET formation region.

(Supplementary Note 12) In the step of laminating the conductive layer on the gate insulating film,
The lower conductive layer in the nMOSFET formation region and the pMOSFET formation region is formed at an N concentration showing a work function suitable for an nMOSFET, and the upper conductive layer is formed on the lower conductive layer without introducing N And
In the step of introducing N such that the N concentration is different between the nMOSFET formation region and the pMOSFET formation region with respect to the upper conductive layer,
When N is introduced only into the upper conductive layer in the pMOSFET formation region and the heat treatment is performed later, the lower conductive layer in the pMOSFET formation region exhibits a work function suitable for pMOSFET. Introducing N so that
Item 9. The supplementary note 9, wherein after introducing N, the low resistance layer is formed on the upper conductive layer in the nMOSFET formation region and the pMOSFET formation region, and the heat treatment is performed after the formation of the low resistance layer. A method for manufacturing a semiconductor device.

(Additional remark 13) The said lower layer side conductive layer is HfN, Hf, ZrN, or Zr, The manufacturing method of the semiconductor device of Additional remark 9 characterized by the above-mentioned.
(Additional remark 14) The said upper layer side conductive layer is formed using a high melting metal or an intermetallic compound, The manufacturing method of the semiconductor device of Additional remark 9 characterized by the above-mentioned.

  (Supplementary note 15) The method for manufacturing a semiconductor device according to supplementary note 9, wherein the low-resistance layer is formed using a metal or an intermetallic compound having a low resistance and a high melting point.

It is a figure which shows the structural example of CMOSFET provided with the metal gate electrode. It is a figure which shows an example of the relationship between N density | concentration in a HfN layer, and a work function. It is a principal part cross-sectional schematic diagram of the formation process of a HfN layer and Mo layer. It is a principal part cross-sectional schematic diagram of an ion implantation process. It is a principal part cross-sectional schematic diagram which shows the state after ion implantation. It is a principal part cross-sectional schematic diagram of the formation process of Mo layer. It is a principal part cross-sectional schematic diagram of a gate process and an impurity introduction | transduction process. It is a principal part cross-sectional schematic diagram of sidewall formation and an impurity introduction | transduction process. It is a principal part cross-sectional schematic diagram of the formation process of a source / drain area | region.

Explanation of symbols

1 CMOSFET
2 Semiconductor substrate 3,31 Element isolation region 10 nMOSFET
11, 21, 32 Gate insulating film 12, 22, 42, 43 Metal gate electrode 12a, 22a, 33, 33a HfN layer 12b, 12c, 22c Metal layer 13, 23, 39 Side wall 14, 24, 40, 41 Source / Drain regions 14a, 24a, 40a, 41a LDD
20 pMOSFET
22b N-doped metal layer 30 Si substrate 34, 38 Mo layer 34a, 34b N-doped Mo layer 35 nMOSFET formation region 36 pMOSFET formation region 37 resist

Claims (2)

  In a method for manufacturing a complementary semiconductor device including a metal gate electrode,
  forming a gate insulating film on the semiconductor layers of the nMOSFET formation region and the pMOSFET formation region;
  Forming a lower conductive layer on the formed gate insulating film;
  Forming an upper conductive layer on the lower conductive layer formed;
  Introducing nitrogen such that the nMOSFET forming region and the pMOSFET forming region have different nitrogen concentrations with respect to the formed upper conductive layer;
  Forming a low resistance layer on the upper conductive layer of the nMOSFET formation region and the pMOSFET formation region after introducing nitrogen;
  A step of performing a heat treatment for diffusing nitrogen from the upper conductive layer to the lower conductive layer after forming the low resistance layer;
  Have
  In the step of forming the lower conductive layer, a hafnium nitride layer or a zirconium nitride layer having a nitrogen concentration exhibiting a work function suitable for an nMOSFET is formed on the gate insulating film, and the nMOSFET forming region and the pMOSFET forming region are Deposited as a lower conductive layer,
  In the step of forming the upper conductive layer, a molybdenum layer is deposited as the upper conductive layer on the lower conductive layer without introducing nitrogen,
  In the step of introducing nitrogen so that the nitrogen concentration is different between the nMOSFET formation region and the pMOSFET formation region with respect to the upper layer side conductive layer, the heat treatment is performed later only on the upper layer side conductive layer in the pMOSFET formation region. Nitrogen is introduced so that the lower conductive layer in the pMOSFET formation region has a nitrogen concentration exhibiting a work function suitable for the pMOSFET when performed,
  After introducing nitrogen, a molybdenum layer is deposited as the low resistance layer on the upper conductive layer in the nMOSFET formation region and the pMOSFET formation region, and the heat treatment is performed after the formation of the low resistance layer. Device manufacturing method.   After the step of forming the low resistance layer on the upper conductive layer of the nMOSFET formation region and the pMOSFET formation region,
  A step of performing gate processing on the formed lower conductive layer, the upper conductive layer, and the low resistance layer;
  Introducing an impurity of a predetermined conductivity type into the semiconductor layer after the gate processing;
  Have
  2. The heat treatment includes diffusing nitrogen from the upper conductive layer to the lower conductive layer and activating the impurities introduced into the semiconductor layer by the heat treatment. The manufacturing method of the semiconductor device of description.

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