JP3918218B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a semiconductor device.ofThe present invention relates to a manufacturing method, and more particularly, to a MIS (Metal Insulator Semiconductor) transistor and a manufacturing method thereof.
[0002]
[Prior art]
  With the recent miniaturization and speeding up of elements, a salicide (Self Aligned Silicide) technique for forming a refractory metal silicide in a self-aligning manner has been widely proposed as a means for reducing parasitic resistance and has already been commercialized. In addition, due to the demand for low power consumption of elements, a dual gate structure having both N-type and P-type gate electrodes is required.
[0003]
  Hereinafter, a method for manufacturing a C-MOS transistor having a dual gate structure using the conventional salicide technique will be described with reference to process cross-sectional views of FIGS.
  First, after an element isolation oxide film 52 is formed on a Si (silicon) substrate 51 in an element isolation region, among the element regions isolated by the element isolation oxide film 52, a region for forming an NMOS transistor (hereinafter, referred to as an NMOS transistor). A P-type well 53 is formed on the surface of the Si substrate 51 in the “NMOS region”, and an N-type well is formed on the surface of the Si substrate 51 in the region for forming the PMOS transistor (hereinafter referred to as “PMOS region”). 54 is formed. Subsequently, a gate electrode 56 made of a polycrystalline silicon film is formed on the P-type well 53 and the N-type well 54 with a gate oxide film 55 interposed therebetween (see FIG. 35).
[0004]
  Next, after covering the PMOS region with a resist (not shown), N-type impurity ions are formed on the surface of the P-type well 53 in the NMOS region using the resist, the element isolation oxide film 52, and the gate electrode 56 in the NMOS region as a mask. Is selectively implanted to form a low concentration N of LDD (Lightly Doped Drain) structure.^-Impurity regions (not shown) are formed. Similarly, P-type impurity ions are selectively ion-implanted into the surface of the N-type well 54 in the PMOS region to form a low-concentration P having an LDD structure.^-Impurity regions (not shown) are formed. Thereafter, a gate sidewall 57 made of an insulating film is formed on each side surface of the gate electrode 56 in the NMOS region and the PMOS region, and a silicon oxide film 58 as a sacrificial oxide film is deposited on the entire surface of the substrate.
[0005]
  Subsequently, after covering the PMOS region with a resist 59, the resist 59, the element isolation oxide film 52, the gate electrode 56 in the NMOS region, and the gate sidewall 57 on the side surface of the gate electrode 56 are used as masks. As an N-type impurity ion on the surface of the mold well 53, for example, As⁺(Arsenic ions) are selectively implanted. Thus, N^-High-concentration N constituting the source / drain of the LDD structure integrated with the impurity region⁺Impurity regions 60a and 60b are formed. At this time, the gate electrode 56 in the NMOS region also becomes As.⁺Is ion-implanted, the gate electrode 56 becomes an N-type gate electrode 56a (see FIG. 36).
[0006]
  Next, after removing the resist 59 and covering the NMOS region with the resist 61, the resist 61, the element isolation oxide film 52, the gate electrode 56 in the PMOS region, and the gate sidewall 57 on the side surface of the gate electrode 56 are used as a mask. As a P-type impurity ion on the surface of the N-type well 54 in the PMOS region, for example, BF₂ ⁺(Boron fluoride ion) is selectively ion-implanted. Thus, P^-High concentration of P that constitutes the source / drain of the LDD structure integrally with the impurity region⁺Impurity regions 62a and 62b are formed. At this time, the BF is also applied to the gate electrode 56 in the PMOS region.₂ ⁺Is ion-implanted, the gate electrode 56b becomes a P-type gate electrode 56b (see FIG. 37).
[0007]
  Next, after removing the resist 61, heat treatment is performed, and N^-Impurity region and N⁺Impurity regions 60a, 60b, P^-Impurity region and P⁺The impurity ions implanted into the impurity regions 62a and 62b and the N-type and P-type gate electrodes 56a and 56b are activated.
  Subsequently, after removing the silicon oxide film 58, for example, a Ti (titanium) film 63 is formed as a refractory metal film on the entire surface of the substrate (see FIG. 38).
[0008]
  Then, using a two-step annealing method, N⁺Impurity regions 60a, 60b and P⁺The Ti film 63 deposited on the impurity regions 62a and 62b and the N-type and P-type gate electrodes 56a and 56b is silicided.
  That is, by the first heat treatment, N⁺Impurity regions 60a, 60b and P⁺The Ti film 63 on the impurity regions 62a and 62b is silicided to form C49 phase TiSi.₂A (titanium silicide) film 63a is formed. At the same time, the Ti film 63 on the N-type and P-type gate electrodes 56a and 56b is silicided to form C49-phase TiSi.₂A film 63b is formed. At this time, the Ti film 63 on the element isolation oxide film 52 and the gate side wall 57 remains as a Ti film 63 without reacting with the base film, but the unreacted Ti film 63 is made of ammonia overwater or the like. Selectively remove. Then, by the second heat treatment, C49 phase TiSi₂The films 63a and 63b are made of relatively low-resistance C54 phase TiSi.₂Phase transition is performed on the films 63a and 63b. Thus, N⁺Impurity regions 60a, 60b and P⁺C54 phase TiSi on the impurity regions 62a and 62b₂The film 63a is formed on the N-type and P-type gate electrodes 56a and 56b with C54 phase TiSi.₂The films 63b are formed in a self-aligned manner.
[0009]
  Next, an interlayer insulating film 64 is formed on the entire surface of the substrate. Thereafter, the interlayer insulating film 64 is coated with N⁺Impurity regions 60a, 60b and P⁺TiSi on impurity regions 62a and 62b₂TiSi on film 63a and N-type and P-type gate electrodes 56a, 56b₂A connection hole reaching the film 63b is opened. Subsequently, after filling these connection holes with, for example, W (tungsten) plugs 65 and further forming wiring layers 66 connected to these W plugs 65, a surface protective film 67 is formed on the entire surface of the substrate (FIG. 39). reference). In this way, a dual gate C-MOS transistor is manufactured.
[0010]
[Problems to be solved by the invention]
  However, when a dual-gate C-MOS transistor is manufactured using the conventional salicide technique, several problems occur.
  For example, with the miniaturization of elements, N constituting source / drain⁺When the width of the impurity regions 60a and 60b is narrowed, TiSi₂N including membrane 63a⁺The sheet resistance of the impurity regions 60a and 60b is increased. That is, N⁺TiSi formed on impurity regions 60a and 60b₂There is a problem that the sheet resistance of the film 63a depends on the line width, that is, a so-called thin line effect occurs.
[0011]
  In order to suppress this fine line effect, N⁺Impurity regions 60a, 60b, P⁺An amorphous layer is formed on the surfaces of the impurity regions 62a and 62b and the N-type and P-type gate electrodes 56a and 56b to accelerate the silicidation reaction, and further heat treatment is performed between the two-stage heat treatments for silicidation. Is proposed (see Japanese Patent Laid-Open No. 5-291180). However, in this case, TiSi₂Films 63a and 63b are N⁺Impurity regions 60a, 60b and P⁺Grows so as to protrude from the impurity regions 62a and 62b and the N-type and P-type gate electrodes 56a and 56b to the element isolation oxide film 52 and the gate sidewall 57, and N⁺TiSi on impurity regions 60a and 60b₂TiSi on film 63a and N-type gate electrode 56a₂The film 63b is short-circuited, and P⁺TiSi on impurity regions 62a and 62b₂TiSi on film 63a and P-type gate electrode 56b₂There is a possibility that the film 63b may be short-circuited, and there is a problem that transistor characteristics are deteriorated.
[0012]
  Further, As as N-type impurity ions is formed on the surface of the P-type well 53 in the NMOS region.⁺N to form source / drain by ion implantation⁺When forming the impurity regions 60a and 60b, this As⁺Range is BF₂ ⁺The diffusion coefficient of As (arsenic) as an N-type impurity is smaller than that of B (boron) as a P-type impurity.⁺The junction depth of the impurity regions 60a and 60b becomes shallow. For this reason, N⁺TiSi on impurity regions 60a and 60b₂When forming the film 63a, alloy spikes are easily generated, and N⁺There is a problem that the junction leak in the impurity regions 60a and 60b is likely to occur and the reliability is lowered.
[0013]
  Also, N with a shallow junction depth⁺It is difficult to reduce the impurity concentration of the impurity regions 60 a and 60 b on the surface, and further, the As oxide through the silicon oxide film 58.⁺O (oxygen) atoms are mixed into the Si substrate 50 by a knock-on effect caused by ion implantation. For this reason, N⁺The silicidation reaction of the Ti film 63 deposited on the impurity regions 60a and 60b is suppressed, and it becomes difficult to sufficiently reduce the sheet resistance, and there is a problem that transistor characteristics deteriorate.
[0014]
  Therefore, the present invention has been made in view of the above problems, and can suppress the thin line effect in the dual gate semiconductor device using the salicide technology and prevent deterioration in transistor characteristics and reliability. Semiconductor deviceofAn object is to provide a manufacturing method.
[0015]
[Means for Solving the Problems]
  In order to solve the above problems, the present inventor has already proposed a “method for manufacturing a semiconductor device” of Japanese Patent Application No. 8-75217. In Japanese Patent Application No. 8-75217, N constituting a source / drain is disclosed.⁺Impurity region and P⁺When ion implantation is performed on the surface of the impurity region and the N-type and P-type gate electrodes to form an amorphous layer, the ion implantation is performed with the sacrificial oxide film and the natural oxide film removed from these surfaces. It is said.
[0016]
  As a result, the silicidation reaction can be prevented from being suppressed by the knocked-on O atoms, and a sufficiently thick amorphous layer is formed to promote the silicidation reaction.⁺Impurity region and P⁺The fine line effect in the impurity region can be suppressed. Further, since a heat treatment added in the middle of the two-step heat treatment of the two-step annealing method for silicidation is not necessary, TiSi by this additional heat treatment₂There is no risk of a short circuit due to the protruding growth of the film, and deterioration of transistor characteristics can be prevented.
[0017]
  In this way, N on the surface of the Si substrate⁺Impurity region and P⁺TiSi on the impurity region₂TiSi with sufficiently low resistance when the film is formed in a self-aligned manner₂A film can be obtained and the thin line effect can be suppressed.
[0018]
  However, according to the inventors' subsequent experiments, the refractory metal silicide film formed on the gate electrode, particularly As⁺The refractory metal silicide film formed on the N-type gate electrode implanted with a high concentration of ion has a line width dependency that tends to increase the sheet resistance in a thin line region having a gate width of 0.3 μm or less. I found Therefore, a new problem has arisen about how to suppress the thin line effect of the refractory metal silicide film formed on the gate electrode, particularly the N-type gate electrode.
[0019]
  As a result of various studies on this new problem, the present inventor has conceived that an amorphous silicon film is used in place of the conventional polycrystalline silicon film as the material of the gate electrode. In the conventional manufacturing method, an amorphous silicon film is used in place of the polycrystalline silicon film, and a refractory metal silicide film is formed on the gate electrode made of the amorphous silicon film. It was confirmed that a refractory metal silicide film can be obtained and the thin line effect is suppressed.
[0020]
  However, in the case of the gate electrode made of this amorphous silicon film, it has become clear that so-called depletion of the gate electrode occurs remarkably instead of being able to suppress the thin line effect. That is, a predetermined applied voltage V_CCQuantum mechanical effect of gate capacitance C (Quantumn Gate effect capacitance C considering mechanical effect_OXRatio to C / C_OXIn the case of the conventional gate electrode made of a polycrystalline silicon film, it was 90% or more, and in the case of a gate electrode made of an amorphous silicon film, it was 90% or less. This tendency is more remarkable in the N-type gate electrode than in the P-type gate electrode.
[0021]
  The cause of such depletion of the gate electrode, particularly the remarkable depletion of the N-type gate electrode, is considered as follows. That is, for example, As⁺As this ion is implanted⁺Is relatively small, and the diffusion coefficient of As is relatively small. Therefore, As does not sufficiently diffuse throughout the gate electrode, and in the case of a polycrystalline silicon film, As⁺Is deeply implanted along the crystal grains, but in the case of an amorphous silicon film, As⁺Is implanted only in a shallow region as compared to polycrystalline silicon, and therefore, only the vicinity of the surface of the gate electrode is a desired high-concentration N-type region. Conceivable.
[0022]
  As a means for suppressing such depletion of the gate electrode, after implanting P-type and N-type impurity ions into the gate electrode, the heat treatment for activating it is heated to a high temperature for a long time to sufficiently diffuse the impurity. It is possible. However, in this case, in the PMOS transistor using B having a large diffusion coefficient as a P-type impurity, there is a problem that transistor characteristics are deteriorated due to punch through due to impurity diffusion.
[0023]
  Further, as another means for suppressing the depletion of the gate electrode, it is conceivable to reduce the thickness of the gate electrode. However, in this case, when the refractory metal silicide film is formed on the gate electrode, there arises a problem that the breakdown voltage of the gate oxide film deteriorates due to partial overgrowth (penetration) of the refractory metal silicide film. In order to suppress the breakdown voltage degradation of the gate oxide film, the thickness of the gate electrode is required to be 150 nm or more. However, at this thickness, the gate electrode is significantly depleted, and deterioration of the transistor characteristics is inevitable. There is a problem.
[0024]
  As described above, in order to suppress the thin line effect of the refractory metal silicide film formed on the gate electrode, even if an amorphous silicon film is used instead of the conventional polycrystalline silicon film as the material of the gate electrode, If the conventional manufacturing method is used as it is, new problems such as depletion of the gate electrode occur.
[0025]
  Therefore, the present inventor, in addition to suppressing the thin line effect of the refractory metal silicide film formed on the gate electrode, when using an amorphous silicon film instead of the conventional polycrystalline silicon film as the material of the gate electrode, Thus, a manufacturing method capable of suppressing depletion of the gate electrode, ensuring a gate breakdown voltage, and preventing deterioration of transistor characteristics was studied. Also, a composite gate electrode capable of utilizing the mutual advantages of an amorphous silicon film capable of suppressing the thin line effect and a polycrystalline silicon film capable of suppressing depletion of the gate electrode The structure was examined. As a result of such examination, the present inventor has made the following semiconductor device according to the present invention.ofI came up with a manufacturing method.
0026]
  Claim1A method of manufacturing a semiconductor device according to the present invention includes a polycrystalline silicon film on a semiconductor substrate via a gate insulating filmFormingAfterA step of implanting predetermined impurity ions into the polycrystalline silicon film, and after forming an amorphous silicon film on the polycrystalline silicon film,The amorphous silicon film and the polycrystalline silicon film are patterned into a predetermined shape to form a gate electrode having a two-layer structure of a lower polycrystalline silicon film and an upper amorphous silicon film. A second step of adding a predetermined impurity to the surface of the semiconductor substrate and the gate electrode to form an impurity region and making the gate electrode conductive, and depositing a refractory metal film on the entire surface of the substrate, followed by heat treatment To silicidize the refractory metal film on the impurity region and on the gate electrode and etch away the unreacted refractory metal film to form a refractory metal silicide film on the impurity region and on the gate electrode in a self-aligned manner. And a third step.
0027]
  Thus claims1In the method of manufacturing a semiconductor device according to the above, by forming a gate electrode having a two-layer structure of a lower polycrystalline silicon film and an upper amorphous silicon film, impurity ions are deepened along the crystal grains. Since the polycrystalline silicon film having the property of being implanted to the bottom constitutes the lower layer of the gate electrode, impurities can be diffused uniformly throughout the gate electrode, and depletion of the gate electrode can be suppressed. In addition, when a refractory metal silicide film is formed on the gate electrode in a self-aligned manner, the refractory metal film is directly deposited on the amorphous silicon film constituting the upper layer of the gate electrode and silicided by heat treatment. Therefore, this silicidation reaction is promoted to realize a sufficiently low resistance, and the thin line effect of the refractory metal silicide film formed on the gate electrode can be suppressed.
0028]
  In this way, the advantage of the polycrystalline silicon film that can suppress the depletion of the gate electrode and the advantage of the amorphous silicon film that can suppress the thin line effect of the refractory metal silicide film are utilized. Therefore, the thin line effect of the refractory metal silicide film formed on the gate electrode and the depletion of the gate electrode can be suppressed at the same time.
  In addition, since it is not necessary to reduce the thickness of the gate electrode more than necessary in order to suppress the depletion of the gate electrode, a part of the refractory metal silicide film is formed when the refractory metal silicide film is formed on the gate electrode. The breakdown voltage of the gate oxide film due to excessive overgrowth (penetration) can be prevented. Furthermore, since it is not necessary to perform high-temperature and long-time heat treatment at the time of impurity ion activation in order to suppress depletion of the gate electrode, punch-through and short-channel effects due to diffusion of impurities with a large diffusion coefficient particularly in PMOS transistors Can be prevented, and deterioration of transistor characteristics can be prevented.
0029]
  Also,semiconductorAfter forming a polycrystalline silicon film on the substrate via a gate insulating film, a step of implanting predetermined impurity ions into the polycrystalline silicon film, and after forming an amorphous silicon film on the polycrystalline silicon film, Patterning these amorphous silicon film and polycrystalline silicon film into a predetermined shape, and forming a gate electrode having a two-layer structure of a lower polycrystalline silicon film and an upper amorphous silicon film; To have a configuration comprisingFromBefore adding a predetermined impurity to the gate electrode of the two-layer film structure, a predetermined impurity ion is implanted in advance into the polycrystalline silicon film constituting the lower layer of the gate electrode that tends to have a low impurity concentration. Thus, the impurity concentration of the entire gate electrode can be made uniform, and depletion of the gate electrode can be more effectively suppressed.
0030]
  Claims2According to the method for manufacturing a semiconductor device, a polycrystalline silicon film is formed on a semiconductor substrate in first and second element regions via a gate insulating film.FormingAfterIn the first element region Selectively implanting first conductivity type impurity ions into the polycrystalline silicon film; and forming an amorphous silicon film on the polycrystalline silicon film;These amorphous silicon film and polycrystalline silicon film are patterned into a predetermined shape to form first and second gates having a two-layer structure of a lower polycrystalline silicon film and an upper amorphous silicon film. A first step of forming electrodes in the first and second element regions, respectively, and a first conductivity type impurity ion is selectively implanted into the surface of the semiconductor substrate and the first gate electrode in the first element region; After selectively implanting impurity ions of the second conductivity type into the surface of the semiconductor substrate and the second gate electrode in the second element region, the impurity ions are activated by heat treatment, and are respectively applied to the first and second element regions. First impurity type and second conductivity type impurity regions are formed, and first and second gate electrodes are formed as first conductivity type and second conductivity type gate electrodes, respectively.2And after the refractory metal film is deposited on the entire surface of the substrate, the refractory metal film on the first conductivity type and second conductivity type impurity regions and on the first conductivity type and second conductivity type gate electrodes by heat treatment. And the unreacted refractory metal film is removed by etching, and the refractory metal is formed on the first conductivity type and second conductivity type impurity regions and on the first conductivity type and second conductivity type gate electrodes. First, the silicide film is formed in a self-aligned manner.3The process is comprised.
0031]
  Thus claims2In the method of manufacturing a semiconductor device according to the first aspect, first and second conductivity type impurity regions are formed in the first and second element regions, and the lower polycrystalline silicon film and the upper amorphous silicon film are formed. Forming a first conductive type and a second conductive type gate electrode having a two-layer structure, and on the first conductive type and second conductive type impurity regions and the first conductive type and second conductive type gates. By forming a refractory metal silicide film on the electrode in a self-aligning manner, it is possible to suppress depletion of the gate electrode even in a so-called dual gate structure having both N-type and P-type gate electrodes. By utilizing the advantages of the crystalline silicon film and the amorphous silicon film capable of suppressing the thin line effect of the refractory metal silicide film, the thin line effect and gate of the refractory metal silicide film formed on the gate electrode are utilized. Since it is possible to simultaneously suppress the poles of depletion, it is possible to contribute miniaturization of elements of the dual-gate structure, the high speed.
0032]
  In addition, after a polycrystalline silicon film is formed on the semiconductor substrate in the first and second element regions via a gate insulating film, the first conductivity type impurity ions are selected in the polycrystalline silicon film in the first element region. And a step of forming an amorphous silicon film on the polycrystalline silicon film, and then patterning the amorphous silicon film and the polycrystalline silicon film into a predetermined shape to form a lower polycrystalline silicon film Forming a first gate electrode and a second gate electrode having a two-layer structure of a first amorphous silicon film and an upper amorphous silicon film in the first and second element regions, respectively. The polycrystalline silicon film constituting the lower layer of the first gate electrode in which the impurity concentration tends to be lowered before the impurity of the first conductivity type is added to the first gate electrode having a two-layer film structure in one element region First conductivity type Selectively implanting impurity ions, since is possible to increase the impurity concentration of the lower layer permits, can be more effectively suppressed depletion of a first conductivity type gate electrode.
0033]
  Claims3The method of manufacturing a semiconductor device according to claim 8 is the method of manufacturing a semiconductor device according to claim 8, wherein the first conductivity type impurity ions to be selectively implanted into the polycrystalline silicon film in the first element region are N-type impurity ions. With this configuration, it is possible to increase the impurity concentration in the lower layer of the N-type gate electrode, which tends to cause depletion of the gate electrode particularly, and to more effectively suppress the depletion of the N-type gate electrode. Can do.
0034]
  Claims4A method of manufacturing a semiconductor device according to claim 13In the method of manufacturing a semiconductor device according to the above, after the step of selectively implanting N-type impurity ions into the polycrystalline silicon film in the first element region, P-type impurity ions are implanted into the polycrystalline silicon film in the second element region. By adopting a structure including the step of selectively injecting, not only the impurity concentration of the lower layer of the N-type gate electrode but also the impurity concentration of the lower layer of the P-type gate electrode is increased, so that the N-type and Depletion of both P-type gate electrodes can be suppressed.
0035]
  Claims5In the method of manufacturing a semiconductor device according to the first aspect, after depositing an amorphous silicon film via a gate insulating film on the semiconductor substrate in the first and second element regions, the amorphous silicon film is patterned into a predetermined shape. Then, the first step of forming the first and second gate electrodes made of an amorphous silicon film, and the surface of the semiconductor substrate in the first element region and the first gate electrode are selectively doped with N-type impurity ions. After injectingN-type impurity ionsActivatedAn insulating film is formed on the entire surface of the substrate by the vapor phase growth method under the heat treatment conditions, and at the same time,A second step of forming an N-type impurity region on the surface of the semiconductor substrate of the first element region and making the first gate electrode an N-type gate electrode;Through the insulating filmAfter selectively implanting P-type impurity ions into the surface of the semiconductor substrate and the second gate electrode in the second element region,PredeterminedA third step of activating P-type impurity ions by the heat treatment to form a P-type impurity region on the surface of the semiconductor substrate of the second element region and making the second gate electrode a P-type gate electrode;After removing the insulating filmAfter the refractory metal film is deposited on the entire surface of the substrate, the refractory metal film on the N-type and P-type impurity regions and the N-type and P-type gate electrodes is silicided by heat treatment, and an unreacted refractory metal film is formed. And a fourth step of forming a refractory metal silicide film in a self-aligned manner on the N-type and P-type impurity regions and on the N-type and P-type gate electrodes by etching away.
0036]
  Thus claims5In the method of manufacturing a semiconductor device according to the present invention, the refractory metal silicide film is formed in a self-aligned manner on the N-type and P-type gate electrodes made of an amorphous silicon film, so that these N-type and P-type gates are formed. The fine line effect of the refractory metal silicide film formed on the electrode can be suppressed.
0037]
  In addition, after selectively injecting N-type impurity ions into the first gate electrode and performing a first heat treatment for activating the N-type impurity ions, P-type impurity ions are applied to the second gate electrode. By selectively implanting and performing the second heat treatment for activating the P-type impurity ions, the P-type impurity is not yet added to the second gate electrode during the first heat treatment. Even if the range of N-type impurity ions during ion implantation is relatively small and the diffusion coefficient of N-type impurities is relatively small, punch-through and short channel effects due to diffusion of P-type impurities having a large diffusion coefficient Since N-type impurities can be sufficiently diffused throughout the first gate electrode made of an amorphous silicon film without causing deterioration of the characteristics of the PMOS transistor due to generation or the like, it tends to occur particularly noticeably. It is possible to suppress the depletion of the N-type gate electrode.
0038]
  In this way, depletion of the N-type gate electrode can be suppressed by making the N-type gate electrode conductive before the P-type gate electrode, and the refractory metal formed on the gate electrode. By utilizing the advantages of the amorphous silicon film that can suppress the thin line effect of the silicide film, even in a dual gate structure, the N-type gate electrode is depleted and the refractory metal formed on the gate electrode The fine line effect of the silicide film can be suppressed at the same time. Furthermore, since it is not necessary to reduce the thickness of the gate electrode in order to suppress depletion of the gate electrode, partial overgrowth of the refractory metal silicide film when the refractory metal silicide film is formed on the gate electrode. It is possible to prevent the breakdown voltage of the gate oxide film from being deteriorated due to (penetration) and to prevent the transistor characteristics from being deteriorated.
0039]
  Also,A refractory metal silicide film is formed on the N-type and P-type gate electrodes made of an amorphous silicon film in a self-aligned manner, and an N-type impurity ion is formed on the first gate electrode made of the amorphous silicon film. The insulating film is formed after selectively injecting, but the heat treatment conditions for forming this insulating film are sufficient to activate the N-type impurity ions.N typeIn addition, the thin line effect of the refractory metal silicide film formed on the P-type gate electrode can be suppressed, the depletion of the N-type gate electrode can be suppressed, and the deterioration of the transistor characteristics due to the breakdown voltage degradation of the gate oxide film can be prevented. .
  In addition, the insulating film formed after the N-type impurity ions are implanted into the first gate electrode is used when the P-type impurity ions are selectively implanted into the surface of the semiconductor substrate in the second element region and the second gate electrode. Since it becomes a screen oxide film, even if it is a P-type impurity having a large diffusion coefficient, it becomes possible to easily reduce the junction depth of the P-type impurity region formed on the semiconductor substrate surface of the second element region, The PMOS transistor characteristics can be improved.
0040]
  As prior arts related to the present invention, there are “a manufacturing method of a MIS type semiconductor device” of Japanese Patent Laid-Open No. 3-209934 and “a method of manufacturing a semiconductor device” of Japanese Patent Laid-Open No. 7-37992. The essential differences from the present invention will be described below.
0041]
  In “Manufacturing method of MIS type semiconductor device” of Japanese Patent Application Laid-Open No. Hei 3-20934, the method of manufacturing a semiconductor device in which titanium silicide is formed on the exposed polycrystalline silicon surface in a self-aligned manner is provided. A step of forming a polycrystalline silicon film over the gate insulating film, a process of amorphizing the vicinity of the surface of the polycrystalline silicon film by implanting impurity ions into the polycrystalline silicon film; A process of processing a silicon film into a gate electrode and wiring by photolithography and etching techniques, a process of forming a titanium metal film over the entire surface of the semiconductor substrate, and a heat treatment of the semiconductor substrate on which the titanium metal film is formed Changing the titanium on the silicon surface and titanium on the gate electrode into titanium silicide, and the titanium silicide Method for producing a MIS-type semiconductor device characterized by comprising the step of selectively removing the titanium compound and the titanium metal other than "a.
0042]
  JPIn the manufacturing method according to Japanese Patent No. 3-209834, impurity ions are implanted into a polycrystalline silicon film formed on a semiconductor substrate via a gate insulating film to make the surface vicinity amorphous, and this surface vicinity is made amorphous silicon. The film is processed into a gate electrode, a titanium metal film is formed on the gate electrode, the amorphous silicon layer on the gate electrode surface is converted into titanium silicide by heat treatment, and titanium silicide is self-aligned on the gate electrode. To form.
0043]
  Accordingly, the claims of the present invention1A method of manufacturing a semiconductor device according to the present invention, ie, forming a gate electrode having a two-layer film structure of a lower polycrystalline silicon film and an upper amorphous silicon film on a semiconductor substrate via a gate insulating film, A semiconductor device characterized by depositing a refractory metal film on an electrode, siliciding the refractory metal film on the gate electrode by heat treatment, and forming a refractory metal silicide film on the gate electrode in a self-aligning manner. The manufacturing method is essentially different from the manufacturing method disclosed in JP-A-3-209834.
0044]
  Similarly, the claims of the present invention5The first and second gate electrodes made of an amorphous silicon film are formed on the semiconductor substrate in the first and second element regions via the gate insulating film, and the first and second gate electrodes are formed. After selectively injecting N-type impurity ions into the first gate electrode, the N-type impurity ions are activated by a first heat treatment to make the first gate electrode an N-type gate electrode, and subsequently to the second gate electrode. After selectively implanting P-type impurity ions, the second heat treatment activates the P-type impurity ions to form a P-type gate electrode, and a high melting point is formed on these N-type and P-type gate electrodes. A method of manufacturing a semiconductor device characterized in that the metal silicide film is formed in a self-aligned manner is essentially different from the manufacturing method of Japanese Patent Laid-Open No. 3-209984.
0045]
  JPIn the manufacturing method according to No. 7-37992, after an amorphous silicon layer is formed on a semiconductor substrate on which a gate insulating film is formed, the amorphous silicon layer is converted into a polycrystalline silicon layer by heat treatment, and a metal silicide is formed on the polycrystalline silicon layer. A layer is formed, and the metal silicide layer and the polycrystalline silicon layer are patterned to form a gate electrode.
  Accordingly, the claims of the present invention1A method of manufacturing a semiconductor device according to the present invention, ie, forming a gate electrode having a two-layer film structure of a lower polycrystalline silicon film and an upper amorphous silicon film on a semiconductor substrate via a gate insulating film, A manufacturing method of a semiconductor device characterized by forming a refractory metal silicide film on an electrode in a self-aligning manner is essentially different from the manufacturing method of Japanese Patent Application Laid-Open No. 7-37992.
0046]
  Similarly, the claims of the present invention5The first and second gate electrodes made of an amorphous silicon film are formed on the semiconductor substrate in the first and second element regions via the gate insulating film, and the first and second gate electrodes are formed. After selectively injecting N-type impurity ions into the first gate electrode, the N-type impurity ions are activated by a first heat treatment to make the first gate electrode an N-type gate electrode, and subsequently to the second gate electrode. After selectively implanting P-type impurity ions, the second heat treatment activates the P-type impurity ions to form a P-type gate electrode, and a high melting point is formed on these N-type and P-type gate electrodes. A method for manufacturing a semiconductor device characterized in that the metal silicide film is formed in a self-aligned manner is essentially different from the method described in Japanese Patent Laid-Open No. 7-37992.
0047]
DETAILED DESCRIPTION OF THE INVENTION
  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
(First embodiment)
  A dual-gate C-MOS transistor and a manufacturing method thereof according to a first embodiment of the present invention will be described with reference to FIGS. Here, FIG. 1 is a cross-sectional view showing a dual-gate C-MOS transistor according to this embodiment, and FIGS. 2 to 12 are process cross-sectional views for explaining a method of manufacturing the C-MOS transistor of FIG. 13 is a graph showing the relationship between the width of the gate electrode and the sheet resistance of the C-MOS transistor of FIG. 1, and FIG. 14 is a graph showing the relationship between the impurity region and the width of the gate electrode and the sheet of the comparative example of this embodiment. It is a graph which shows the relationship with resistance.
0048]
  As shown in FIG. 1, an element isolation oxide film 12 is formed on a Si substrate 11 in an element isolation region, and the element region is isolated by the element isolation oxide film 12. Instead of the element isolation oxide film 12, the element region may be isolated by an element isolation groove formed by a trench method.
  Of these element regions, a P-type well 13 is formed on the surface of the Si substrate 11 in the NMOS region, and an N-type well 14 is formed on the surface of the Si substrate 11 in the PMOS region. Further, a buried layer (not shown) is formed for the purpose of suppressing punch-through between the source and drain of the MOS transistor.
0049]
  The surface of the P-type well 13 in the NMOS region has a high concentration of N added with, for example, As as an N-type impurity.⁺Impurity regions 15a and 15b are formed facing each other, and these N⁺A region sandwiched between the impurity regions 15a and 15b is a channel region. And these N⁺Adjacent to the impurity regions 15a and 15b, the channel region side has a low concentration of N.^-Impurity regions (not shown) are formed. Thus, N⁺Impurity regions 15a and 15b and N^-The impurity region is integrated with the source / drain of the LDD structure.
0050]
  Similarly, the surface of the N-type well 14 in the PMOS region has a high concentration of P to which, for example, B is added as a P-type impurity.⁺Impurity regions 16a and 16b and low concentration P^-Impurity regions (not shown) are formed relative to each other.^-A region sandwiched between the impurity regions is a channel region. And P⁺Impurity regions 16a and 16b and P^-The impurity region is integrated with the source / drain of the LDD structure.
  N on the surface of the P-type well 13^-A gate oxide film 17 having a thickness of about 5 nm is formed on the channel region sandwiched between the impurity regions. On the gate oxide film 17, a polycrystalline silicon film 18a having a thickness of, for example, about 100 to 150 nm and an amorphous silicon film 19a having a thickness of, for example, about 20 to 50 nm are sequentially stacked. An N-type gate electrode 20a having a two-layer film structure is formed.
0051]
  Similarly, P on the surface of the N-type well 14^-On the channel region sandwiched between the impurity regions, a gate oxide film 17 having a thickness of about 5 nm is formed. On the gate oxide film 17, a P-type impurity is added to a thickness of about 100 to 150 nm. A P-type gate electrode 20b having a two-layer film structure in which a crystalline silicon film 18b and an amorphous silicon film 19b having a thickness of about 20 to 50 nm are sequentially stacked is formed.
0052]
  Here, the thickness of the polycrystalline silicon films 18a and 18b of about 100 to 150 nm is necessary to prevent depletion of the N-type and P-type gate electrodes 20a and 20b and to prevent deterioration of the gate breakdown voltage. It is set as the film thickness. The amorphous silicon films 19a and 19b have a thickness of about 20 to 50 nm when the refractory metal silicide film is formed on the N-type and P-type gate electrodes 20a and 20b. It is sufficient to reduce the resistance of the refractory metal silicide film on the gate electrodes 20a and 20b, and when the N-type impurity ions are implanted into the N-type gate electrode 20a, the lower polycrystalline layer It is set as a thin film thickness necessary to obtain a sufficient range to the silicon film 18a.
0053]
  Further, gate sidewalls 21 made of an insulating film such as a silicon oxide film or a silicon nitride film are formed on the side surfaces of the N-type and P-type gate electrodes 20a and 20b.
0054]
  N constituting the source / drain⁺Impurity regions 15a, 15b and P⁺C54 phase TiSi is formed on the impurity regions 16a and 16b.₂A film 22a is formed, and C54 phase TiSi is formed on the N-type and P-type gate electrodes 20a and 20b.₂A film 22b is formed. These TiSi₂Instead of the films 22a and 22b, a silicide film of a refractory metal such as Co (cobalt), Ni (nickel), Pt (platinum), for example, CoSi₂Film, NiSi₂A film, a PtSi film, or the like may be used.
0055]
  An interlayer insulating film 23 is formed on the entire surface of the substrate. In addition, for example, W plugs 24 are embedded in the plurality of connection holes opened in the interlayer insulating film 23, and these W plugs 24 are⁺Impurity regions 15a, 15b and P⁺TiSi on impurity regions 16a and 16b₂TiSi on film 22a and N-type and P-type gate electrodes 20a, 20b₂Each is connected to the film 22b. A wiring layer 25 is connected to these W plugs 24. The whole is covered with the surface protective film 26.
0056]
  Next, a method for manufacturing the dual-gate C-MOS transistor of FIG. 1 will be described with reference to FIGS.
  First, using a LOCOS (Local Oxidatin of Silicon) method, wet oxidation is performed at a temperature of 950 ° C. to form an element isolation oxide film 12 on the Si substrate 11 in the element isolation region. Instead of forming the element isolation oxide film 12 using this LOCOS method, element isolation grooves may be formed using a trench method.
0057]
  Subsequently, among the element regions separated by the element isolation oxide film 12, a P-type well 13 is formed on the surface of the Si substrate 11 in the NMOS region, and an N-type well 14 is formed on the surface of the Si substrate 11 in the PMOS region. To do. Further, a buried layer (not shown) for the purpose of suppressing punch-through between the source / drain of the MOS transistor, ion implantation for adjusting the threshold voltage Vth, and the like are performed.
0058]
  Next, H₂/ O₂For example, pyrogenic oxidation using a gas is performed under the condition of a temperature of 850 ° C., and a gate oxide film 17 having a thickness of about 5 nm is formed on the P-type well 13 and the N-type well 14 in the NMOS region and the PMOS region, respectively (see FIG. (See FIG. 2).
0059]
  Next, a polycrystalline silicon film 18 having a thickness of, for example, about 100 to 150 nm is formed on the entire surface of the substrate by using a CVD (Chemical Vapor Deposition) method. The film formation conditions of the polycrystalline silicon film 18 at this time are, for example,
      Pressure: 50-400Pa,
      Deposition temperature: 600-650 ° C,
      SiH_FourGas flow rate: 50-2000sccm
(See FIG. 3).
Next, predetermined impurity ions are implanted into the polycrystalline silicon film.
→ Based on “After forming a polycrystalline silicon film, a predetermined impurity ion is implanted into the polycrystalline silicon film” described in paragraph 0033.
0060]
  Next, an amorphous silicon film 19 having a thickness of, for example, about 20 to 50 nm is formed on the polycrystalline silicon film 18. The film formation conditions of the amorphous silicon film 19 at this time are, for example,
      Pressure: 50-400Pa,
      Deposition temperature: 500-600 ° C,
      SiH_FourGas flow rate: 50-2000sccm
(See FIG. 4).
0061]
  Next, the amorphous silicon film 19 and the polycrystalline silicon film 18 are patterned into a gate shape using a lithography technique and a dry etching method. In this way, the gate electrode 20 composed of the polycrystalline silicon film 18 and the amorphous silicon film 19 sequentially stacked via the gate oxide film 17 on the P-type well 13 and the N-type well 14 in the NMOS region and the PMOS region, respectively. Form (see FIG. 5).
0062]
  Next, after covering the PMOS region with a resist (not shown), the resist, the element isolation oxide film 12, and the gate electrode 20 in the NMOS region are used as masks to form N-type impurity ions, for example, As.⁺Is selectively implanted into the surface of the P-type well 13 to form an LDD structure at a low concentration of N^-Impurity regions (not shown) are formed. Similarly, as P-type impurity ions, for example, BF₂ ⁺Is selectively ion-implanted into the surface of the N-type well 14 to form a low-concentration P having an LDD structure.^-Impurity regions (not shown) are formed.
0063]
  Subsequently, for example, SiH_Four/ O₂Atmospheric pressure CVD method using gas as raw material gas, TEOS (tetaraethoxysilane; (C₂H_FiveO)_FourTEOS low pressure CVD method using Si) as raw material, SiH_Four/ NH_ThreeAn insulating film such as a silicon oxide film or a silicon nitride film is deposited on the entire surface of the substrate using an atmospheric pressure CVD method using a gas or the like as a source gas, and then this insulating film is anisotropically etched using a dry etching method. Thus, gate sidewalls 21 made of an insulating film are formed on each side surface of the gate electrode 20 in the NMOS region and the PMOS region (see FIG. 6).
0064]
  Next, after covering the PMOS region with a resist 27, the resist 27, the element isolation oxide film 12, the gate electrode 20 in the NMOS region, and the gate side wall 21 on the side surface of the gate electrode 20 are used as N-type impurity ions. For example As⁺Are selectively implanted into the surface of the P-type well 13. In addition, as ion implantation conditions at this time, the acceleration energy is about 20 to 80 keV, and the dose amount is 1 × 10 6.¹⁵~ 5x10¹⁵/ Cm²To the extent. Thus, N^-High-concentration N constituting the source / drain of the LDD structure integrated with the impurity region⁺Impurity regions 15a and 15b are formed.
0065]
  At the same time, the gate electrode 20 in the NMOS region where the polycrystalline silicon film 18 and the amorphous silicon film 19 are stacked is also formed on the As.⁺Is ion-implanted, the gate electrode 20 of this NMOS region⁺Becomes an N-type gate electrode 20a made of an amorphous silicon film 19a and a polycrystalline silicon film 18a. At this time, the thickness of the upper amorphous silicon film 19 is as thin as about 20 to 50 nm.⁺This range can sufficiently reach the underlying polycrystalline silicon film 18. Then, As reaches the lower polycrystalline silicon film 18.⁺Is deeply implanted along the crystal grains, so that As is formed throughout the entire N-type gate electrode 20a.⁺Is injected with good uniformity (see FIG. 7).
0066]
  Next, the resist 27 is removed. Subsequently, after the NMOS region is covered with a resist 28, P-type impurity ions are formed using the resist 28, the element isolation oxide film 12, the gate electrode 20 in the PMOS region, and the gate side wall 21 on the side surface of the gate electrode 20 as a mask. For example, BF₂ ⁺Are selectively ion-implanted into the surface of the N-type well 14. The ion implantation conditions at this time are such that the acceleration energy is about 20 to 40 keV and the dose is 1 × 10.¹⁵~ 5x10¹⁵/ Cm²To the extent. Thus, P^-High concentration of P that constitutes the source / drain of the LDD structure integrally with the impurity region⁺Impurity regions 16a and 16b are formed.
  At the same time, the BF is also applied to the gate electrode 20 in the PMOS region where the polycrystalline silicon film 18 and the amorphous silicon film 19 are laminated.₂ ⁺Is implanted, so that the gate electrode 20 in the PMOS region is BF.₂ ⁺Becomes a P-type gate electrode 20b composed of an amorphous silicon film 19b and a polycrystalline silicon film 18b (see FIG. 8).
0067]
  Next, after removing the resist 28, heat treatment is performed using a rapid thermal annealing (RTA) method, for example, at a temperature of 1000 ° C. for a treatment time of 30 seconds, and N^-Impurity region and N⁺Impurity regions 15a, 15b, P^-Impurity region and P⁺Impurity ions As implanted into the impurity regions 16a and 16b and the N-type and P-type gate electrodes 20a and 20b.⁺, BF₂ ⁺Activate.
0068]
  Followed by N⁺Impurity regions 15a, 15b and P⁺A natural oxide film (not shown) that naturally grows on the impurity regions 16a and 16b and the N-type and P-type gate electrodes 20a and 20b is completely removed by hydrofluoric acid treatment, and then the entire surface of the substrate is formed by vapor deposition. For example, a Ti film 22 having a thickness of about 30 nm is formed as the melting point metal film. Instead of the Ti film 22, a refractory metal film such as a Co film, a Ni film, or a Pt film may be used (see FIG. 9).
0069]
  Then, using a two-step annealing method, N⁺Impurity regions 15a, 15b and P⁺The Ti film 22 deposited on the impurity regions 16a and 16b and the N-type and P-type gate electrodes 20a and 20b is silicided.
0070]
  That is, as the first heat treatment, for example, N₂(Nitrogen) RTA treatment is performed in a gas atmosphere at a temperature of 650 ° C. for a treatment time of 30 seconds, and N⁺Impurity regions 15a, 15b and P⁺The Si in the impurity regions 16a and 16b and the Ti in the Ti film 22 are reacted to form C49 phase TiSi.₂A film 22a is formed, and Si of the N-type and P-type gate electrodes 20a and 20b and Ti of the Ti film 22 are reacted to form C49-phase TiSi.₂A film 22b is formed. At this time, the Ti film 22 on the element isolation oxide film 12 and the gate sidewall 21 does not react with the underlying film, and therefore remains as an unreacted Ti film 22. The unreacted Ti film 22 is converted into ammonia perwater (NH_Three: H₂O₂: H₂O = 1: 2: 6) etc. to selectively remove.
  After that, as the second heat treatment, for example, N₂Perform RTA treatment at a temperature of 800 ° C. and a treatment time of 30 seconds in a gas atmosphere to obtain C49 phase TiSi₂The films 22a and 22b are made of C54 phase TiSi having a relatively low resistance.₂Phase transition is performed on the films 22a and 22b. Thus, N⁺Impurity regions 15a, 15b and P⁺C54 phase TiSi on the impurity regions 16a and 16b₂The film 22a is also formed on the N-type and P-type gate electrodes 20a, 20b with C54 phase TiSi.₂The films 22b are formed in a self-aligned manner (see FIG. 10).
0071]
  Next, an interlayer insulating film 23 is formed on the entire surface of the substrate (see FIG. 11). Next, the interlayer insulating film 23 is coated with N⁺Impurity regions 15a, 15b and P⁺TiSi on impurity regions 16a and 16b₂Connection holes reaching the film 22a and TiSi on the N-type and P-type gate electrodes 20a, 20b₂After opening the connection holes reaching the film 22b, the connection holes are filled with, for example, W plugs 24, respectively. Then, after forming the wiring layer 25 connected to the W plug 24, the surface protective film 26 is formed on the entire surface of the substrate (see FIG. 12). In this way, the dual-gate C-MOS transistor of FIG. 1 is manufactured.
0072]
  As described above, according to the present embodiment, a gate having a two-layer structure of the polycrystalline silicon film 18 and the amorphous silicon film 19 via the silicon oxide film 17 on the Si substrate 11 in the NMOS region and the PMOS region. Electrodes 20 are formed, and these gate electrodes 20 are respectively connected to As.⁺And BF₂ ⁺N-type and P-type gate electrodes 20a and 20b are formed by ion implantation, and the thickness of the upper amorphous silicon film 19 constituting these gate electrodes 20 is about 20 to 50 nm. Due to the extremely thinness, ion-implanted As⁺And BF₂ ⁺Can reach the lower polycrystalline silicon film 18 as well, and As reaches the lower polycrystalline silicon film 18.⁺And BF₂ ⁺Are implanted deep along the crystal grains. Therefore, the N-type and P-type gate electrodes 20a and 20b in which the N-type and P-type impurities are uniformly diffused over the entire surface can be formed, and the N-type and P-type gate electrodes 20a and 20b are depleted. Can be suppressed.
0073]
  Then, the diffusion of impurities with good uniformity into the entire N-type and P-type gate electrodes 20a, 20b is caused by As having a relatively small range.⁺Is more effective in the N-type gate electrode 20a in which As is implanted with a relatively small diffusion coefficient. For this reason, this embodiment is particularly effective in suppressing the depletion of the N-type gate electrode 20a that tends to cause significant depletion.
0074]
  Further, after the Ti film 22 is formed on the entire surface of the substrate, the C54 phase TiSi is formed on the N-type and P-type gate electrodes 20a and 20b by silicidation reaction by heat treatment, removal of the unreacted Ti film 22 and the like.₂The film 22b is formed in a self-aligning manner. At this time, a Ti film is formed on the amorphous silicon films 19a and 19b having an upper layer thickness of about 20 to 50 nm constituting the N-type and P-type gate electrodes 20a and 20b. Since 22 is directly deposited and silicided by heat treatment, this silicidation reaction is promoted to achieve a sufficiently low resistance, and therefore formed on the N-type and P-type gate electrodes 20a and 20b. TiSi₂The fine line effect of the film 22b can be suppressed.
0075]
  In the dual-gate C-MOS transistor manufactured by the present inventor based on the present embodiment, the widths of the N-type and P-type gate electrodes 20a and 20b are changed to be on the N-type and P-type gate electrodes 20a and 20b. TiSi formed₂When the sheet resistance of the film 22b was measured, the result shown in the graph of FIG. 13 was obtained. As is apparent from this graph, TiSi₂It can be said that the line width dependence of the sheet resistance of the film 22b is hardly observed including the thin line region. Accordingly, TiSi formed on the N-type and P-type gate electrodes 20a and 20b.₂It was confirmed that the thin line effect of the film 22b was suppressed.
0076]
  For comparison, in the graph of FIG. 14, the source / drain is configured in a C-MOS transistor having a dual gate structure manufactured based on the method of manufacturing a semiconductor device according to the above-mentioned Japanese Patent Application No. 8-75217. N⁺Impurity region and P⁺TiSi formed on the impurity regions and the N-type and P-type gate electrodes made of the polycrystalline silicon film by changing the width thereof₂The result of having measured the sheet resistance of the film | membrane is shown. From this graph, N⁺Impurity region and P⁺TiSi formed on impurity region₂Although the line width dependence of the sheet resistance of the film is not observed including the thin line region, TiSi formed on the N-type and P-type gate electrodes₂The dependence of the sheet resistance of the film on the line width is observed, and in the thin line region, the sheet resistance increases rapidly as the gate width decreases, and this tendency is particularly noticeable in the case of the N-type gate electrode.
  Therefore, by comparing the graph of FIG. 13 with the graph of FIG. 14, the TiSi formed on the N-type and P-type gate electrodes 20a and 20b.₂Thin line effect of the film 22b, particularly TiSi formed on the N-type gate electrode 20b₂It is confirmed that the thin line effect of the film 22b is suppressed by this embodiment.
0077]
  In this way, by forming the N-type and P-type gate electrodes 20a and 20b having the two-layer structure of the lower polycrystalline silicon films 18a and 18b and the upper amorphous silicon films 19a and 19b, the gates are formed. Advantages of polycrystalline silicon films 18a and 18b that can suppress depletion of electrodes and TiSi₂Even in the so-called dual gate structure having the N-type and P-type gate electrodes 20a and 20b at the same time by utilizing the advantages of the amorphous silicon films 19a and 19b capable of suppressing the thin line effect of the film 22b, TiSi formed on the N-type and P-type gate electrodes 20a and 20b₂Since the thin line effect of the film 22b and the depletion of the N-type and P-type gate electrodes 20a and 20b, particularly the depletion of the N-type gate electrode 20a can be suppressed at the same time, miniaturization of the dual gate structure device Can contribute to speeding up.
0078]
  In addition, since the thickness of the N-type and P-type gate electrodes 20a and 20b is not reduced more than necessary in order to suppress depletion, TiSi is formed on the N-type and P-type gate electrodes 20a and 20b.₂When forming the film 22b, TiSi₂It is possible to prevent the breakdown voltage of the gate oxide film 17 from being deteriorated due to partial overgrowth (penetration) of the film 22b.
  In addition, since it is not necessary to perform high-temperature and long-time heat treatment at the time of impurity ion activation to suppress depletion of the N-type gate electrode 20a in particular, the diffusion of impurities such as B having a large diffusion coefficient in the PMOS transistor is eliminated. The occurrence of punch-through and short channel effects can be prevented, and deterioration of transistor characteristics can be prevented.
0079]
(Second Embodiment)
  A dual-gate C-MOS transistor and a method for manufacturing the same according to a second embodiment of the present invention will be described with reference to FIGS. Here, FIG. 15 is a sectional view showing a dual-gate C-MOS transistor according to the second embodiment, and FIGS. 16 to 20 are steps for explaining a method of manufacturing the C-MOS transistor of FIG. It is sectional drawing. In addition, the same code | symbol is attached | subjected to the element same as the component of the said 1st Embodiment, and description is abbreviate | omitted or simplified.
0080]
  As shown in FIG. 15, an N-type impurity is added via a gate oxide film 17 onto the P-type well 13 in the NMOS region separated by the element isolation oxide film 12 formed on the Si substrate 11. An N-type gate electrode 20d having a two-layer film structure in which a polycrystalline silicon film 18d and an amorphous silicon film 19a are sequentially stacked is formed.
  That is, the point that the N-type gate electrode 20d has a two-layer film structure of the lower polycrystalline silicon film 18d and the upper amorphous silicon film 19a is the lower polycrystalline silicon film in the first embodiment. The structure is similar to that of the N-type gate electrode 20a having a two-layer structure of 18a and the upper amorphous silicon film 19a, but the lower polycrystalline silicon film 18d constituting the N-type gate electrode 20d has the above structure. It is characterized in that an N-type impurity having a higher concentration than that of the lower polycrystalline silicon film 18a constituting the N-type gate electrode 20a in the first embodiment is added. The rest of the configuration is almost the same as that of the first embodiment shown in FIG.
0081]
  Next, a method for manufacturing the dual-gate C-MOS transistor of FIG. 15 will be described with reference to FIGS.
  The element isolation oxide film 12 is formed on the Si substrate 11 in the element isolation region and then separated by the element isolation oxide film 12 in the same manner as the steps shown in FIGS. A P-type well 13 is formed on the surface of the Si substrate 11 in the NMOS region, and an N-type well 14 is formed on the surface of the Si substrate 11 in the PMOS region. Subsequently, a gate oxide film 17 is formed on the P-type well 13 and the N-type well 14 in the NMOS region and the PMOS region, respectively, and then a polycrystalline silicon film 18 is formed on the entire surface of the substrate (see FIG. 16).
0082]
  Next, after covering the PMOS region with a resist 29, using this resist 29 as a mask, the polycrystalline silicon film 18 in the NMOS region is doped with N-type impurity ions, for example, As.⁺Are selectively ion-implanted. As ion implantation conditions at this time, the acceleration energy is about 10 to 40 keV, and the dose is 1 × 10 6.¹⁵~ 5x10¹⁵/ Cm²To the extent. As⁺For example, P⁺(Phosphorus ion) may also be used. This P⁺As for the ion implantation conditions in the case of using A, the acceleration energy is about 10 to 40 keV and the dose amount is 1 × 10.¹⁵~ 5x10¹⁵1 / cm²To the extent. Thus, the polycrystalline silicon film 18 in the NMOS region becomes the polycrystalline silicon film 18c implanted with N-type impurity ions (see FIG. 17).
0083]
  Next, after removing the resist 29, an amorphous silicon film 19 is formed on the polycrystalline silicon films 18c and 18 in the same manner as the process shown in FIG. 4 of the first embodiment (see FIG. 18). .
  Next, in the same manner as the process shown in FIG. 5 of the first embodiment, the amorphous silicon film 19 and the polycrystalline silicon films 18c and 18 are patterned into a gate shape and formed on the P-type well 13 in the NMOS region. Forms a gate electrode 20c composed of a polycrystalline silicon film 18c and an amorphous silicon film 19 which are sequentially stacked via a gate oxide film 17, and a gate oxide film 17 is formed on the N-type well 14 in the PMOS region. Then, a gate electrode 20 composed of a polycrystalline silicon film 18 and an amorphous silicon film 19 which are sequentially stacked is formed (see FIG. 19).
0084]
  Next, in the same manner as the steps shown in FIGS. 6 to 12 of the first embodiment, As is formed on the surface of the P-type well 13 in the NMOS region.⁺Is selectively ion-implanted to form a low concentration of N^-Impurity region (not shown) and high concentration N⁺Impurity regions 15a and 15b are formed to constitute the source / drain of the LDD structure.
  At this time, high concentration of N⁺As for forming impurity regions 15a and 15b⁺Is ion-implanted also into the gate electrode 20c, so that the gate electrode 20c made of the polycrystalline silicon film 18c and the amorphous silicon film 19 is made of As.⁺Is further ion-implanted polycrystalline silicon film 18d and As⁺Becomes an N-type gate electrode 20d made of an amorphous silicon film 19a into which ions are implanted. That is, the lower polycrystalline silicon film 18d already has As.⁺Is ion-implanted, an amount of As sufficient to suppress depletion of the N-type gate electrode 20d.⁺Will be ion-implanted.
0085]
  In addition, BF is formed on the surface of the N-type well 14 in the PMOS region.₂ ⁺Selectively ion-implanted with a low concentration of P^-Impurity region (not shown) and high concentration P⁺Impurity regions 16a and 16b are formed to constitute the source / drain of the LDD structure. At this time, a high concentration of P⁺BF for forming impurity regions 16a and 16b₂ ⁺Is also injected into the gate electrode 20, so that both BF₂ ⁺As a result, a P-type gate electrode 20b made of a polycrystalline silicon film 18b and an amorphous silicon film 19b into which ions are implanted is formed.
0086]
  Thereafter, N is performed by heat treatment using the RTA method.^-Impurity region and N⁺Impurity regions 15a, 15b, P^-Impurity region and P⁺The impurity ions implanted into the impurity regions 16a and 16b and the N-type and P-type gate electrodes 20d and 20b are activated. Subsequently, after forming a Ti film 22 as a refractory metal film on the entire surface of the substrate, N-step annealing is used to form N film.⁺Impurity regions 15a, 15b and P⁺The Ti film 22 on the impurity regions 16a and 16b and the N-type and P-type gate electrodes 20a and 20b is silicided to form N⁺Impurity regions 15a, 15b and P⁺C54 phase TiSi on the impurity regions 16a and 16b₂The films 22a and 22b are formed on the N-type and P-type gate electrodes 20a and 20b.₂The films 22b are formed in a self-aligned manner.
0087]
  Subsequently, the interlayer insulating film 23 formed on the entire surface of the base is coated with N⁺Impurity regions 15a, 15b and P⁺TiSi on impurity regions 16a and 16b₂Connection holes reaching the film 22a and TiSi on the N-type and P-type gate electrodes 20a, 20b₂The connection holes reaching the film 22b are opened, and TiSi is passed through the W plugs 24 filling the connection holes.₂After the wiring layer 25 connected to the films 22a and 22b is formed, a surface protective film 26 is formed on the entire surface of the substrate (see FIG. 20). In this way, the dual-gate C-MOS transistor of FIG. 15 is manufactured.
0088]
  As described above, according to the present embodiment, As is formed only in the NMOS region portion of the polycrystalline silicon film 18 formed on the Si substrate 11 via the silicon oxide film 17.⁺Is selectively implanted to form a polycrystalline silicon film 18c, and the polycrystalline silicon film 18c and the amorphous silicon film 19 laminated thereon are patterned to form the polycrystalline silicon film 18c and the amorphous silicon in the NMOS region. After the gate electrode 20c made of the film 19 is formed, the gate electrode 20c is coated with As.⁺To form an N-type gate electrode 20d having a two-layer film structure of a lower polycrystalline silicon film 18d and an upper amorphous silicon film 19a, thereby forming a lower layer constituting the N-type gate electrode 20d. The polycrystalline silicon film 18d is doubled with As.⁺Therefore, the impurity concentration in the lower layer where the impurity concentration is generally lowest in the N-type gate electrode can be made sufficiently high. Therefore, it is possible to form the N-type gate electrode 20d to which N-type impurities are added with good uniformity throughout. Therefore, the suppression of depletion of the N-type gate electrode 20d that tends to cause particularly significant depletion can be achieved more effectively than in the case of the first embodiment.
  Further, TiSi formed on the N-type and P-type gate electrodes 22d and 22b.₂Suppression of the fine line effect of the film 22b and the like can achieve the same effects as in the case of the first embodiment.
0089]
  Note that in the second embodiment, in order to suppress the depletion of the N-type gate electrode, which is particularly likely to cause significant depletion, only the lower polycrystalline silicon film 18d constituting the N-type gate electrode 20d has 2 Heavy As⁺Although ion implantation is performed, the same may be performed for the P-type gate electrode.
  In other words, As is only applied to the NMOS region portion of the polycrystalline silicon film 18.⁺Is selectively implanted to form a polycrystalline silicon film 18c, and then, for example, BF is applied only to the other PMOS region.₂ ⁺Is selectively implanted to form a polycrystalline silicon film 18e, and the polycrystalline silicon films 18c and 18e and the amorphous silicon film 19 laminated thereon are patterned to form a polycrystalline silicon film 18c and an amorphous film in the NMOS region. A gate electrode 20c made of a porous silicon film 19 is formed, and a gate electrode 20e made of a polycrystalline silicon film 18e and an amorphous silicon film 19 is formed in the PMOS region. Subsequently, As is applied to the gate electrode 20c by the same process as in the second embodiment.⁺Are selectively ion-implanted to form an N-type gate electrode 20d, and then, for example, BF is added to the gate electrode 20e.₂ ⁺BF selectively, BF₂ ⁺Is a double-implanted polycrystalline silicon film 18f and BF₂ ⁺A p-type gate electrode 20f having a two-layer structure with an upper amorphous silicon film 19b into which ions are implanted.
  In this case, in addition to the suppression of depletion of the N-type gate electrode 20d, the suppression of depletion of the P-type gate electrode 20f can be achieved more effectively than in the case of the first embodiment.
[0090]
(Third embodiment)
  A dual-gate C-MOS transistor and a method of manufacturing the same according to a third embodiment of the present invention will be described with reference to FIGS. Here, FIG. 21 is a sectional view showing a dual-gate C-MOS transistor according to the third embodiment, and FIGS. 22 to 28 are steps for explaining a method of manufacturing the C-MOS transistor of FIG. It is sectional drawing. In addition, the same code | symbol is attached | subjected to the element same as the component of the said 1st Embodiment, and description is abbreviate | omitted or simplified.
[0091]
  As shown in FIG. 21, among the element regions isolated by the element isolation oxide film 12 formed on the Si substrate 11, the N-type region is formed on the P-type well 13 in the NMOS region via the gate oxide film 17. An N-type gate electrode 30a made of an amorphous silicon film to which a type impurity is added is formed. Similarly, a P-type gate electrode 30 b made of an amorphous silicon film to which a P-type impurity is added is formed on the n-type well 14 in the PMOS region via a gate oxide film 17.
[0092]
  That is, the N-type gate electrode 20a in the first embodiment has a two-layer structure of the polycrystalline silicon film 18a to which the N-type impurity is added and the amorphous silicon film 19a, and the P-type gate electrode 20b has the P-type structure. In contrast to the two-layer structure of the polycrystalline silicon film 18b to which the type impurity is added and the amorphous silicon film 19b, in the present embodiment, the N-type gate electrode 30a and the P-type gate electrode 30b. Is characterized in that it consists of a single-layer amorphous silicon film to which an N-type impurity and a P-type impurity are added, respectively. The rest of the configuration is almost the same as that of the first embodiment shown in FIG.
[0093]
  Next, a method for manufacturing the dual-gate C-MOS transistor of FIG. 21 will be described with reference to FIGS.
  In the same manner as the process shown in FIG. 2 of the first embodiment, after the element isolation oxide film 12 is formed on the Si substrate 11 in the element isolation region, the element region isolated by the element isolation oxide film 12 is formed. Among them, a P-type well 13 is formed on the surface of the Si substrate 11 in the NMOS region, and an N-type well 14 is formed on the surface of the Si substrate 11 in the PMOS region. Subsequently, gate oxide films 17 are formed on the P-type well 13 and the N-type well 14 (see FIG. 22).
[0094]
  Next, after forming an amorphous silicon film on the entire surface of the substrate, the amorphous silicon film is patterned into a gate shape, and the gate electrode 30 made of the amorphous silicon film is formed into a P-type in the NMOS region and the PMOS region. The gate oxide film 17 is formed on each of the well 13 and the N-type well 14 (see FIG. 23).
  Next, in the same way as the steps shown in FIGS. 6 to 7 of the first embodiment, the surface of the P-type well 13 in the NMOS region is, for example, As.⁺Selectively ion-implanted and N^-An impurity region (not shown) is formed, and further, for example, BF is formed on the surface of the N-type well 14 in the PMOS region.₂ ⁺Selectively ion-implanted and P^-After forming the impurity region (not shown), the gate sidewall 21 made of an insulating film is formed on each side surface of the gate electrode 30 in each of the NMOS region and the PMOS region.
[0095]
  Subsequently, after covering the PMOS region with a resist 31, the resist 31, the element isolation oxide film 12, the gate electrode 30 in the NMOS region, and the gate sidewall 21 on the side surface of the gate electrode 30 are used as masks. For example, As on the surface of the mold well 13⁺Are selectively ion-implanted. As ion implantation conditions at this time, the acceleration energy is about 20 to 80 keV, and the dose is 1 × 10 6.¹⁵~ 5x10¹⁵/ Cm²To the extent. Thus, N^-High-concentration N constituting the source / drain of the LDD structure integrated with the impurity region⁺Impurity regions 15a and 15b are formed. At the same time, the gate electrode 30 in the NMOS region is also As.⁺Is ion-implanted, the gate electrode 30 is made of As.⁺Becomes an N-type gate electrode 30a made of an amorphous silicon film into which ions are implanted (see FIG. 24).
[0096]
  Next, after removing the resist 31, heat treatment is performed using the RTA method under conditions of, for example, a temperature of 1000 to 1100 ° C. and a processing time of 10 to 30 seconds, and N^-Impurity region and N⁺As implanted into impurity regions 15a and 15b and N-type gate electrode 30a⁺Activate. Note that furnace annealing or the like may be used instead of the RTA method. In this case, for example, heat treatment is performed under conditions of a temperature of 800 to 950 ° C. and a treatment time of 10 to 30 minutes. In this manner, the As implanted into the N-type gate electrode 30a before the P-type impurity ions are implanted into the gate electrode 30 in the PMOS region.⁺A feature of the manufacturing method according to the present embodiment is that a heat treatment step for activating the substrate is provided (see FIG. 25).
[0097]
  Next, the NMOS region is covered with a resist 32, and then the resist 32, the element isolation oxide film 12, the gate electrode 30 in the PMOS region, and the gate sidewall 21 on the side surface of the gate electrode 30 are used as masks. For example, BF on the surface of the well 14₂ ⁺Are selectively ion-implanted. As ion implantation conditions at this time, the acceleration energy is about 20 to 40 keV, and the dose is 1 × 10 6.¹⁵~ 5x10¹⁵/ Cm²To the extent. Thus, P^-P that constitutes the source / drain of the LDD structure integrally with the impurity region⁺Impurity regions 16a and 16b are formed. At the same time, the BF is applied to the gate electrode 30 in the PMOS region.₂ ⁺Is ion-implanted, the gate electrode 30 becomes a P-type gate electrode 30b (see FIG. 26).
[0098]
  Next, in the same manner as the process shown in FIG. 9 of the first embodiment, after removing the resist 32, heat treatment using the RTA method is performed, and P^-Impurity region and P⁺BF implanted into impurity regions 16a and 16b and P-type gate electrode 30b₂ ⁺Activate.
  Followed by N⁺Impurity regions 15a, 15b and P⁺After removing the natural oxide film naturally grown on the impurity regions 16a and 16b and the N-type and P-type gate electrodes 30a and 30b, for example, a Ti film 22 is formed as a refractory metal film on the entire surface of the substrate by using, for example, an evaporation method. Film. Instead of the Ti film 22, a refractory metal film such as a Co film, a Ni film, or a Pt film may be used (see FIG. 27).
[0099]
  Next, in the same manner as the steps shown in FIGS. 10 to 12 of the first embodiment, N-step annealing is used.⁺Impurity regions 15a, 15b and P⁺The Ti film 22 on the impurity regions 16a and 16b and the N-type and P-type gate electrodes 30a and 30b is silicided. Thus, N⁺Impurity regions 15a, 15b and P⁺C54 phase TiSi on the impurity region 16a₂The film 22a is also formed on the N-type and P-type gate electrodes 30a and 30b with C54 phase TiSi.₂The films 22b are formed in a self-aligned manner. If a Co film, Ni film, Pt film or the like is used instead of the Ti film 22, TiSi₂CoSi instead of film₂Film and NiSi₂A film, a PtSi film, or the like is formed.
[0100]
  Subsequently, the interlayer insulating film 23 formed on the entire surface of the base is coated with N⁺Impurity regions 15a, 15b and P⁺TiSi on impurity regions 16a and 16b₂Connection holes reaching the film 22a and TiSi on the N-type and P-type gate electrodes 30a, 30b₂The connection holes reaching the film 22b are opened, and TiSi is passed through the W plugs 24 filling the connection holes.₂After the wiring layer 25 connected to the films 22a and 22b is formed, a surface protective film 26 is formed on the entire surface of the substrate (see FIG. 28). In this way, the dual gate structure C-MOS transistor of FIG. 21 is manufactured.
[0101]
  As described above, according to the present embodiment, the gate electrode 30 made of an amorphous silicon film is formed in the NMOS region and the PMOS region, respectively, and As is formed on the gate electrode 30 in the NMOS region.⁺Are selectively ion-implanted to form an N-type gate electrode 30a, and this As⁺After the heat treatment for activating the BF, the BF is applied to the gate electrode 30 in the PMOS region.₂ ⁺Are selectively implanted to form a P-type gate electrode 30b, and this BF₂ ⁺As a result of the heat treatment for activating the As, the As-implanted ions are implanted into the N-type gate electrode 30a in the NMOS region.⁺In the heat treatment for activating the P-type impurity, the P-type impurity is not yet added to the gate electrode 30 in the PMOS region. Therefore, As at the time of ion implantation⁺Range is BF₂ ⁺Even when the diffusion coefficient of As is relatively small compared to the range of B, and the diffusion coefficient of As is relatively small compared to the diffusion coefficient of B, punch-through and short channel effects due to diffusion of B, which has a large diffusion coefficient, in the PMOS transistor. Since the As can be sufficiently diffused in the entire N-type gate electrode 30a in the NMOS region without causing deterioration of transistor characteristics such as generation, the N-type gate tends to be particularly prone to depletion. Depletion of the electrode 30a can be suppressed.
[0102]
  Further, after the Ti film 22 is formed on the entire surface of the substrate, the C54 phase TiSi is formed on the N-type and P-type gate electrodes 30a and 30b by the silicidation reaction by heat treatment and the removal of the unreacted Ti film 22 or the like.₂The film 22b is formed in a self-aligned manner. At this time, the N-type and P-type gate electrodes 30a and 30b are made of an amorphous silicon film, and the Ti film 22 is directly deposited on the amorphous silicon film. Then, it is silicided by heat treatment. For this reason, this silicidation reaction is promoted to realize a sufficiently low resistance, and TiSi formed on the N-type and P-type gate electrodes 30a and 30b.₂The fine line effect of the film 22b can be suppressed.
[0103]
  In the dual-gate C-MOS transistor manufactured by the present inventor based on this embodiment, the widths of the N-type and P-type gate electrodes 30a and 30b are changed to change the N-type and P-type gate electrodes 30a and 30b. TiSi formed on top₂When the sheet resistance of the film 22b was measured, the same result as that shown in the graph of FIG. 13 in the first embodiment was obtained. That is, TiSi₂The line width dependence of the sheet resistance of the film 22b is not observed including the thin line region, and TiSi formed on the N-type and P-type gate electrodes 30a and 30b.₂It was confirmed that the thin line effect of the film 22b was suppressed. This is because the silicidation reaction between the amorphous silicon film constituting the N-type and P-type gate electrodes 30a and 30b and the Ti film 22 thereon is determined by the N-type and P-type gate electrodes in the first embodiment. As long as it is substantially the same as the silicidation reaction between the upper amorphous silicon films 19a and 19b constituting the layers 20a and 20b and the Ti film 22 thereon, it is natural.
[0104]
  In this way, when the N-type and P-type gate electrodes 30a and 30b made of an amorphous silicon film are formed, the N-type gate electrode 30a is made conductive before the P-type gate electrode 30b is made conductive. TiSi₂The depletion of the N-type gate electrode 30a is suppressed while utilizing the advantages of the amorphous silicon film capable of suppressing the fine line effect of the film 22b, and the N-type and P-type gate electrodes 30a in the dual gate structure, TiSi formed on 30b₂Since the thin line effect of the film 22b and the depletion of the N-type gate electrode 30a can be suppressed at the same time, it is possible to contribute to miniaturization and higher speed of an element having a dual gate structure.
  In addition, since the thickness of the gate electrode is not reduced more than necessary to suppress depletion of the N-type gate electrode 30a, TiSi is formed on the N-type and P-type gate electrodes 30a and 30b.₂When forming the film 22b, TiSi₂It is possible to prevent the breakdown of the gate oxide film 17 from occurring due to partial overgrowth (penetration) of the film 22b.
[0105]
(Fourth embodiment)
  A method for manufacturing a dual-gate C-MOS transistor according to the fourth embodiment of the present invention will be described with reference to FIGS. Here, FIG. 29 to FIG. 34 are process cross-sectional views for explaining the manufacturing method of the C-MOS transistor according to this embodiment, respectively. Note that the structure of the C-MOS transistor manufactured by the method according to the present embodiment is the same as that shown in FIG. The same components as those of the third embodiment are denoted by the same reference numerals, and the description thereof is omitted or simplified.
[0106]
  In the same manner as the steps shown in FIGS. 22 to 23 of the third embodiment, the element isolation oxide film 12 is formed on the Si substrate 11 in the element isolation region, and then separated by the element isolation oxide film 12. In the element region, a P-type well 13 is formed on the surface of the Si substrate 11 in the NMOS region, and an N-type well 14 is formed on the surface of the Si substrate 11 in the PMOS region. Subsequently, a gate electrode 30 made of an amorphous silicon film is formed on the P-type well 13 and the N-type well 14 with a gate oxide film 17 interposed therebetween (see FIG. 29).
  Next, in the same manner as the process shown in FIG. 24 of the third embodiment, a low concentration N is formed on the surface of the P-type well 13 in the NMOS region.^-An impurity region (not shown) is formed, and a low concentration P is formed on the surface of the N-type well 14 in the PMOS region.^-After forming the impurity region (not shown), the gate sidewall 21 made of an insulating film is formed on each side surface of the gate electrode 30 in each of the NMOS region and the PMOS region.
[0107]
  Subsequently, after covering the PMOS region with a resist 31, the resist 31, the element isolation oxide film 12, the gate electrode 30 in the NMOS region, and the gate sidewall 21 on the side surface of the gate electrode 30 are used as masks. For example, As on the surface of the mold well 13⁺Are selectively ion-implanted. The ion implantation conditions at this time are the same as those in the third embodiment. Thus, N^-High-concentration N constituting the source / drain of the LDD structure integrated with the impurity region⁺Impurity regions 15a and 15b are formed. At the same time, the gate electrode 30 in the NMOS region is also As.⁺Is ion-implanted, the gate electrode 30 becomes an N-type gate electrode 30a (see FIG. 30).
[0108]
  Next, after removing the resist 33, a silicon oxide film 34 called HTO (High Temperature Oxide) having a thickness of about several to 100 nm is formed on the entire surface of the substrate by using, for example, a CVD method. This film is formed by SiH_FourGas and N₂Using O gas as the reaction gas, for example
      SiH_FourGas flow rate: 20sccm,
      N₂O gas flow rate: 1200sccm,
      Deposition temperature: 800-850 ° C,
      Deposition time: 1-3 hours,
      Pressure: 80Pa
Perform according to the conditions.
  At the same time, the heat treatment during the formation of the silicon oxide film 34 causes N^-Impurity region and N⁺N-type impurity ions implanted into impurity regions 15a and 15b and N-type gate electrode 30a are activated (see FIG. 31).
[0109]
  Next, after covering the NMOS region with a resist 35, the silicon oxide film 34 is further masked using the resist 35, the element isolation oxide film 12, the gate electrode 30 in the PMOS region, and the gate sidewall 21 on the side surface of the gate electrode 30 as a mask. Through the surface of the N-type well 14 in the PMOS region, for example, BF₂ ⁺Are selectively ion-implanted. The ion implantation conditions at this time are the same as those in the third embodiment. Thus, P^-High concentration of P that constitutes the source / drain of the LDD structure integrally with the impurity region⁺Impurity regions 16a and 16b are formed. At the same time, the BF is applied to the gate electrode 30 in the PMOS region.₂ ⁺Is ion-implanted, the gate electrode 30 becomes a P-type gate electrode 30b. Thus, the BF is formed on the gate electrode 30 and the N-type well 14 surface in the PMOS region.₂ ⁺Is characterized in that the silicon oxide film 34 is used as a screen oxide film for this ion implantation (see FIG. 32).
[0110]
  Next, after removing the resist 35, the silicon oxide film 34 is further removed. The removal of the silicon oxide film 34 can be easily performed by etching using, for example, a hydrofluoric acid chemical solution. At the time of removing the silicon oxide film 34 by etching, N⁺Impurity regions 15a, 15b and P⁺The natural oxide film naturally grown on the impurity regions 16a and 16b and the N-type and P-type gate electrodes 30a and 30b is removed. Subsequently, for example, a Ti film 22 is formed as a refractory metal film on the entire surface of the substrate by vapor deposition. Instead of the Ti film 22, a refractory metal film such as a Co film, a Ni film, or a Pt film may be used (see FIG. 33).
[0111]
  Next, in the same manner as the process shown in FIG. 28 of the third embodiment, N-step annealing is used.⁺Impurity regions 15a, 15b and P⁺The Ti film 22 on the impurity regions 16a and 16b and the N-type and P-type gate electrodes 30a and 30b is silicided. Thus, N⁺Impurity regions 15a, 15b and P⁺TiSi on the impurity region 16a₂The film 22a is formed on the N-type and P-type gate electrodes 30a and 30b with TiSi.₂The films 22b are formed in a self-aligned manner. If a Co film, Ni film, Pt film or the like is used instead of the Ti film 22, TiSi₂CoSi instead of film₂Film and NiSi₂A film, a PtSi film, or the like is formed.
[0112]
  Subsequently, the interlayer insulating film 23 formed on the entire surface of the base is coated with N⁺Impurity regions 15a, 15b and P⁺TiSi on impurity regions 16a and 16b₂Connection holes reaching the film 22a and TiSi on the N-type and P-type gate electrodes 30a, 30b₂The connection holes reaching the film 22b are opened, and TiSi is passed through the W plugs 24 filling the connection holes.₂After the wiring layer 25 connected to the films 22a and 22b is formed, a surface protective film 26 is formed on the entire surface of the substrate (see FIG. 34). Thus, the dual-gate C-MOS transistor according to this embodiment is manufactured.
[0113]
  As described above, according to the present embodiment, the gate electrode 30 in the NMOS region is connected to As.⁺Are selectively implanted to form an N-type gate electrode 30a, and BF is applied to the gate electrode 30 in the PMOS region.₂ ⁺Is selectively implanted to form a P-type gate electrode 30b, a silicon oxide film 34 called HTO is formed using the CVD method. At this time, the film formation temperature is 800 to 850 ° C. Yes, since the film formation time is 1 to 3 hours, As in the third embodiment.⁺N-type gate electrode in the NMOS region without causing deterioration of transistor characteristics such as punch-through and short channel effect in the PMOS transistor, because the same activation effect as in the case of performing the heat treatment for activating the transistor is obtained. Since As can be sufficiently diffused throughout the entire 30a, the depletion of the N-type gate electrode 30a, which tends to cause particularly significant depletion, is suppressed as in the case of the third embodiment. be able to.
[0114]
  Similarly to the case of the third embodiment, since the N-type and P-type gate electrodes 30a and 30b are made of an amorphous silicon film, TiSi formed on the N-type and P-type gate electrodes 30a and 30b.₂Since the thin line effect of the film 22b can be suppressed, TiSi formed on the N-type and P-type gate electrodes 30a and 30b.₂The thin line effect of the film 22b and the depletion of the N-type gate electrode 30a can be suppressed at the same time, and the same effect as in the case of the third embodiment can be achieved.
  Further, according to the present embodiment, the surface of the N-type well 14 in the PMOS region and the gate electrode 30 are BF.₂ ⁺When selectively ion-implanting ions, ion implantation is performed through the silicon oxide film 34 so that the silicon oxide film 34 becomes BF.₂ ⁺Since it functions as a screen oxide film for ion implantation, even if the diffusion coefficient of B is large, the high concentration P constituting the source / drain of the PMOS transistor⁺The junction depth of the impurity regions 16a and 16b can be easily reduced, and the transistor characteristics can be improved.
[0115]
【The invention's effect】
  As described above in detail, according to the semiconductor device and the manufacturing method thereof according to the present invention, the following effects can be obtained.
[0116]
  Claims1According to the method for manufacturing a semiconductor device according to the present invention, a gate electrode having a two-layer structure of a lower polycrystalline silicon film and an upper amorphous silicon film is formed, and a refractory metal film deposited on the gate electrode By forming a refractory metal silicide film on the gate electrode in a self-aligned manner by, for example, siliciding by heat treatment, a polycrystalline silicon film into which impurity ions are implanted deep along the crystal grains is formed into the gate electrode. Therefore, an impurity is diffused uniformly in the entire gate electrode, so that depletion of the gate electrode can be suppressed, and an amorphous silicon film that facilitates silicidation reaction is formed as an upper layer of the gate electrode. Therefore, a sufficiently low resistance is realized, and the thin line effect of the refractory metal silicide film formed on the gate electrode can be suppressed. Therefore, it is possible to manufacture a MIS transistor capable of realizing high driving capability as well as miniaturization and high speed.
  In addition, since it is not necessary to reduce the thickness of the gate electrode more than necessary in order to suppress the depletion of the gate electrode, a part of the refractory metal silicide film is formed when the refractory metal silicide film is formed on the gate electrode. The breakdown voltage of the gate oxide film due to excessive overgrowth (penetration) can be prevented. Furthermore, since it is not necessary to perform high-temperature and long-time heat treatment at the time of impurity ion activation in order to suppress depletion of the gate electrode, punch-through and short-channel effects due to diffusion of impurities with a large diffusion coefficient particularly in PMOS transistors Can be prevented, and deterioration of transistor characteristics can be prevented.
[0117]
  Also,Double layer filmA predetermined impurity ion is previously implanted into the polycrystalline silicon film constituting the lower layer of the gate electrode having a structure, and then the same kind of impurity is added again to the entire gate electrode, so that the impurity concentration in the lower layer tends to decrease. Since the concentration can be increased, the impurity concentration of the entire gate electrode is made uniform, and depletion of the gate electrode can be suppressed more effectively.
[0118]
  Claims2According to the method for manufacturing a semiconductor device according to the present invention, the first conductivity type and the second conductivity type gate electrodes having a two-layer film structure of the lower polycrystalline silicon film and the upper amorphous silicon film are formed. Even if a dual gate structure having both N-type and P-type gate electrodes by forming a refractory metal silicide film on the first conductivity type and second conductivity type gate electrodes in a self-aligned manner, the gate electrode By using the advantages of a polycrystalline silicon film that can suppress depletion of the amorphous silicon film and the advantage of an amorphous silicon film that can suppress the thin line effect of a refractory metal silicide film, it was formed on the gate electrode. Since the thin line effect of the refractory metal silicide film and the depletion of the gate electrode can be suppressed at the same time, it is possible to contribute to miniaturization and higher speed of the MIS transistor having a dual gate structure.
[0119]
  Also,Double layer filmOf the first and second gate electrodes having the structure, after first implanting impurity ions of the first conductivity type into the polycrystalline silicon film constituting the lower layer of the first gate electrode, the entire first gate electrode is reintroduced. By adding the same kind of impurities, it becomes possible to increase the impurity concentration of the lower layer, which tends to decrease the impurity concentration, so that the impurity concentration of the entire first gate electrode is made uniform and more effective. Depletion of the first gate electrode can be suppressed.
[0120]
  Claims3According to the method for manufacturing a semiconductor device according to the present invention, N-type impurity ions are implanted in advance into the polycrystalline silicon film constituting the lower layer of the first gate electrode out of the first and second gate electrodes having a two-layer film structure. After that, by adding an N-type impurity again to the entire first gate electrode, the impurity concentration in the lower layer of the N-type gate electrode, which tends to cause depletion of the gate electrode in particular, is increased, and it is more effective. In addition, depletion of the N-type gate electrode can be suppressed.
[0121]
  Claims4According to the method for manufacturing a semiconductor device according to the present invention, N-type impurity ions are implanted in advance into the polycrystalline silicon film constituting the lower layer of the first gate electrode out of the first and second gate electrodes having a two-layer film structure. Subsequently, P-type impurity ions are implanted in advance into the polycrystalline silicon film constituting the lower layer of the second gate electrode, and then the N-type and P-type impurities are respectively added to the entire first and second gate electrodes. By adding, not only the N-type impurity concentration in the lower layer of the N-type gate electrode but also the P-type impurity concentration in the lower layer of the P-type gate electrode is increased, so that both the N-type and P-type gate electrodes can be more effectively performed. Can be suppressed.
[0122]
  Further, since the second heat treatment for activating the P-type impurity ions is performed separately from the first heat treatment for activating the N-type impurity ions, punch-through due to the diffusion of the P-type impurities having a large diffusion coefficient and the short channel effect. It is possible to set conditions for suppressing the occurrence by using the conventional technique, and it is possible to prevent deterioration of transistor characteristics. Furthermore, since it is not necessary to reduce the thickness of the gate electrode in order to suppress depletion of the gate electrode, partial overgrowth of the refractory metal silicide film when the refractory metal silicide film is formed on the gate electrode. It is possible to prevent the breakdown voltage of the gate oxide film from being deteriorated due to (penetration) and to prevent the transistor characteristics from being deteriorated.
[0123]
  Claims5According to the manufacturing method of the semiconductor device according toAmorphousFirst and second gate electrodes made of a silicon film are formed, N-type impurity ions are selectively implanted into the first gate electrode, and then the insulating film is subjected to heat treatment conditions sufficient to activate the N-type impurity ions. Then, P-type impurity ions are selectively implanted into the second gate electrode through this insulating film and activated by a second heat treatment, and a refractory metal silicide is formed on these N-type and P-type gate electrodes. Since the film is formed in a self-aligned manner, the N-type and P-type gate electrodes are formed from an amorphous silicon film in which the silicidation reaction is easily promoted.While the fine line effect of the refractory metal silicide film formed on the N-type and P-type gate electrodes can be suppressed,In addition, since the P-type impurity is not yet added to the second gate electrode when forming the insulating film for activating the N-type impurity ions implanted into the first gate electrode,N-type impurities can be sufficiently diffused throughout the first gate electrode, and depletion of the N-type gate electrode, which tends to be particularly noticeable, can be suppressed.
  The insulating film formed after the N-type impurity ions are implanted into the first gate electrode serves as a screen oxide film when the P-type impurity ions are selectively implanted into the second gate electrode. The junction depth of the P-type impurity region to which a large P-type impurity is added can be easily reduced, and the transistor characteristics can be improved.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a dual-gate C-MOS transistor according to a first embodiment.
2 is a process cross-sectional view (No. 1) for describing a method of manufacturing the C-MOS transistor of FIG. 1; FIG.
3 is a process cross-sectional view (No. 2) for describing the method of manufacturing the C-MOS transistor of FIG. 1; FIG.
FIG. 4 is a process cross-sectional view (part 3) for explaining the method of manufacturing the C-MOS transistor of FIG. 1;
5 is a process cross-sectional view (No. 4) for describing the method of manufacturing the C-MOS transistor of FIG. 1; FIG.
6 is a process cross-sectional view (No. 5) for explaining the manufacturing method of the C-MOS transistor of FIG. 1; FIG.
7 is a process cross-sectional view (No. 6) for describing the method of manufacturing the C-MOS transistor of FIG. 1; FIG.
8 is a process cross-sectional view (No. 7) for describing the method of manufacturing the C-MOS transistor of FIG. 1; FIG.
9 is a process sectional view (No. 8) for explaining the production method of the C-MOS transistor of FIG. 1; FIG.
10 is a process cross-sectional view (No. 9) for explaining the method of manufacturing the C-MOS transistor of FIG. 1; FIG.
11 is a process cross-sectional view (No. 10) for describing the method of manufacturing the C-MOS transistor of FIG. 1; FIG.
12 is a process sectional view (No. 11) for explaining the production method of the C-MOS transistor of FIG. 1; FIG.
13 is a graph showing the relationship between the gate electrode width and sheet resistance of the C-MOS transistor of FIG. 1;
FIG. 14 is a graph showing the relationship between the width of an impurity region and a gate electrode and a sheet resistance in a comparative example of the first embodiment.
FIG. 15 is a cross-sectional view showing a dual-gate C-MOS transistor according to a second embodiment.
16 is a process cross-sectional view (No. 1) for describing the method of manufacturing the C-MOS transistor of FIG. 15; FIG.
FIG. 17 is a process cross-sectional view (part 2) for explaining the method of manufacturing the C-MOS transistor of FIG. 15;
FIG. 18 is a process cross-sectional view (part 3) for explaining the method of manufacturing the C-MOS transistor of FIG. 15;
FIG. 19 is a process cross-sectional view (part 4) for explaining the method of manufacturing the C-MOS transistor of FIG. 15;
FIG. 20 is a process cross-sectional view (part 5) for explaining the method of manufacturing the C-MOS transistor of FIG. 15;
FIG. 21 is a cross-sectional view showing a dual-gate C-MOS transistor according to a third embodiment.
FIG. 22 is a process cross-sectional view (No. 1) for describing the method of manufacturing the C-MOS transistor of FIG. 21;
FIG. 23 is a process cross-sectional view (part 2) for explaining the method of manufacturing the C-MOS transistor of FIG. 21;
FIG. 24 is a process cross-sectional view (part 3) for explaining the method of manufacturing the C-MOS transistor of FIG. 21;
FIG. 25 is a process cross-sectional view (part 4) for explaining the method of manufacturing the C-MOS transistor of FIG. 21;
FIG. 26 is a process cross-sectional view (part 5) for explaining the method of manufacturing the C-MOS transistor of FIG. 21;
FIG. 27 is a process cross-sectional view (No. 6) for describing the method of manufacturing the C-MOS transistor of FIG. 21;
FIG. 28 is a process cross-sectional view (part 7) for explaining the method of manufacturing the C-MOS transistor of FIG. 21;
FIG. 29 is a process cross-sectional view (No. 1) for describing the method of manufacturing the dual-gate C-MOS transistor according to the third embodiment;
FIG. 30 is a process cross-sectional view (part 2) for explaining the method of manufacturing the dual-gate C-MOS transistor according to the third embodiment;
FIG. 31 is a process cross-sectional view (part 3) for explaining the method of manufacturing the dual-gate C-MOS transistor according to the third embodiment;
FIG. 32 is a process cross-sectional view (No. 4) for explaining the method of manufacturing the dual-gate C-MOS transistor according to the third embodiment;
FIG. 33 is a process cross-sectional view (part 5) for explaining the method of manufacturing the dual-gate C-MOS transistor according to the third embodiment;
FIG. 34 is a process cross-sectional view (No. 6) for explaining the method of manufacturing the dual-gate C-MOS transistor according to the third embodiment;
FIG. 35 is a process cross-sectional view (No. 1) for describing the method of manufacturing the dual-gate C-MOS transistor using the conventional salicide technology.
FIG. 36 is a process cross-sectional view (No. 2) for describing the method of manufacturing the dual-gate C-MOS transistor using the conventional salicide technology.
FIG. 37 is a process cross-sectional view (No. 3) for explaining the method of manufacturing the dual-gate C-MOS transistor using the conventional salicide technique.
FIG. 38 is a process cross-sectional view (No. 4) for describing the method of manufacturing the dual-gate C-MOS transistor using the conventional salicide technology.
FIG. 39 is a process cross-sectional view (No. 5) for describing the method of manufacturing the dual-gate C-MOS transistor using the conventional salicide technology.
[Explanation of symbols]
  11 · Si substrate, 12 · Oxide film for element isolation, 13 · P type well, 14 · N type well, 15a, 15b · N⁺Impurity region, 16a, 16b · P⁺Impurity region, 17, gate oxide film, 18, 18a, 18b, 18c, 18d polycrystalline silicon film, 19, 19a, 19b amorphous silicon film, 20 gate electrode, 20a, 20c, 20d N gate Electrode, 20b · P-type gate electrode, 21 · gate sidewall, 22 · Ti film, 22a, 22b · TiSi₂Film, 23. interlayer insulating film, 24. W plug, 25. wiring layer, 26. surface protective film, 30. gate electrode, 30a. N type gate electrode, 30b. P type gate electrode, 31. resist, 32. resist 33, resist, 34, silicon oxide film, 35, resist, 51, Si substrate, 52, oxide film for element isolation, 53, P type well, 54, N type well, 55, gate oxide film, 56, gate electrode 56a · N type gate electrode, 56b · P type gate electrode, 57 · gate sidewall, 58 · silicon oxide film, 59 · resist, 60a, 60b · N⁺Impurity region, 61 · resist, 62a, 62b · P⁺Impurity region, 63 · Ti film, 63a, 63b · TiSi₂Film, 64. interlayer insulating film, 65. W plug, 66. wiring layer, 67. surface protective film.

Claims (5)

Forming a polycrystalline silicon film on the semiconductor substrate through a gate insulating film, and then implanting predetermined impurity ions into the polycrystalline silicon film; and forming an amorphous silicon film on the polycrystalline silicon film Thereafter, the amorphous silicon film and the polycrystalline silicon film are patterned into a predetermined shape to form a gate electrode having a two-layer film structure of the lower polycrystalline silicon film and the upper amorphous silicon film. A first step of forming;
Adding a predetermined impurity to the surface of the semiconductor substrate and the gate electrode to form an impurity region, and making the gate electrode conductive;
After depositing a refractory metal film over the entire surface of the substrate, the refractory metal film on the impurity region and the gate electrode is silicided by heat treatment, and the unreacted refractory metal film is removed by etching, A third step of forming a refractory metal silicide film on the impurity region and on the gate electrode in a self-aligning manner;
A method for manufacturing a semiconductor device, comprising: After a polycrystalline silicon film is formed on the semiconductor substrate in the first and second element regions via a gate insulating film, impurity ions of the first conductivity type are selected in the polycrystalline silicon film in the first element region Implanting and forming an amorphous silicon film on the polycrystalline silicon film, and then patterning the amorphous silicon film and the polycrystalline silicon film into a predetermined shape to form the underlying polycrystalline film A first step of forming first and second gate electrodes having a two-layer structure of a silicon film and an upper amorphous silicon film in the first and second element regions, respectively;
Impurity ions of a first conductivity type are selectively implanted into the surface of the semiconductor substrate and the first gate electrode in the first element region, and the surface of the semiconductor substrate and the second gate in the second element region. After the second conductivity type impurity ions are selectively implanted into the electrodes, the impurity ions are activated by heat treatment, so that the first conductivity type and the second conductivity type impurity regions are respectively formed in the first and second element regions. A second step of forming the first and second gate electrodes into gate electrodes of the first conductivity type and the second conductivity type, respectively,
After the refractory metal film is deposited on the entire surface of the substrate, the refractory metal film on the first conductivity type and second conductivity type impurity regions and on the first conductivity type and second conductivity type gate electrodes is formed by heat treatment. In addition to silicidation, the unreacted refractory metal film is removed by etching, so that the high-concentration on the first conductivity type and second conductivity type impurity regions and on the first conductivity type and second conductivity type gate electrodes. A third step of forming a melting point metal silicide film in a self-aligning manner;
A method for manufacturing a semiconductor device, comprising: The method of manufacturing a semiconductor device according to claim 2 .
The semiconductor device manufacturing method, wherein the first conductivity type impurity ions selectively implanted into the polycrystalline silicon film in the first element region are N type impurity ions. In the manufacturing method of the semiconductor device according to claim 3 ,
After the step of selectively implanting N-type impurity ions into the polycrystalline silicon film in the first element region, P-type impurity ions are selectively implanted into the polycrystalline silicon film in the second element region. The manufacturing method of the semiconductor device characterized by comprising the process. After depositing an amorphous silicon film via a gate insulating film on the semiconductor substrate in the first and second element regions, the amorphous silicon film is patterned into a predetermined shape, and the amorphous silicon film A first step of forming first and second gate electrodes comprising:
After selectively implanting N-type impurity ions into the surface of the semiconductor substrate and the first gate electrode in the first element region, the entire surface of the substrate is formed by a vapor phase growth method under a heat treatment condition for activating the N-type impurity ions. forming an insulating film, thereby forming an N-type impurity regions simultaneously on the semiconductor substrate surface of the first element region, a second step of the first gate electrode to the N-type gate electrode,
After selectively injecting P-type impurity ions into the surface of the semiconductor substrate and the second gate electrode in the second element region through the insulating film, the P-type impurity ions are activated by a predetermined heat treatment, and the first A third step of forming a P-type impurity region on the surface of the semiconductor substrate of the second element region and making the second gate electrode a P-type gate electrode ;
After the insulating film is removed, a refractory metal film is deposited on the entire surface of the substrate, and then the refractory metal film on the N-type and P-type impurity regions and the N-type and P-type gate electrodes is silicided by heat treatment. In addition, the unreacted refractory metal film is removed by etching, and a refractory metal silicide film is formed in a self-aligned manner on the N-type and P-type impurity regions and on the N-type and P-type gate electrodes. 4 steps and
A method for manufacturing a semiconductor device , comprising :

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