JP4403115B2 - Display device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a display device using polysilicon and a manufacturing method thereof, and more particularly to a liquid crystal display device capable of simplifying the process and a manufacturing method thereof.

  In general, in a liquid crystal display device, each of liquid crystal cells arranged in a matrix on a liquid crystal display panel (hereinafter referred to as a liquid crystal panel) displays an image by adjusting light transmittance according to a video signal.

  A thin film transistor (hereinafter referred to as TFT) is used as a switching element for independently supplying a video signal to each liquid crystal cell. As the active layer of such a TFT, amorphous silicon or polysilicon is used. Here, in the case of using polysilicon whose charge mobility is about 100 times faster than that of amorphous silicon, a driving circuit requiring a high response speed can be incorporated in the liquid crystal panel.

  FIG. 1 is a diagram schematically showing a TFT substrate of a conventional poly liquid crystal panel with a built-in drive circuit.

  The polysilicon TFT substrate shown in FIG. 1 has an image display area 7 in which a TFT 30 and a pixel electrode 22 are formed for each pixel area defined by the intersection of the gate line 2 and the data line 4, and data in the image display area 7. A data driver 5 for driving the line 4 and a gate driver 3 for driving the gate line 2 in the image display area 7 are provided.

  The image display area 7 includes a TFT 30 and a pixel electrode 22 formed in each of the pixel areas defined by the intersections of the plurality of gate lines 2 and the data lines 4. The TFT 30 charges the pixel electrode 22 with the video signal from the data line 4 in response to the scan signal of the gate line 2. The pixel electrode 22 charged with the video signal generates a potential difference with the common electrode of the color filter substrate facing the TFT substrate and the liquid crystal, and the liquid crystal molecules rotate due to the dielectric anisotropy due to the potential difference. The gray level is realized by changing the light transmittance according to the degree of rotation of the liquid crystal molecules.

  The gate driver 3 sequentially drives the gate lines 2.

  The data driver 5 supplies a video signal to the data line 4 every time the gate line 2 is driven.

  FIG. 2 is an enlarged plan view showing one pixel region included in the image display region 7 of the polysilicon TFT substrate shown in FIG. 1, and FIG. 3 is a line II ′ of the pixel region of the TFT substrate shown in FIG. It is sectional drawing which follows.

  The TFT substrate shown in FIGS. 2 and 3 includes a TFT 30 connected to the gate line 2 and the data line 4 and a pixel electrode 22 connected to the TFT 30. The TFT 30 is formed of an NMOS-TFT or a PMOS-TFT, but only the case where it is formed of an NMOS-TFT will be described below.

  The TFT 30 includes a gate electrode 6 connected to the gate line 2, a source electrode included in the data line 4, and a drain electrode 10 connected to the pixel electrode 22 through a pixel contact hole 20 that penetrates the protective film 18. The gate electrode 6 is formed so as to overlap with the channel region 14C of the active layer 14 formed on the buffer film 12 with the gate insulating film 16 interposed therebetween. The source and drain electrodes 10 are formed with the gate electrode 6 and the interlayer insulating film 26 interposed therebetween. The source and drain electrodes 10 are connected to the source region 14S of the active layer 14 into which n + impurities are implanted through the source contact hole 24S and the drain contact hole 24D that penetrate the interlayer insulating film 26 and the gate insulating film 16, respectively. And the drain region 14D.

  Such an image display region 32 of the polysilicon type TFT substrate is formed by a six mask process as follows.

  Specifically, the buffer film 12 is formed on the lower substrate 1 by the first mask process, and the active layer 14 is formed thereon. The active layer 14 is formed by depositing amorphous silicon on the buffer film 12 and crystallizing with laser to form polysilicon, and then patterning the polysilicon layer by a photolithography process and an etching process using a first mask. It is formed.

  In the second mask process, the gate insulating film 16 is formed on the buffer film 12 on which the active layer 14 is formed, and the gate line 2 and the gate electrode 6 are formed thereon. Then, using the gate electrode 6 as a mask, an n + impurity is implanted into the non-overlapping region of the active layer 14 to form the source region 14S and the drain region 14D of the active layer 14.

  In the third mask process, an interlayer insulating film 26 is formed on the gate insulating film 16 on which the gate line 2 and the gate electrode 6 are formed, and a source contact hole 24S and a drain contact penetrating the interlayer insulating film 26 and the gate insulating film 16 are formed. A hole 24D is formed.

  In the fourth mask process, the data line 4 and the drain electrode 10 including the source electrode are formed on the interlayer insulating film 26.

  In the fifth mask process, the protective film 18 is formed on the interlayer insulating film 26 on which the data line 4 and the drain electrode 10 are formed, and the pixel contact hole 20 that penetrates the protective film 18 and exposes the drain electrode 10 is formed. The

  In the sixth mask process, a transparent pixel electrode 22 connected to the drain electrode 10 through the pixel contact hole 20 is formed on the protective film 18.

  Thus, since the image display region 7 of the conventional polysilicon type TFT substrate is formed by the six mask process, there is a problem that the manufacturing process is complicated. This is because one mask process includes many processes such as a thin film deposition process, a cleaning process, a photolithography process, an etching process, a photoresist stripping process, and an inspection process.

  Further, in the conventional polysilicon type TFT substrate, when the gate driver 3 and the data driver 5 are formed together with the image display region 7, a CMOS-TFT has to be formed. Therefore, the number of steps increases to 9 mask steps. The manufacturing process is further complicated. Therefore, in order to reduce costs, a method that can reduce the number of mask processes for the poly TFT substrate is necessary.

  Therefore, the present invention has been made in view of the above-described points, and provides a display device that can simplify the process and a manufacturing method thereof.

In order to achieve the above object, a display device according to the present invention is formed in a substrate having an image display region and a driver region, a first active layer formed in the image display region on the substrate, and the driver region. Second active layer and third active layer, a first insulating film formed on the first to third active layers, and on the first insulating film corresponding to the first to third active layers. A first conductive film including a first gate electrode, a second gate electrode, and a third gate electrode, a gate line and a pixel electrode connected to the first gate electrode, and the first conductive film are formed. A second insulating film formed on the first insulating film and formed with a contact hole exposing the source and drain regions of the first to third active layers and a transmission hole exposing the pixel electrode; Formed on an insulating film, First to third source electrodes and first to third drain electrodes connected to the source and drain regions of the third active layer, respectively, and a second conductive pattern including a data line connected to the first source electrode; The first to third gate electrodes, the gate line, and the pixel electrode have a double layer structure in which a metal layer is formed on the transparent conductive layer, and the transparent conductive layer of the pixel electrode includes the pixel characterized in that it is exposed through the transparent hole penetrating the insulating layer and the metal layer in the region.

  In addition, the method for manufacturing a display device according to the present invention includes a step of forming first to third active layers on a substrate, a step of forming a first insulating film on the active layer, the first gate electrode, A double layer including a second gate electrode and a third gate electrode, a gate line connected to the first gate electrode, and a pixel electrode on the first insulating film, wherein the metal layer is formed on the transparent conductive layer Forming a first conductive pattern having a structure; forming source and drain regions doped with a first impurity on the first active layer and the second active layer; and forming on the third active layer. Forming source and drain regions doped with a second impurity; forming a second insulating film on the first conductive pattern; and source and drain regions of the first, second and third active layers Source and drain contour to expose Forming a through hole to expose the transparent conductive layer of the pixel electrode, and first, second and third connected to the source and drain regions of the first, second and third active layers. Forming a second conductive pattern including a third source and drain region and a data line, wherein the first drain electrode is connected to the transparent conductive layer of the pixel electrode.

  The display device and the manufacturing method thereof according to the present invention can reduce the number of steps to seven mask steps while forming the drive circuit together with the image display region. Thereby, it is possible to reduce the cost of materials and capital investment and improve the yield.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  4 is a plan view showing a part of a poly TFT substrate according to an embodiment of the present invention, and FIG. 5 is a cross-sectional view taken along lines III-III ′ and IV-IV ′ of the TFT substrate shown in FIG.

  4 and 5 includes an image display area 196, a gate driver 194 that drives the gate line 102 in the image display area 196, and a data driver 192 that drives the data line 104.

  The image display area 196 includes a TFT 130 connected to the gate line 102 and the data line 104, a pixel electrode 122 and a storage capacitor 160 connected to the TFT 130. The TFT 130 is formed of an NMOS-TFT or a PMOS-TFT, but only the case where it is formed of an NMOS-TFT will be described below. Therefore, the TFT 130 in the image display area 196 is defined as the first NMOS-TFT 130.

  The data line 104 defines a pixel region where the pixel electrode 122 is formed by crossing the gate line 102 and the storage line 152 with the interlayer insulating film 118 interposed therebetween.

  The first NMOS-TFT 130 supplies the video signal of the data line 104 to the pixel electrode 122 in response to the gate signal of the gate line 102. For this, the first NMOS-TFT 130 includes a first gate electrode 106 connected to the gate line 102, a first source electrode included in the data line 104, and a first drain electrode 110 connected to the pixel electrode 122. And a first active layer 114 that forms a channel between the first source electrode and the first drain electrode 110.

  Here, the gate line 102 and the first gate electrode 106 have a double-layer structure in which the transparent conductive layer 101 and the metal layer 103 are stacked thereon together with the storage line 152.

The first active layer 114 is formed on the lower substrate 100 with the buffer film 112 interposed therebetween.
The first active layer 114 includes a channel region 114C that is overlapped with the first gate electrode 106 with the gate insulating film 116 interposed therebetween, and a source region 114S and a drain region 114D into which n + impurities are implanted with the channel region 114C interposed therebetween. Prepare. The source region 114S and the drain region 114D of the first active layer 114 are included in the data line 104 through the first source contact hole 124S and the first drain contact hole 124D penetrating the interlayer insulating film 118 and the gate insulating film 116. The first source electrode and the first drain electrode 110 are connected to each other. The first active layer 114 further includes an LDD (Lightly Doped Drain) region in which an n− impurity is implanted between the channel region 114C, the source region 114S, and the drain region 114D in order to reduce the off current.

  The pixel electrode 122 includes a transparent conductive layer 101 formed on the gate insulating film 116 in the pixel region, and a metal layer 103 remaining along the frame on the transparent conductive layer 101. In other words, the transparent conductive layer 101 of the pixel electrode 122 is exposed through the transmission hole 120 that penetrates the interlayer insulating film 118 and the metal layer 103. In contrast, the pixel electrode 122 may be formed of only the transparent conductive layer 101 without the remaining metal layer 103. The pixel electrode 122 is connected to the first drain electrode 110 extending from the TFT 130 along the side surface of the transmission hole 120 across the storage line 152. Specifically, the first drain electrode 110 is connected to the metal layer 103 and the transparent conductive layer 101 of the pixel electrode 122 exposed through the transmission hole 120. The pixel electrode 122 charges the video signal supplied from the thin film transistor 130 and generates a potential difference with a common electrode formed on a color filter substrate (not shown). Due to this potential difference, the liquid crystal positioned on the thin film transistor substrate and the color filter substrate is rotated by the dielectric anisotropy, and the transmission amount of light incident from the light source (not shown) via the pixel electrode 122 is adjusted, so that the color filter substrate Permeate toward.

  The storage capacitor 160 includes first and second storage capacitors Cst1 and Cst2 connected in parallel between the storage line 152 and the TFT 130. The first storage capacitor Cst1 is formed such that the storage line 152 overlaps the storage lower electrode 150 extending from the first active layer 114 and the gate insulating film 116 therebetween. The second storage capacitor Cst2 is formed such that the first drain electrode 110 intersects the storage line 152 with the interlayer insulating film 118 interposed therebetween. The storage capacitor 160 whose capacity is increased by the parallel connection of the first and second storage capacitors Cst1 and Cst2 allows the video signal charged in the pixel electrode 120 to be stably maintained.

  The gate driver 194 and the data driver 192 include a second NMOS-TFT 180 and a PMOS-TFT 190 connected in a CMOS structure.

  The second NMOS-TFT 180 includes a second active layer 144 formed on the buffer film 112, a second gate electrode 136 superimposed on the channel region of the second active layer 144 with the gate insulating film 116 interposed therebetween, and a second source contact hole. The second source electrode 138 and the second drain electrode 140 are connected to the source region and the drain region of the second active layer 144 via the 154S and the second drain contact hole 154D. The second active layer 144 further includes a channel region and an LDD region into which an n− impurity is implanted between the source region and the drain region in order to reduce off current. Such a second NMOS-TFT 180 is formed in the same structure as the first NMOS-TFT 130 formed in the image display area 196.

  The second PMOS-TFT 190 includes a third active layer 174 formed on the buffer film 112, a third gate electrode 166 superimposed on the channel region 174C of the third active layer 174 across the gate insulating film 116, and a third source contact. A third source electrode 168 and a third drain electrode 170 connected to the source region 174S and the drain region 174D of the third active layer 174 through the hole 184S and the third drain contact hole 184D are provided. Here, the source region 174S and the drain region 174D of the third active layer 174 are formed by implanting p impurities.

  As described above, in the polysilicon type TFT substrate according to the present invention, the pixel electrode 122 has the gate insulating film together with the gate line 102 having the double layer structure, the first to third gate electrodes 106, 136, 166 and the storage line 152. By being formed on 116, the process can be simplified. As a result, the source / drain metal pattern including the data line 104 including the first source electrode, the second and third source electrodes 138 and 168, and the first to third drain electrodes 110, 140, and 170 is exposed. However, such a source / drain metal pattern can be protected by being positioned in a region sealed by a sealing material. For example, the source / drain metal pattern formed in the region sealed by the sealing material can be sufficiently protected not only by the alignment film applied thereon but also by the liquid crystal formed in the sealing region.

  6A to 6G are cross-sectional views illustrating a method for manufacturing a polysilicon TFT substrate according to an embodiment of the present invention. Here, since the second NMOS-TFT 180 included in the gate driver 194 and the data driver 192 has the same structure as the first NMOS-TFT 130 in the image display region 196, it will not be shown, but will be described with reference to FIG. .

  Referring to FIG. 6A, a buffer film 112 is formed on the lower substrate 100, and a first active layer 114 and a storage lower electrode 150 are formed on the image display region. An active layer 144 (not shown) and a 3174th layer are formed in the driver region.

The buffer film 112 is formed by depositing an inorganic insulating material such as SiO ₂ on the entire surface of the lower substrate 100.

  Next, an amorphous silicon thin film is formed on the buffer film 112 by a method such as LPVD (Low Pressure Chemical Vapor Deposition) or PECVD (Plasma Enhanced Chemical Vapor Deposition), and then crystallized to form a polysilicon thin film. At this time, a dehydrogenation step for removing hydrogen atoms present in the amorphous silicon thin film can be performed before the crystallization of the amorphous silicon thin film. As a method for crystallizing amorphous silicon thin film, one of excimer laser annealing methods is the sequential lateral direction which improves the size of grains by scanning the line beam laterally and growing the grains laterally. The crystallization (SLS: Sequential Lateral Solidification) method is mainly used.

  Then, a first active layer 114 and a storage lower electrode 150 are formed in the image display region by patterning the polysilicon thin film by a photolithography process and an etching process using the first mask, and the second active layer 144 ( And a third active layer 174 are formed in the driver region.

  Referring to FIG. 6B, an n + impurity is implanted into the storage lower electrode 150 using the second mask process so as to have conductivity.

  Specifically, a photoresist pattern that exposes the storage lower electrode 150 is formed by a photolithography process using the second mask, and n + impurities are implanted into the exposed storage lower electrode 150, thereby forming the storage lower electrode 150. Make it conductive. Then, the photoresist pattern is removed by a strip process.

  Referring to FIG. 6C, a gate insulating layer 116 is formed on the buffer layer 112 where the first to third active layers 114 and 144 (not shown) and 174 and the storage lower electrode 150 are formed. Through the third mask process, the pixel electrode 122 is formed together with the gate line 102 having the double layer structure, the first to third gate electrodes 106, 136, and 166 and the storage line 152.

The gate insulating film 116 is formed on the entire surface of the buffer film 112 on which the first to third active layers 114 and 144 (not shown) and 174 and the storage lower electrode 150 are formed, such as SiO _2. It is formed by vapor deposition.

  Subsequently, the transparent conductive layer 101 and the metal layer 103 are stacked on the gate insulating film 116 by a sputtering method or the like. As the transparent conductive layer 101, ITO (Indium Tin Oxide), TO (Tin Oxide), ITZO (Indium Tin Zinc Oxide), IZO (Indium Zinc Oxide) or the like is used, and as the metal layer 103, Mo, Ti, Cu Metal materials such as AlNd, Al, Cr, Mo alloy, Cu alloy, Al alloy, etc. are used in a single layer or at least a double layer structure. Next, the metal layer 103 and the transparent conductive layer 101 are patterned by a photolithography process and an etching process using the second mask, so that the gate line 102 having the double layer structure and the first to third gate electrodes 106 are formed. The pixel electrode 122 is formed together with 136 (not shown), 166 and the storage line 152.

  Referring to FIG. 6D, a source region 114S and a drain region 114D of first and second active layers 114 and 144 (not shown) and an LDD region are formed by a fourth mask process.

  Specifically, an nD region is formed in the exposed portions of the first active layer 114 and the second active layer 144 (not shown) using the first and second gate electrodes 106 and 136 (not shown) as a mask. Impurities are implanted.

  Subsequently, a photoresist pattern exposing the source region 114S and the drain region 114D of the first and second active layers 114 and 144 is formed by a photolithography process using a fourth mask, and the exposed source region 114S and drain are exposed. An n + impurity is implanted into the region 114D. The source region 114S and the drain region 114D of the first and second active layers 114 and 144 sandwich the channel region 114C overlapped with the gate electrodes 106 and 136 and the LDD region into which only the n− impurity is implanted. Located at. Then, the photoresist pattern is removed by a strip process.

  Referring to FIG. 6E, a source region 174S and a drain region 174D of the third active layer 174 are formed by implanting p + impurities into the third active layer 174 through a fifth mask process.

  Specifically, a photoresist pattern exposing both side regions and the drain region 174D of the third active layer 174 is formed by a photolithography process using a fifth mask. A source region 174S and a drain region 174D of the third active layer 174 are formed by implanting p + impurity into both side regions of the exposed third active layer 174. The source and drain regions 174S and 174D of the third active layer 174 are located with a channel region 174C overlapping with the third gate electrode 166 interposed therebetween. Next, the photoresist pattern is removed by a strip process.

  Referring to FIG. 6F, a sixth mask process is performed on the gate insulating layer 116 on which the gate line 102, the gate electrodes 106, 136 (not shown), 166, the storage line 152, and the pixel electrode 122 are formed. An interlayer insulating film 118 having drain contact holes 124S, 124D, 154S, 154D, 184S, 184D and a transmission hole 120 is formed.

The interlayer insulating film 118 is formed of an inorganic material such as SiO ₂ or SiNx on the gate insulating film 116 on which the gate line 102, the gate electrodes 106, 136 (not shown), 166, the storage line 152, and the pixel electrode 122 are formed. An insulating material is deposited on the entire surface.

  Subsequently, first to third source contact holes 124S, 154S (not shown), 184S, first through the interlayer insulating film 118 and the gate insulating film 116 are formed by a photolithography process and an etching process using a sixth mask. Through the third drain contact holes 124D, 154D (not shown), 184D, and the transmission holes 120 penetrating the interlayer insulating film 118 are formed. The first to third source contact holes 124S, 154S, 184S expose the source regions 114S, 174S of the first to third active layers 114, 144, 174, respectively, and the first to third drain contact holes 124D, 154D, 184D exposes the drain regions 114D and 174D of the first to third active layers 114, 144, and 174, respectively. The transmission hole 120 exposes the metal layer 103 that is the upper layer of the pixel electrode 122.

  Next, the transparent conductive layer 101 is exposed by etching the metal layer 103 of the pixel electrode 122 exposed through the transmission hole 120. At this time, the metal layer 103 superimposed on the interlayer insulating film 118 may remain in the periphery of the transparent conductive layer 101.

  Referring to FIG. 6G, the data line 104 including the first source electrode, the second and third source electrodes 138 (not shown), 168, first, A source / drain metal pattern including third to third drain electrodes 110, 140 (not shown) and 170 is formed.

  The source / drain metal pattern is formed by forming a source / drain metal layer on the interlayer insulating film 118 and then patterning the source / drain metal layer by a photolithography process and an etching process using a seventh mask. The data line 104 and the first drain electrode 110 are connected to the source region 114S and the drain region 114D of the first active layer 114 through the first source contact hole 124S and the first drain contact hole 124D, respectively. The first drain electrode 110 is connected to the pixel electrode 122 through the transmission hole 120 while overlapping with the storage line 152. The second source electrode 138 and the second drain electrode 140 are connected to each of the source region and the drain region of the second active layer 144 through the second source contact hole 154S and the second drain contact hole 154D. The third source electrode 168 and the third drain electrode 170 are connected to the source region 174S and the drain region 174D of the third active layer 174 through the third source contact hole 184S and the third drain contact hole 184D, respectively. .

  As described above, the method of manufacturing the polysilicon TFT substrate according to the embodiment of the present invention can be simplified by seven mask processes. As a result, the poly TFT substrate according to the embodiment of the present invention has a structure in which the source / drain metal pattern is exposed due to the absence of the protective film, but is located in the region sealed by the sealing material. It can be sufficiently protected not only by the alignment film applied to the substrate but also by the liquid crystal filled in the sealing region.

  As described above, the liquid crystal display device and the manufacturing method thereof according to the present invention can reduce the number of steps to seven mask steps while forming the drive circuit together with the image display region. Thereby, the cost of materials and capital investment can be reduced and the yield can be improved.

  From the above description, it will be understood by those skilled in the art that various changes and modifications can be made without departing from the technical idea of the present invention. Therefore, the technical scope of the present invention is not limited to the contents described in the detailed description of the specification, but must be defined by the claims.

FIG. 6 is a block diagram schematically showing a conventional polysilicon thin film transistor substrate. It is a top view which expands and shows the 1 pixel area | region shown in FIG. It is sectional drawing which follows the II 'line | wire of one pixel area | region shown in FIG. 1 is a plan view partially showing a polysilicon thin film transistor substrate according to an embodiment of the present invention. It is sectional drawing which follows the III-III 'and IV-IV' line of the polysilicon thin-film transistor substrate shown in FIG. It is sectional drawing explaining the manufacturing method of the polysilicon thin-film transistor substrate by embodiment of this invention. It is sectional drawing explaining the process of following FIG. 6A. FIG. 6B is a cross-sectional view illustrating a process following FIG. 6B. It is sectional drawing explaining the process of following FIG. 6C. It is sectional drawing explaining the process of following FIG. 6D. It is sectional drawing explaining the process of following FIG. 6E. It is sectional drawing explaining the process of following FIG. 6F.

Explanation of symbols

1, 100 Substrate 2, 102 Gate line 3, 194 Gate driver 4, 104 Data line 5, 192 Data driver 6, 106, 136, 166 Gate electrode 7, 196 Image display area 10, 110, 140, 170 Drain electrode 12, 112 Buffer film 14, 114, 144, 174 Active layer 14S, 114S, 174S Source region 14D, 114D, 174D Drain region 14C, 114C, 174C Channel region 16, 116 Gate insulating film 18 Protective film 20 Pixel contact hole 22, 122 Pixel Electrodes 24S, 124S, 154S, 184S Source contact holes 26, 118 Interlayer insulating films 30, 130, 180, 190 Thin film transistor 150 Storage lower electrode 160 Storage capacitor

Claims (24)

A substrate having an image display area and a driver area;
A first active layer formed in an image display region on the substrate, a second active layer and a third active layer formed in the driver region,
A first insulating film formed on the first to third active layers;
A first gate electrode, a second gate electrode and a third gate electrode which are formed on the first insulating layer corresponding to the first to third active layers, respectively, and a gate line connected to the first gate electrode; And a first conductive film including a pixel electrode;
A first hole is formed on the first insulating layer on which the first conductive layer is formed, and a contact hole exposing the source and drain regions of the first to third active layers and a transmission hole exposing the pixel electrode are formed. Two insulating films;
First to third source electrodes and first to third drain electrodes formed on the second insulating film and connected to source and drain regions of the first to third active layers, respectively, and the first source electrode A second conductive pattern including a data line connected to
Including
The first to third gate electrodes, the gate lines, and the pixel electrodes have a double layer structure in which a metal layer is formed on a transparent conductive layer.
The transparent conductive layer of the pixel electrodes, the display device characterized in that it is exposed through a transmission hole which penetrates the second insulating layer and the metal layer. A storage line having the double layer structure;
A storage lower electrode connected to the first active layer;
The display device according to claim 1, further comprising a first storage capacitor formed by overlapping the storage lower electrode with the storage line with the first insulating layer interposed therebetween. The display device according to claim 2 , wherein the storage line intersects the data line. It said first drain electrode, a display device according to claim 2, further comprising a second storage capacitor formed above is overlapped with the storage line across the second insulating layer. The display device according to claim 2 , wherein the storage lower electrode extends from the first active layer and includes an impurity. Before Symbol first drain electrode, a display device according to claim 1, characterized in that it is directly connected to the transparent conductive layer of the pixel electrode. The display device according to claim 6 , wherein the first drain electrode is in contact with a metal layer of the pixel electrode. The display device according to claim 1, wherein the metal layer of the pixel electrode surrounds the periphery of the transmission hole. The display device according to claim 1, wherein the first to second active regions include a channel region, a source region and a drain region, and an LDD (Lightly Doped Drain) region. The display device according to claim 9 , wherein the source and drain regions are doped with n + impurities. The display device according to claim 9 , wherein the LDD region is formed between the source region and the drain region and is doped with an n-impurity. The display device according to claim 1, wherein the display device is a liquid crystal display device, and further includes a liquid crystal layer on the substrate. Forming a first active layer to a third active layer on a substrate;
Forming a first insulating film on the active layer;
A first gate electrode; a second gate electrode; a third gate electrode; a gate line connected to the first gate electrode; and a pixel electrode on the first insulating film; and a metal layer on the transparent conductive layer. Forming a first conductive pattern having a double layer structure to be formed;
Forming source and drain regions doped with a first impurity on the first active layer and the second active layer;
Forming source and drain regions doped with a second impurity on the third active layer;
Forming a second insulating film on the first conductive pattern;
Forming source and drain contact holes exposing the source and drain regions of the first, second and third active layers, and forming transmission holes exposing the transparent conductive layer of the pixel electrode;
Forming first, second and third source and drain regions connected to the source and drain regions of the first, second and third active layers, and a second conductive pattern including a data line. ,
The method for manufacturing a display device, wherein the first drain electrode is connected to the transparent conductive layer of the pixel electrode. Forming a storage lower electrode extended from the first active layer;
Patterning the first conductive layer to form a storage line;
The method of manufacturing a display device according to claim 13 , further comprising: forming a storage capacitor by overlapping the storage lower electrode with the storage line. The display device manufacturing method according to claim 14 , wherein the storage line is juxtaposed with the data line. The method for manufacturing a display device according to claim 14 , further comprising forming a second storage capacitor by overlapping the storage line with the first drain electrode. The method for manufacturing a display device according to claim 14 , further comprising a step of implanting impurities into the storage lower electrode. The method further comprises forming an LDD region between a channel region overlapping with the first and second gate electrodes and the source and drain regions on the first and second active layers. 14. A method for manufacturing the display device according to 14 . The LDD region, according to claim 18, characterized in that as a mask the first and second gate electrodes are formed by doping n- impurity in each part of the first and second active layers Method of manufacturing the display device. The step of forming the transmission hole includes:
Patterning the first insulating film to form the transmission hole;
The method for manufacturing a display device according to claim 13 , further comprising: etching the metal layer of the pixel electrode through the transmission hole to expose the transparent conductive layer of the pixel electrode. 21. The method of manufacturing a display device according to claim 20 , wherein the transmission hole penetrates the first insulating film and the metal layer, and the metal layer surrounds the periphery of the transmission hole. The method of manufacturing a display device according to claim 13 , further comprising forming a buffer film between the substrate and the first, second, and third active layers. The method for manufacturing a display device according to claim 13 , wherein the display device is a liquid crystal display device and further includes a liquid crystal layer on the substrate. The method for manufacturing a display device according to claim 13 , wherein the first drain electrode is in contact with a metal layer of the pixel electrode.

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