KR0184509B1 - Thin film transistor and its fabrication method - Google Patents
Thin film transistor and its fabrication method Download PDFInfo
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- KR0184509B1 KR0184509B1 KR1019960017528A KR19960017528A KR0184509B1 KR 0184509 B1 KR0184509 B1 KR 0184509B1 KR 1019960017528 A KR1019960017528 A KR 1019960017528A KR 19960017528 A KR19960017528 A KR 19960017528A KR 0184509 B1 KR0184509 B1 KR 0184509B1
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- 239000010409 thin film Substances 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 238000000034 method Methods 0.000 title claims description 11
- 239000010408 film Substances 0.000 claims abstract description 39
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 238000005498 polishing Methods 0.000 claims description 6
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims 3
- 239000004020 conductor Substances 0.000 claims 2
- 239000000463 material Substances 0.000 claims 2
- 229910052581 Si3N4 Inorganic materials 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 1
- 150000002500 ions Chemical class 0.000 claims 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims 1
- 229910052814 silicon oxide Inorganic materials 0.000 claims 1
- 239000000126 substance Substances 0.000 claims 1
- 230000010354 integration Effects 0.000 abstract description 5
- 230000015654 memory Effects 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000007943 implant Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
- H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
- H10D30/6715—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
- H10B10/125—Static random access memory [SRAM] devices comprising a MOSFET load element the MOSFET being a thin film transistor [TFT]
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
- H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
- H10D30/0316—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral bottom-gate TFTs comprising only a single gate
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
- H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
- H10D30/6732—Bottom-gate only TFTs
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- Thin Film Transistor (AREA)
- Semiconductor Memories (AREA)
Abstract
[청구범위에 기재된 발명이 속한 기술분야][Technical field to which the invention described in the claims belong]
본 발명은 박막 트랜지스터에 관한 것이다.The present invention relates to a thin film transistor.
[발명이 해결하려고 하는 기술적 과제][Technical Challenges to Invent]
본 발명은 하부 게이트 TFT의 채널 도전층을 채널 영역과 소오스 및 드레인 영역을 분리 형성하여 부정합을 제거하여 안정된 특성을 가지며 또한 오프셋 영역을 게이트 도전층과 수직으로 형성하여 SRAM 쎌의 고집적화를 가질 수 있는 TFT 및 그 제조 방법을 제공한다.According to the present invention, the channel conduction layer of the lower gate TFT is formed by separating the channel region and the source and drain regions to remove mismatches, and the offset region is formed perpendicularly to the gate conduction layer to achieve high integration of the SRAM. Provided are a TFT and a method of manufacturing the same.
[발명의 해결방법의 요지][Summary of the solution of the invention]
본 발명은 게이트 도전층 상부에 채널을 가지는 박막 트랜지스터에 있어서, 상기 게이트 도전층 상부표면 양끝단의 소정거리의 안쪽부분과 상기 게이트 도전층을 제외한 기판 상부표면에, 상기 기판으로부터 상기 게이트 도전층 상부표면 높이에서 소정 높이까지 형성된 제1절연막과, 상기 게이트 도전층 상부표면과 상기 제1절연막 측벽을 따라 소정 두께를 가지며 오프셋 영역의 길이만큼 상기 제1절연막의 상부표면 높이와 동일한 높이로 형성된 제2절연막과, 상기 제2절연막의 상부표면 및 측벽을 따라 소정 두께로 형성된 제1도전층과, 상기 제1채널 도전층의 상부표면 및 측벽을 따라 상기 제1절연막의 상부표면 높이와 동일한 높이까지 채워져 형성된 제3절연막과, 상기 제3절연막을 사이에 두고 상기 제1절연막 양쪽 상부표면에서 상기 제3절연막 상부표면의 소정 부분까지 소정 두께로 각각 분리 형성된 제2도전층을 가짐을 특징으로 한다.According to an aspect of the present invention, there is provided a thin film transistor having a channel on an upper portion of a gate conductive layer, wherein the gate conductive layer is disposed on the upper surface of the substrate except for the gate conductive layer and the inner portion of a predetermined distance at both ends of the upper surface of the gate conductive layer. A first insulating film formed from a surface height to a predetermined height, a second thickness formed along a top surface of the gate conductive layer and sidewalls of the first insulating film, and a second thickness formed at the same height as the upper surface height of the first insulating film by a length of an offset region; An insulating film, a first conductive layer formed to a predetermined thickness along the upper surface and sidewalls of the second insulating film, and filled to the same height as the upper surface height of the first insulating film along the upper surface and sidewalls of the first channel conductive layer; The third insulating film formed on both upper surfaces of the first insulating film and the third insulating film formed therebetween; It characterized by up to a predetermined portion of the surface portion having a second conductive layer formed separately from each other to a desired thickness.
[발명의 중요한 용도][Important Uses of the Invention]
본 발명은 박막 트랜지스터에 적합하게 사용된다.The present invention is suitably used for thin film transistors.
Description
제1도는 종래 기술의 일실시예에 따른 하부 게이트 TFT를 보여주는 단면도.1 is a cross-sectional view showing a lower gate TFT according to an embodiment of the prior art.
제2a∼f도는 본 발명의 일실시예에 따른 TFT 제조 공정 순서를 보여주는 공정 단면도.2A to 2F are cross-sectional views showing a TFT manufacturing process sequence according to an embodiment of the present invention.
본 발명은 박막 트랜지스터에 관한 것으로, 특히 스태틱 램(Static Random Access Memory: 이하 SRAM이라 칭함)의 부하소자로 사용되는 박막 트랜지스터(Thin Film Transistor: 이하 TFT라 칭함) 및 그 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to thin film transistors, and more particularly, to thin film transistors (hereinafter referred to as TFTs) used as load elements of static random access memories (hereinafter referred to as SRAMs) and methods of manufacturing the same.
일반적으로, SRAM은 다이나믹 램(Dynamic Random Access Memory: 이하 DRAM이라 칭함)에 비하여 집적도가 떨어지는 반면, 리프레쉬(Refresh) 과정이 필요없어 동작 속도가 빠를 뿐만 아니라 소비 전력이 작다는 잇점이 있다. 따라서 반도체 메모리 분야에서 널리 이용되고 있다. 반도체 메모리 장치에서 SRAM의 부하 소자로써 사용되는 TFT의 제조는 4메가(Mega)급 이상의 저전력 소비 및 고집적 제품군에서는 필수적인 요소 기술이다. TFT는 그 구조에 따라 실리콘 게이트(Silicon Gate) 도전층이 채널 도전층 예를들면 제1 및 제2도전층 상부에 위치하게 되면 상부 게이트(Top Gate) TFT라 하며, 실리콘 게이트 도전층이 채널 도전층 하부에 위치하게 되면 하부 게이트(Bottom Gate) TFT라 한다. 일반적으로 공정 아키텍쳐 구현이 용이한 하부 게이트 TFT가 널리 실용화되고 있다. 그러나 TFT는 채널 도전층이 일반적인 실리콘 단결정(Single Crystal)으로 사용되는 벌크(Bulk) 트랜지스터와는 달리, 비정질(Amorphous) 실리콘으로 구성되어 있어 적절한 공정 조건에서만 최적의 트랜지스터 특성을 구현할 수 있다. 이와 같은 특성 최적화는 대기시 낮은 소비전력을 얻기 위해 낮은 오프(Off) 전류와 메모리 쎌(Memory Cell)의 데이터를 안정되게 유지하기 위해 높은 온(On) 전류특성을 동시에 만족시켜야 한다. 특성 최적화를 위해 즉, 낮은 오프전류를 얻기 위해 박막 트랜지스터에 오프셋(Offset) 영역을 형성시키는 방법과 채널 두께를 줄이는 방법등이 이용되고 있으며, 높은 온(On) 전류를 얻기 위해서 오프셋 영역을 도핑(Doping)시키는 방법과 박막 트랜지스터의 게이트 절연막 두께를 줄이는 방법등이 시도되고 있다.In general, while SRAM has a lower density than Dynamic Random Access Memory (DRAM), it does not require a refresh process, and thus, the operation speed is fast and power consumption is low. Therefore, it is widely used in the field of semiconductor memory. The manufacture of TFTs used as load elements of SRAMs in semiconductor memory devices is an essential element technology for low power consumption and high integration products of more than 4 Mega class. The TFT is called a top gate TFT when the silicon gate conductive layer is positioned above the channel conductive layer, for example, the first and second conductive layers, according to the structure thereof. The silicon gate conductive layer is a channel conductive layer. When positioned below the layer, it is called a bottom gate TFT. In general, a lower gate TFT having an easy process architecture implementation has been widely used. However, unlike bulk transistors in which the channel conductive layer is used as a single silicon, the TFT is composed of amorphous silicon, so that the optimal transistor characteristics can be realized only under appropriate process conditions. This characteristic optimization must satisfy both the low off current and the high on current characteristics in order to keep the data of the memory cell stable in order to obtain low power consumption during standby. In order to optimize the characteristics, that is, a method of forming an offset region in a thin film transistor to obtain a low off current and a method of reducing a channel thickness, etc., doping an offset region to obtain a high on current Doping) and a method of reducing the thickness of the gate insulating film of the thin film transistor have been attempted.
제1도는 종래 기술의 일실시예에 따른 하부 게이트 TFT를 보여주는 단면도이다. 제1도를 참조하면, 채널 도전층 3의 형성 후 TFT의 소오스(Source) 영역 9-1 및 드레인(Drain) 영역 9-2를 주입 마스크(Implant Mask)를 사용하여 형성시키므로, 소오스 9-1 및 드레인 9-1 영역과 하부 채널 도전층간에 부정합(Misalign)이 발생하기 쉬운 문제점이 있다. 이로 인하여 오프셋 길이도 일정하게 유지하기 힘들게 되어, TFT의 문턱전압(Vt) 변화 및 쎌 내의 TFT 특성의 비조화(Mismatch)와 같은 SRAM 쎌의 특성 저하가 발생하는 문제점이 있다. 또한 종래의 하부 게이트 TFT에서는 오프셋 영역이 게이트 도전층 영역 3과 나란히 형성되어 반도체 메모리 장치를 고집적화 하는데 불리한 문제점이 있다.1 is a cross-sectional view showing a lower gate TFT according to an embodiment of the prior art. Referring to FIG. 1, since the source region 9-1 and the drain region 9-2 of the TFT are formed using the implant mask after the formation of the channel conductive layer 3, the source 9-1 is formed. And misalignment between the drain 9-1 region and the lower channel conductive layer. This makes it difficult to keep the offset length constant, resulting in a problem of deterioration of the characteristics of the SRAM fin such as a change in the threshold voltage Vt of the TFT and mismatch of TFT characteristics in the fin. In addition, in the conventional lower gate TFT, an offset region is formed in parallel with the gate conductive layer region 3, which is disadvantageous in high integration of the semiconductor memory device.
따라서, 본 발명의 목적은 하부 게이트 TFT의 채널 도전층을 채널 영역과 소오스 및 드레인 영역을 분리 형성하여 부정합을 제거하여 안정된 특성을 가지는 TFT 및 그 제조 방법을 제공함에 있다.Accordingly, an object of the present invention is to provide a TFT having a stable characteristic by forming a channel conductive layer of a lower gate TFT separately from a channel region and a source and drain region to remove mismatches, and a method of manufacturing the same.
본 발명의 다른 목적은 주입 마스크를 사용하여 소오스 및 드레인 영역을 형성시키지 않음으로써 소오스 및 드레인 영역 형성시 발생하는 부정합을 제거하여 안정된 특성을 가지는 TFT 및 그 제조 방법을 제공함에 있다.Another object of the present invention is to provide a TFT and a method of manufacturing the same, which do not form a source and a drain region by using an injection mask, thereby eliminating mismatches generated when the source and drain regions are formed.
본 발명의 또다른 목적은 오프셋 영역이 게이트 도전층과 수직으로 형성되게 하여 SRAM 쎌의 고집적화를 유리하게 하는 TFT 및 그 제조 방법을 제공함에 있다.It is still another object of the present invention to provide a TFT and a method for manufacturing the same, in which an offset region is formed perpendicular to the gate conductive layer, which favors high integration of the SRAM fin.
상기한 목적들을 달성하기 위한 본 발명의 기술적 사상에 따르면, 게이트 도전층 상부에 채널을 가지는 박막 트랜지스터에 있어서, 상기 게이트 도전층 상부표면 양끝단의 소정거리의 안쪽부분과 상기 게이트 도전층을 제외한 기판 상부표면에, 상기 기판으로부터 상기 게이트 도전층 상부표면 높이에서 소정 높이까지 형성된 제1절연막과, 상기 게이트 도전층 상부표면과 상기 제1절연막 측벽을 따라 소정 두께를 가지며 오프셋 영역의 길이만큼 상기 제1 절연막의 상부표면 높이와 동일한 높이로 형성된 제2절연막과, 상기 제2절연막의 상부표면 및 측벽을 따라 소정 두께로 형성된 제1도전층과, 상기 제1채널 도전층의 상부표면 및 측벽을 따라 상기 제1절연막의 상부표면 높이와 동일한 높이까지 채워져 형성된 제3절연막과, 상기 제3절연막을 사이에 두고 상기 제1절연막 양쪽 상부표면에서 상기 제3절연막 상부표면의 소정 부분까지 소정 두께로 각각 분리 형성된 제2도전층을 가지는 것을 특징으로 한다.According to the technical idea of the present invention for achieving the above objects, in the thin film transistor having a channel on the gate conductive layer, the substrate excluding the inner portion of the predetermined distance of both ends of the upper surface of the gate conductive layer and the gate conductive layer A first insulating film formed on an upper surface of the gate conductive layer from an upper surface of the gate conductive layer to a predetermined height from the substrate, and having a predetermined thickness along the upper surface of the gate conductive layer and the sidewall of the first insulating film and having a predetermined thickness along the length of the offset region; A second insulating film formed at the same height as an upper surface of the insulating film, a first conductive layer formed to a predetermined thickness along the upper surface and sidewalls of the second insulating film, and along the upper surface and sidewalls of the first channel conductive layer; A third insulating film filled with the same height as the upper surface of the first insulating film, and the third insulating film And to the first side of the top surface in the first insulating film characterized by having a second conductive layer formed, each separated by a predetermined thickness to the predetermined portion of the top surface of the third insulating film.
이하 본 발명의 바람직한 실시예들의 상세한 설명이 첨부된 도면들을 참조하여 설명된다.DETAILED DESCRIPTION A detailed description of preferred embodiments of the present invention will now be described with reference to the accompanying drawings.
도면들중 동일한 구성요소 및 부분들은 가능한한 어느곳에서든지 동일한 부호들을 나타내고 있음을 유의하여야 한다.It should be noted that like elements and parts in the figures represent the same numerals wherever possible.
제2a∼f도는 본 발명의 일실시예에 따른 TFT 제조 공정 순서를 보여주는 공정 단면도이다. 제 2a∼f도를 참조하면, 폴리 실리콘(Poly Silicon) 또는 비정질 실리콘으로 게이트 도전층 3을 형성한 후 제1절연막 5를 상기 게이트 도전층 3 및 기판 상부에 침적(Deposition)하고 게이트 형성할 부분을 소정 부분 식각하여 접촉구(Contact)를 형성한다(a). 여기서 침적한 절연막의 두께로 오프셋 길이가 결정된다. 상기 형성된 접촉구에 제2절연막 예를들면 게이트 절연막 7을 침적한 후 폴리 실리콘이나 비정질 실리콘으로 제1도전층 9를 상기 게이트 절연막 7의 상부에 침적하고, TFT의 특성 최적화를 위해 채널 이온 주입을 위하여 채널을 형성한다(b). 상기 형성된 제1도전층 9의 상부에 제3절연막 11을 두껍게 침적한다(c). 이후 기계 및 화학적 폴리싱(Chemical Mechanical Polishing: 이하 CMP이라 칭함) 공정으로 게이트 절연막 7 하부에 위치하는 제1절연막 5의 상부표면이 노출될때 까지 폴리싱한다(d). 또한 상기 CMP의 양으로 오프셋 길이를 조절할 수 있다. 이후 전술한 바와 같이 형성한 패턴(Pattern) 위에 폴리 실리콘이나 비정질 실리콘으로 제2도전층 13을 전체 상부 표면에 침적시키고 그 위에서 소오스 13-1 및 드레인 13-2를 형성하기 위한 이온 주입을 한다(e). 그리고 나서 채널의 패턴을 상기 제3절연막 11이 노출되도록 사진 식각을 통하여 형성한다(f).2A to 2F are cross-sectional views illustrating a TFT manufacturing process sequence according to an embodiment of the present invention. Referring to FIGS. 2A through F, a portion in which a gate conductive layer 3 is formed of polysilicon or amorphous silicon, and a first insulating layer 5 is deposited on the gate conductive layer 3 and the substrate, and the gate is formed. Etching a predetermined portion to form a contact (At contact) (a). Here, the offset length is determined by the thickness of the deposited insulating film. A second insulating layer, for example, a gate insulating layer 7 is deposited on the formed contact hole, and then a first conductive layer 9 is deposited on the upper portion of the gate insulating layer 7 with polysilicon or amorphous silicon, and channel ion implantation is performed to optimize the characteristics of the TFT. To form a channel (b). The third insulating layer 11 is thickly deposited on the formed first conductive layer 9 (c). Subsequently, by performing a mechanical mechanical polishing (CMP) process, polishing is performed until the upper surface of the first insulating film 5 positioned below the gate insulating film 7 is exposed (d). It is also possible to adjust the offset length by the amount of CMP. Subsequently, the second conductive layer 13 is deposited on the entire upper surface of the pattern formed as described above with polysilicon or amorphous silicon and ion implanted to form the source 13-1 and the drain 13-2 thereon ( e). Then, the channel pattern is formed by photolithography to expose the third insulating layer 11 (f).
결과적으로, SRAM에 있어서 메모리 쎌의 데이터를 안정되게 유지하고, 대기시 소비전류를 낮게 억제하기 위해서 메모리 쎌의 로드(Load) 소자로 TFT 소자를 사용하게 된다.As a result, the TFT element is used as the load element of the memory V to keep the data of the memory V stable in the SRAM and to suppress the standby current consumption.
따라서 상기한 본 발명에 따르면, 주입 마스크를 사용하여 소오스 및 드레인 영역을 형성하지 않음으로써 소오스 및 드레인 영역 형성시 발생하는 미스얼라인 문제를 근본적으로 해결하고, 또한 오프셋 영역을 게이트 도전층과 수직으로 형성하여 SRAM 쎌의 고집적화에도 유리한 효과가 있다.Therefore, according to the present invention described above, the source and drain regions are not formed using the implant mask, thereby fundamentally solving the misalignment problem generated when the source and drain regions are formed, and the offset region is perpendicular to the gate conductive layer. It also has a beneficial effect on high integration of SRAM fins.
상기한 본 발명은 도면을 중심으로 예를들어 한정되었지만, 그 동일한 것은 본 발명의 기술적 사상을 벗어나지 않는 범위내에서 여러가지 변화와 변형이 가능함이 본 분야의 숙련된 자에게 있어 명백할 것이다.Although the present invention described above has been limited to, for example, the drawings, the same will be apparent to those skilled in the art that various changes and modifications can be made without departing from the technical spirit of the present invention.
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| KR1019960017528A KR0184509B1 (en) | 1996-05-22 | 1996-05-22 | Thin film transistor and its fabrication method |
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| US7256060B2 (en) | 2004-11-12 | 2007-08-14 | Lg.Philips Lcd Co., Ltd. | Liquid crystal display device and method of fabricating the same |
| US7396765B2 (en) | 2004-11-12 | 2008-07-08 | Lg Display Co., Ltd. | Method of fabricating a liquid crystal display device |
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| US7414691B2 (en) | 2004-08-12 | 2008-08-19 | Lg Display Co., Ltd. | Liquid crystal display device with prevention of defective disconnection of drain/pixel electrodes by forming two conductive layers on top of entire pixel electrode and then removing a portion of both therefrom |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR101048998B1 (en) | 2004-08-26 | 2011-07-12 | 엘지디스플레이 주식회사 | LCD and its manufacturing method |
| KR101048903B1 (en) | 2004-08-26 | 2011-07-12 | 엘지디스플레이 주식회사 | LCD and its manufacturing method |
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1996
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|---|---|---|---|---|
| US7414691B2 (en) | 2004-08-12 | 2008-08-19 | Lg Display Co., Ltd. | Liquid crystal display device with prevention of defective disconnection of drain/pixel electrodes by forming two conductive layers on top of entire pixel electrode and then removing a portion of both therefrom |
| US7638801B2 (en) | 2004-08-13 | 2009-12-29 | Lg Display Co., Ltd. | Liquid crystal display device and fabrication method thereof |
| US7927930B2 (en) | 2004-08-13 | 2011-04-19 | Lg Display Co., Ltd. | Method for fabricating a liquid crystal display device |
| US7407842B2 (en) | 2004-11-12 | 2008-08-05 | Lg Display Co., Ltd. | Liquid crystal display device and method of fabricating the same |
| US7396765B2 (en) | 2004-11-12 | 2008-07-08 | Lg Display Co., Ltd. | Method of fabricating a liquid crystal display device |
| US7619286B2 (en) | 2004-11-12 | 2009-11-17 | Lg Display Co., Ltd. | Liquid crystal display device and method of fabricating the same |
| US7256060B2 (en) | 2004-11-12 | 2007-08-14 | Lg.Philips Lcd Co., Ltd. | Liquid crystal display device and method of fabricating the same |
| US7474362B2 (en) | 2004-12-22 | 2009-01-06 | Lg Display Co., Ltd. | Liquid crystal display device and method of fabricating the same |
| US7632722B2 (en) | 2004-12-24 | 2009-12-15 | Lg Display Co., Ltd. | Liquid crystal display device and method of fabricating the same |
| US7999267B2 (en) | 2004-12-24 | 2011-08-16 | Lg Display Co., Ltd. | Liquid crystal display device |
| US7492432B2 (en) | 2004-12-31 | 2009-02-17 | Lg Display Co., Ltd. | Liquid crystal display device and method of fabricating the same |
| US7595859B2 (en) | 2004-12-31 | 2009-09-29 | Lg Display Co., Ltd. | Liquid crystal display device and method of fabricating the same |
| US7830476B2 (en) | 2004-12-31 | 2010-11-09 | Lg Display Co., Ltd. | Electroluminescence display device comprising a drain electrode being directly contacted with the upper surface of the first transparent conductive layer and the side surface of the second conductive layer and fabricating methods thereof |
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| KR970077363A (en) | 1997-12-12 |
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