KR100557927B1 - Contact formation method of SRAM device - Google Patents

Abstract

The present invention discloses a method for forming a contact of an SRAM device capable of preventing the occurrence of a natural oxide film. The disclosed invention provides a semiconductor substrate having a drive transistor, a junction region for an access transistor and a common node, forming an interlayer insulating film on the semiconductor substrate, and forming a TFT gate on a predetermined portion on the interlayer insulating film. Forming a buffer contact portion on the interlayer insulating film corresponding to the junction region for the electrode and the common node, forming a gate insulating film on the surface of the TFT gate electrode and the buffer contact portion, and forming a poly for channel on the substrate Forming a silicon film, ion implanting impurities into a predetermined portion of the polysilicon film for the channel, forming a source and a drain region of the TFT, forming a passivation film on the polysilicon film for the channel, and A protective film to expose a predetermined portion of the gate electrode of the common node and the drive transistor, Forming a node contact hole by etching the channel polysilicon film, the gate insulating film, the buffer contact portion, and the interlayer insulating film, and forming a contact line to contact the buffer contact portion and the channel polysilicon film in the node contact hole. Characterized in that it comprises a step.

Description

Method for forming contact in SRAM device

1 is a cross-sectional view of a conventional SRAM device.

2A to 2C are cross-sectional views of respective processes for explaining a method for manufacturing a TFT according to the present invention.

3 is a cross-sectional view for explaining another embodiment of the present invention.

(Explanation of symbols for the main parts of the drawing)

20-semiconductor substrate 21-field oxide film

22-gate insulating film 23A, 23B-gate electrode

24-sidewall spacers 25A, 25B-source, drain region

26-First Oxide 27-Bit Line

28-second oxide film 29-planarization film

30-third oxide film 31- TFT gate electrode

31a-buffer contact portion 32-gate insulating film of TFT

33-fourth polysilicon film for channel 34-protective film

37-Contact Line

The present invention relates to a method for forming a contact of an SRAM (hereinafter referred to as SRAM) device, and more particularly, to a method for forming a contact of an SRAM device capable of preventing the occurrence of a natural oxide film in a contact portion.

Semiconductor memory devices are classified into DRAMs (DRAMs) and SRAMs (SRAMs). SRAM is a very popular memory device driven by high speed, low power consumption and simple operation. In addition, unlike DRAM, it is not necessary to refresh periodically stored information and has an advantage of easy design.

The SRAM cell is composed of two pull-down devices, two access devices and two pull-up devices, depending on the configuration of the pull-up device. It is classified into three types: high load resistor (HLR) type and thin film transistor (TFT) type. P-channel bulk MOSFET is used as a pull-up device for the full CMOS type, and a polysilicon layer having a high resistance value is used as the pull-up device for the HLR type, and a P-channel polysilicon TFT is used for the TFT type. Used as

Here, the TFT type SRAM element can be significantly reduced in cell size, and thus it is easy to apply to a semiconductor memory device used exclusively for the storage element. That is, since the TFT is formed on the substrate on which the drive transistor and the access transistor are formed, it is easy for high integration.

1 is a cross-sectional view of a conventional TFT type SRAM device, and schematically illustrates a manufacturing method of a conventional TFT type SRAM device through the drawings.

A gate insulating film is formed on the semiconductor substrate 1 provided with the field oxide film 2 separating the device from the device, and the first polysilicon film is deposited by a known deposition method. Subsequently, the first polysilicon film is partially patterned to form the gate electrode 3A of the access transistor and the gate electrode 3B of the drive transistor. Impurities are injected into the semiconductor substrate 1 on both sides of the gate electrodes 3A and 3B to form source and drain regions S and D regions of the transistor, respectively. At this time, in the drawing, the source region S is a portion to be contacted with the bit line later, and the drain region D is a common connection node between the access transistor and the drive transistor and the TFT to be formed later.

Thereafter, after depositing the first oxide film 4 over the entire structure, the first oxide film 4 is etched to expose the source region S of the access transistor. Thereafter, a second polysilicon film is deposited to contact the exposed source region S, and then a predetermined partial etching is performed to form the bit line 5.

Thereafter, the second oxide film 6, the planarization insulating film 7, and the third oxide film 8 are sequentially formed on the bit line 5 and the first oxide film 4, and then the common connection serving as the drain region of the drive transistor is formed. The third oxide film 8, the planarization insulating film 7, the second oxide film 6, and the first oxide film 4 are partially etched so that the node D and the gate electrode 3B of the drive transistor are simultaneously exposed. The contact hole h is formed.

Subsequently, a third polysilicon film is deposited on the inner wall of the node contact hole h and the third oxide film 8. Thereafter, the third polysilicon film is patterned so as to exist in the gate electrode predetermined region of the TFT and inside the node contact hole h and adjacent to the contact hole h, thereby forming the gate electrode 9A of the TFT and the first node contact line ( 9B). Then, impurities are implanted into the gate electrode 9A and the first node contact line 9B. Thereafter, the gate insulating film 10 of the TFT is formed on the resultant, the gate insulating film 10 is patterned to exist only in the TFT predetermined region, and then the fourth polysilicon to act as the second node contact line, the channel of the TFT and the Vcc line. A film is formed on top of the entire structure. Thereafter, impurities are implanted into only the portion of the fourth polysilicon film except for the channel forming portion of the TFT, and then patterned to a predetermined size to form the Vcc line 11A, the channel region 11B of the TFT, and the second node contact line 11C. ).

However, in the above-described conventional SRAM device, after forming the first node contact line 9B, before forming the second node contact line 11c, a process of forming a gate insulating film, a process of ion implanting impurities, etc. By proceeding, the time for exposing the first node contact line 9B to air is generated.

Accordingly, a natural oxide film is generated on the surface of the first node contact line 9B, and conventionally, a cleaning process for removing the natural oxide film is performed before forming the fourth polysilicon film.

However, the gate insulating film may be partially lost in the cleaning process for removing the natural oxide film. In particular, when the gate insulating film on the sidewall of the TFT gate electrode is removed, the source or drain region and the gate electrode are shorted.

Accordingly, an object of the present invention is to provide a method for forming a contact of an SRAM device capable of preventing the occurrence of a natural oxide film in a contact portion in a node contact hole.

In order to achieve the above object of the present invention, a contact forming method of an SRAM device according to an embodiment of the present invention comprises the steps of providing a semiconductor substrate having a drive transistor, an access transistor and a junction region for a common node; Forming an interlayer insulating film on the semiconductor substrate; Forming a buffer contact portion at a portion corresponding to the junction region for the common node while forming a TFT gate electrode on a predetermined portion on the interlayer insulating film; Forming a gate insulating film on surfaces of the TFT gate electrode and the buffer contact portion; Forming a polysilicon film for the channel on the substrate resultant; Implanting impurities into a predetermined portion of the channel polysilicon film to form source and drain regions of the TFT; Forming a protective film on the polysilicon film for the channel; Forming a node contact hole by etching the passivation layer, the polysilicon layer for the channel, the gate insulating layer, the buffer contact portion, and the interlayer insulating layer so that a predetermined portion of the gate electrode of the common node and the drive transistor is exposed; And forming a contact line in the node contact hole, the contact line being in contact with an exposed portion of the gate electrode of the common node and the drive transistor, the contact line being in contact with the etched side surface of the buffer contact portion and the polysilicon layer for the channel. do.

The contact line is formed by sequentially stacking a polysilicon film doped in the node contact hole and a transition metal silicide film, or by filling a doped polysilicon film in the node contact hole, or in the node contact hole. A metal film is embedded. In this case, when the contact film is formed by embedding the metal film, a tungsten film is used as the metal film.

In addition, the protective film is an oxide film is used, and after the step of forming the contact line, patterning the polysilicon film for the channel, characterized in that it further comprises the step of forming a channel layer.

The buffer contact portion and the TFT gate electrode are formed of a doped polysilicon film.

According to the present invention, when forming a node contact hole in a TFT type SRAM element, a polysilicon film for channel layers of a TFT is formed, and then a node contact hole is formed after covering a protective film on the surface thereof. Thereafter, a contact line is formed in the node contact hole.

Accordingly, it is not necessary to form a double contact line as in the prior art, and the process of forming the contact line proceeds without interruption, so that a natural oxide film is not formed. Therefore, the cleaning process for removing the native oxide film is excluded, so that the gate insulating film loss due to the cleaning is prevented.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A to 2C are cross-sectional views of respective processes for explaining a method of manufacturing a TFT according to the present invention. 3 is a cross-sectional view for explaining another embodiment of the present invention.

Referring to FIG. 2A, the field oxide film 21 is formed in a known manner so that the active region in which the respective drive transistor and access transistor regions are to be formed is defined on the semiconductor substrate 20. Then, the gate insulating film 22 is formed on the semiconductor substrate 20 resultant, and the first polysilicon film is deposited by a known deposition method. Subsequently, the first polysilicon film is partially patterned to form the gate electrode 23A of the access transistor and the gate electrode 23B of the drive transistor. The spacers 24 are formed on both sidewalls of the gate electrodes 23A and 23B in a known manner, and then impurities are injected into the semiconductor substrate 20 on both sides of the spacers 24 so that the source and drain regions 25A and 25B are formed. As a result, the access transistor and the drive transistor are completed.

Thereafter, the first oxide layer 26 is deposited over the entire structure, and then a predetermined portion of the first oxide layer 26 is etched to expose the source region 25A of the access transistor. Thereafter, a second polysilicon film is deposited to contact the exposed source region 25A, and then a predetermined portion is etched to form a bit line 27. Thereafter, the second oxide film 28, the planarization film 29, and the third oxide film 30 are sequentially formed on the bit line 27 and the first oxide film 26.

Then, a third polysilicon film for TFT is deposited on the third oxide film 30, and then the third polysilicon film is partially patterned to exist in a portion corresponding to the TFT predetermined region and the drain region 25B as a common node. The TFT gate electrode 31 and the buffer contact portion 31a are formed. Subsequently, the TFT gate insulating film 32 is formed on the resultant, and then patterned to cover the surfaces of the TFT gate electrode 31 and the buffer contact portion 31a.

Next, as shown in FIG. 2B, a fourth polysilicon film 33 for a channel is deposited on the third oxide film 30 on which the TFT gate electrode 31 and the gate insulating film 32 are formed. Subsequently, a predetermined impurity is ion-implanted into the fourth polysilicon film 33 on both sides of the TFT gate electrode 31 to form a source and a drain region (not shown). Prior to ion implantation, an impurity may be further formed to form an offset region. Thereafter, in order to prevent a natural oxide film from occurring on the surface of the fourth polysilicon film 33, a protective film 34 of a thin film is formed on the fourth polysilicon film 33. At this time, a silicon oxide film is used as the protective film 34.

Thereafter, the protective film 34, the fourth polysilicon film 33, the TFT gate insulating film 32 of the TFT, and the buffer contact portion so that the common drain region 25B and the gate electrode 23B of the drive transistor can be simultaneously exposed. 31a), the third oxide film 30, the planarization film 29, the second oxide film 28, and the first oxide film 26 are sequentially patterned to form the node contact hole H. The fifth polysilicon in the node contact hole H is then contacted with the exposed drain region 25B and in contact with the buffer contact portion 31a of the sidewall of the node contact hole H and the fourth polysilicon film for the channel. The film 35 and the transition metal silicide film 36 are sequentially formed. At this time, after the fifth polysilicon film 35 is deposited, the transition metal silicide film 36 is formed without delay, so that a natural oxide film is not formed on the surface of the fifth polysilicon film 35. Thereafter, the fifth polysilicon film 35 and the transition metal silicide film 36 are partially patterned to form the contact line 37.

In addition, the polysilicon film may be deposited as a thick film, and then etched back to be embedded in the node contact hole, thereby forming a contact line. In addition, in order to further improve conductivity, a tungsten metal film 38 may be embedded in the node contact hole to form a contact line, as shown in FIG. 3.

Thereafter, the fourth polysilicon film 33 and the protective film 34 are partially patterned to form a channel layer.

As described in detail above, according to the present invention, when forming a node contact hole in a TFT-type SRAM element, a polysilicon film for channel layers of a TFT is formed, and then a node contact hole is formed after covering a protective film on the surface thereof. do. Thereafter, a contact line is formed in the node contact hole.

Accordingly, it is not necessary to form a double contact line as in the prior art, and the process of forming the contact line proceeds without interruption, so that a natural oxide film is not formed. Therefore, the cleaning process for removing the native oxide film is excluded, so that the gate insulating film loss due to the cleaning is prevented.

Claims (8)

Providing a semiconductor substrate having a drive transistor, and a junction region for an access transistor and a common node; Forming an interlayer insulating film on the semiconductor substrate; Forming a buffer contact portion at a portion corresponding to the junction region for the common node while forming a TFT gate electrode on a predetermined portion on the interlayer insulating film; Forming a gate insulating film on surfaces of the TFT gate electrode and the buffer contact portion; Forming a polysilicon film for the channel on the substrate resultant; Implanting impurities into a predetermined portion of the channel polysilicon film to form source and drain regions of the TFT; Forming a protective film on the polysilicon film for the channel; Forming a node contact hole by etching the passivation layer, the polysilicon layer for the channel, the gate insulating layer, the buffer contact portion, and the interlayer insulating layer so that a predetermined portion of the gate electrode of the common node and the drive transistor is exposed; And Forming a contact line in the node contact hole, the contact line being in contact with an exposed portion of the gate electrode of the common node and the drive transistor, the contact line being in contact with the etched side surface of the buffer contact portion and the polysilicon layer for the channel. Method for forming a contact of an SRAM device. The method of claim 1, wherein the contact line is formed by sequentially stacking a polysilicon layer doped in the node contact hole and a transition metal silicide layer. The method of claim 1, wherein the contact line is formed by embedding a doped polysilicon layer in the node contact hole. The method of claim 1, wherein the contact line is formed by embedding a metal film in the node contact hole. The method of claim 4, wherein the metal film is a tungsten film. The method of claim 1, wherein the protective film is an oxide film. The method of claim 1, further comprising, after forming the contact line, patterning a polysilicon film for a channel to form a channel layer. The method of claim 1, wherein the buffer contact portion and the TFT gate electrode are formed of a doped polysilicon film.

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