CN106876412A - A kind of array base palte and preparation method - Google Patents

Abstract

The embodiment of the present invention discloses an array substrate and a manufacturing method thereof. The array substrate includes: a plurality of first thin film transistors and a plurality of second thin film transistors; the first thin film transistors and the second thin film transistors are formed on the substrate above the substrate; the active layer of the first thin film transistor is low-temperature polysilicon, and the active layer of the second thin film transistor is an oxide semiconductor; the first thin film transistor is located in the peripheral circuit area of the array substrate, and the second thin film transistor is located in the In the display area of the array substrate: the gate of the first thin film transistor and the gate of the second thin film transistor are located in different layers, and the source and drain electrodes of the first thin film transistor and the source and drain electrodes of the second thin film transistor are located in the same layer. The invention solves the problem of incompatibility of film layers of the two types of thin film transistors when the metal oxide thin film transistor and the low temperature polysilicon thin film transistor are simultaneously formed in the display panel, and improves the electrical performance and stability of the display panel.

Description

A kind of array substrate and manufacturing method

technical field

Embodiments of the present invention relate to the field of display technology, and in particular to an array substrate and a manufacturing method.

Background technique

The metal oxide thin film transistor uses a metal oxide semiconductor layer as the active layer material of the thin film transistor. Due to its high carrier mobility, low deposition temperature and high transparency, it has become the mainstream display panel driving technology. Low-temperature polysilicon thin-film transistors have high switching speeds, and thin-film circuits can be made thinner and smaller, with lower power consumption and so on.

In the prior art, low-temperature polysilicon thin film transistors are used in the peripheral circuit area, and metal oxide thin film transistors are used in the pixel drive circuit in the display area, which improves the problems of poor device uniformity and leakage current.

However, due to the current manufacturing process, low-temperature polysilicon thin film transistors are manufactured at the same time as metal oxide thin film transistors, resulting in the incompatibility of the optimal film thicknesses of the two thin film transistors, so it is impossible to simultaneously ensure the metal oxide thin film transistor Each film layer of the low-temperature polysilicon thin film transistor and the low-temperature polysilicon thin film transistor is in the optimum thickness, and it is difficult to exert the optimum performance.

Contents of the invention

In view of this, an embodiment of the present invention provides an array substrate and a manufacturing method, which solve the problem of incompatibility of the layers of the two types of thin film transistors when the metal oxide thin film transistor and the low-temperature polysilicon thin film transistor are simultaneously formed in the display panel, and improve the performance of the array substrate. The electrical performance and stability of the display panel.

In a first aspect, an embodiment of the present invention provides an array substrate, including: a plurality of first thin film transistors and a plurality of second thin film transistors; the first thin film transistors and the second thin film transistors are formed on the base substrate Above; the active layer of the first thin film transistor is low temperature polysilicon, the active layer of the second thin film transistor is an oxide semiconductor; the first thin film transistor is located in the peripheral circuit area of the array substrate, and the second thin film transistor is located in the peripheral circuit area of the array substrate. Two thin film transistors are located in the display area of the array substrate;

The gate of the first thin film transistor and the gate of the second thin film transistor are located in different layers, and the source and drain electrodes of the first thin film transistor and the source and drain electrodes of the second thin film transistor are located in the same layer.

In a second aspect, an embodiment of the present invention further provides a display panel, including the array substrate described in the first aspect.

In a third aspect, an embodiment of the present invention further provides a method for manufacturing an array substrate, including: forming a plurality of first thin film transistors and a plurality of second thin film transistors above the base substrate;

Wherein, the active layer of the first thin film transistor is low temperature polysilicon, the active layer of the second thin film transistor is an oxide semiconductor; the first thin film transistor is located in the peripheral circuit area of the array substrate, and the second thin film transistor is located in the peripheral circuit area of the array substrate. Two thin film transistors are located in the display area of the array substrate;

The gate of the first thin film transistor and the gate of the second thin film transistor are located in different layers, and the gate of the first thin film transistor and the source and drain electrodes of the second thin film transistor are located in the same layer.

The embodiment of the present invention provides an array substrate and a manufacturing method thereof, and by placing the gate of the first thin film transistor and the gate of the second thin film transistor on different layers, while the source and drain electrodes are on the same layer, it can ensure that the first thin film transistor The thicknesses of the film layers of the second thin film transistor and the second thin film transistor are in their respective optimum ranges, fully exerting the optimal effects of the first thin film transistor and the second thin film transistor in the array substrate, and improving the electrical performance and stability of the display panel.

Description of drawings

Other characteristics, objects and advantages of the present invention will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following description of the drawings.

FIG. 1 is a schematic cross-sectional structure diagram of an array substrate provided by an embodiment of the present invention;

2 is a schematic cross-sectional structure diagram of another array substrate provided by an embodiment of the present invention;

FIG. 3 is a schematic cross-sectional structure diagram of another array substrate provided by an embodiment of the present invention;

FIG. 4 is a schematic cross-sectional structure diagram of another array substrate provided by an embodiment of the present invention;

5 is a schematic cross-sectional structure diagram of another array substrate provided by an embodiment of the present invention;

FIG. 6 is a schematic cross-sectional structure diagram of another array substrate provided by an embodiment of the present invention;

7 is a schematic cross-sectional structure diagram of another array substrate provided by an embodiment of the present invention;

FIG. 8 is a schematic cross-sectional structure diagram of another array substrate provided by an embodiment of the present invention;

9 is a schematic cross-sectional structure diagram of a display panel provided by an embodiment of the present invention;

FIG. 10 is a flow chart of a method for manufacturing an array substrate provided by an embodiment of the present invention.

detailed description

The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, but not to limit the present invention. In addition, it should be noted that, for the convenience of description, only some structures related to the present invention are shown in the drawings but not all structures.

The present invention provides an array substrate, including a base substrate, a plurality of first thin film transistors and a plurality of second thin film transistors; the first thin film transistors and the second thin film transistors are formed above the base substrate; the first thin film transistors The active layer is low temperature polysilicon, the active layer of the second thin film transistor is oxide semiconductor; the first thin film transistor is located in the peripheral circuit area of the array substrate, and the second thin film transistor is located in the display area of the array substrate. In the present invention, the gate of the first thin film transistor and the gate of the second thin film transistor are located in different layers, and the source and drain electrodes of the first thin film transistor and the source and drain electrodes of the second thin film transistor are located in the same layer, which can ensure that the first thin film transistor The thickness of each film layer of the transistor and the second thin film transistor is in their respective optimal ranges, which solves the problem of incompatibility of the optimal film thicknesses of the first thin film transistor and the second thin film transistor in the array substrate in the prior art, and fully utilizes The best effect of the first thin film transistor and the second thin film transistor in the array substrate.

The above is the core idea of the present invention, and the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

FIG. 1 is a schematic cross-sectional structure diagram of an array substrate provided by an embodiment of the present invention. The array substrate includes a base substrate 10 , a plurality of first thin film transistors 30 and a plurality of second thin film transistors 50 , and only one first thin film transistor 30 and one second thin film transistor 50 are exemplarily shown in FIG. 1 . Both the first thin film transistor 30 and the second thin film transistor 50 are formed above the base substrate 10; the active layer 31 of the first thin film transistor 30 is low-temperature polysilicon, and the active layer 52 of the second thin film transistor 50 is an oxide semiconductor; The first thin film transistor 30 is located in the peripheral circuit area A of the array substrate, and the second thin film transistor 50 is located in the display area B of the array substrate. The active layer 31 of the first thin film transistor 30 is low-temperature polysilicon. Such a thin film transistor has high electron mobility, which meets the requirements of high electron mobility and high switching speed in the peripheral circuit area of the display device. The active layer 52 of the second thin film transistor 50 is an oxide semiconductor with high carrier mobility, which can meet the requirement of high device stability in the display area of the display device, is transparent to visible light, has low process temperature and can be produced in a large area, etc. Advantages, the application of oxide thin film transistors to the display area of the array substrate can effectively improve the pixel density, aperture ratio and brightness of the display area, and at the same time improve the display quality of the display panel by improving the stability of the oxide thin film transistors, avoiding the occurrence of Problems such as image retention or uneven brightness. It should be noted that, in the embodiment of the present invention, the first thin film transistor 30 may be an NMOS transistor or a PMOS transistor, and the second thin film transistor 50 may also be an NMOS transistor or a PMOS transistor. In this embodiment of the present invention, the first thin film transistor 30 and the second thin film transistor The channel type of the thin film transistor 50 is not limited.

1, the gate 32 of the first thin film transistor 30 and the gate 51 of the second thin film transistor 50 are located in different layers, and the source and drain electrodes 33 of the first thin film transistor 30 and the source and drain electrodes 53 of the second thin film transistor 50 are located in same floor. FIG. 1 exemplarily sets that the first thin film transistor 30 adopts a top gate structure, and the second thin film transistor 50 adopts a bottom gate structure. 1, a buffer layer 11, an active layer 31 of a first thin film transistor 30, a first insulating layer 12, a gate 32 of the first thin film transistor 30, a second insulating layer 13, a first The gate 51 of the second TFT 50 , the third insulating layer 14 , the active layer 52 of the second TFT 50 , the source and drain electrodes 33 of the first TFT 30 , and the source and drain 53 of the second TFT 50 .

The distance between the active layer 31 of the first thin film transistor 30 and the gate 32 of the first thin film transistor 30 can be adjusted to an optimal thickness according to the characteristics of the first thin film transistor 30 by relevant practitioners. The thickness of the third insulating layer 14 between the gate 51 of the second thin film transistor 50 and the active layer 52 of the second thin film transistor 50 can also be set to an optimal thickness according to the performance requirements of the second thin film transistor 50 . Such a structural arrangement not only ensures the need for a thicker insulating layer between the gate 32 of the first thin film transistor 30 and the source-drain electrode metal of the first thin film transistor 30, but also satisfies the requirement of the gate of the second thin film transistor 50. 51 and the insulating layer between the active layer 52 of the second thin film transistor 50 needs to be relatively thin, which ensures that the thickness of each film layer of the first thin film transistor 30 and the second thin film transistor 50 can be in their respective optimum ranges, The optimal effect of the first thin film transistor 30 and the second thin film transistor 50 in the array substrate is fully exerted, and they are not affected by each other.

Optionally, the buffer layer 11 and the first insulating layer 12 may be inorganic materials, such as silicon oxide and silicon nitride, or a stack of silicon oxide and silicon nitride. Those skilled in the art can understand that the materials of the buffer layer 11 include but are not limited to the above examples. Wherein, regarding the selection of the thickness of the buffer layer 11 , relevant practitioners can adjust the specific thickness of the buffer layer 11 according to the needs of the product.

Optionally, referring to FIG. 1 , the third insulating layer 14 includes a silicon nitride layer 140 and a silicon oxide layer 141 stacked; wherein the silicon oxide layer 141 is in contact with the active layer 52 of the second thin film transistor 50 . Since the hydrogen molecules in the silicon nitride layer 141 will be activated under certain temperature conditions, if the active layer 52 of the second thin film transistor 50 is directly in contact with the silicon nitride layer 141, the active layer 52 will be easily absorbed by the silicon nitride layer. The hydrogen molecules in 141 are hydrogenated, affecting the electrical properties of the active layer 52 . Therefore, in the embodiment of the present invention, the silicon oxide layer 141 is set in contact with the active layer 52 of the second thin film transistor 50 instead of the silicon nitride layer 140 directly contacting the active layer 52, which can avoid nitrogen with a high hydrogen content in the manufacturing process. The effect of the SiO layer 141 on the electrical properties of the active layer 52.

Optionally, referring to FIG. 1 , an etching stopper layer 15 is provided between the active layer 52 of the second thin film transistor 50 and the source-drain electrode 53 of the second thin film transistor 50; the etching stopper layer 15 is provided with a via hole 16, The source and drain electrodes 53 of the second thin film transistor 50 are connected to the active layer 52 of the second thin film transistor 50 through the via hole 16 .

Referring to another array substrate according to an embodiment of the present invention shown in FIG. 2 , an etching stopper layer 15 is disposed on the active layer 52 of the second thin film transistor 50; The active layer 52 of the second thin film transistor 50 is in direct contact.

It should be noted that on the active layer 52 of the second thin film transistor 50 of the array substrate shown in FIG. 1 and FIG. Effect of etching solution on the active layer 52 of the second thin film transistor 50 .

Optionally, the material of the etching stopper layer 15 in the above technical solution includes silicon oxide. Since the etch stop layer 15 is directly in contact with the active layer 52 of the second thin film transistor 50 , silicon oxide can be selected as the representative inorganic material for the material selection of the etch stop layer 15 .

Optionally, the array substrate provided in the embodiment of the present invention may further include a plurality of capacitor structures. Referring to FIG. 3 , the array substrate provided by the embodiment of the present invention may further include a plurality of capacitor structures 40 . Wherein, the first electrode 41 of the capacitive structure 40 and the gate 31 of the first thin film transistor 30 are arranged on the same layer, and the second electrode 42 of the capacitive structure 40 is arranged on the same layer as the gate 51 of the second thin film transistor 50 . In this embodiment, the first electrode 41 of the capacitive structure 40 is set on the same layer as the gate 31 of the first TFT 30, and the second electrode 42 of the capacitive structure 40 is set on the same layer as the gate 51 of the second TFT 50, that is, While manufacturing the thin film transistor, the capacitor structure 40 is manufactured to achieve the effects of simplifying the process flow and reducing the cost.

On the basis of the above embodiments, for example, referring to FIG. 4 , optionally, a protective passivation layer 17 is disposed on the source and drain electrodes 33 of the first thin film transistor 30 and the source and drain electrodes 53 of the second thin film transistor 50 .

Optionally, the material of the protective passivation layer 17 includes silicon oxide. The protective passivation layer 17 can be a layer or a stacked structure. For example, the protective passivation layer 17 may also include a silicon nitride layer 171 and a silicon oxide layer 170 stacked; 53 contacts. Since the protective passivation layer 17 is close to the second thin film transistor 50 and is relatively close to the active layer 52 of the second thin film transistor 50, for example, when the protective passivation layer 17 includes a silicon nitride layer 171 and In the case of the silicon oxide layer 170, considering that the active layer 52 of the second thin film transistor 50 is an oxide semiconductor, after being hydrogenated, the electrical properties will change, so the silicon oxide layer 170 and the first thin film transistor 30 are arranged here. The source and drain electrodes 33 of the second TFT and the source and drain electrodes 53 of the second thin film transistor 50 are in contact.

The protective passivation layer 17 has the advantages of excellent thermal stability, chemical stability, water resistance, insulation, small thermal expansion coefficient, strong adhesion with organic film, and not easy to fall off. It should be noted that the array substrate provided in the embodiment of the present invention can be applied in an organic light emitting display panel, and can also be applied in a liquid crystal display panel and the like. If the array substrate provided by the embodiment of the present invention is applied in an organic light-emitting display panel, optionally, an organic planar layer 18, an anode 19, a pixel definition layer 21, and a light-emitting device layer may be arranged on the protective passivation layer 17 of the array substrate. 20 and cathode 22. When the organic light-emitting display panel emits light, electrons and holes are respectively injected from the cathode 22 and the anode 19 into the light-emitting device layer 20 under the drive of a certain voltage, and after meeting, excitons are formed and the light-emitting molecules are excited, and the latter undergoes radiation relaxation. Yu emits visible light.

If the array substrate provided by the embodiment of the present invention is applied in a liquid crystal display panel, referring to FIG. 5 , an organic planar layer 18 and a pixel electrode 23 may also be disposed on the protective passivation layer 17 of the array substrate 10 . Then, a display panel is formed by filling liquid crystal molecules between the array substrate 10 and the color filter substrate for pressing and packaging. The liquid crystal display panel uses thin film transistors as switching devices to apply a certain voltage driving signal between the pixel electrode and the common electrode to control the orientation of liquid crystal molecules and present a display image.

It should be noted that, in the above embodiments, the film layers of the first thin film transistor and the film layers of the second thin film transistor can be selected in an appropriate thickness range according to actual needs. In the embodiment of the present invention, each film layer of the first thin film transistor and each film layer of the second thin film transistor can be set according to the following thickness range:

Optionally, the silicon nitride layer 140 of the third insulating layer 14 has a thickness ranging from 50nm to 400nm.

Optionally, the thickness of the silicon oxide layer 141 in the third insulating layer 14 ranges from 30 nm to 200 nm.

Optionally, the active layer 52 of the second thin film transistor 50 has a thickness ranging from 20nm to 100nm.

Optionally, the etching stopper layer 15 has a thickness of 50-250 nm.

Exemplarily, referring to FIG. 4 , the buffer layer 11 may exemplarily be a silicon oxide layer, a silicon nitride, and a stacked layer of silicon oxide, with thicknesses of 500 nm, 120 nm, and 300 nm in sequence. The thickness of the active layer 31 of the first thin film transistor 30 may be 45nm, the first insulating layer 12 of the first thin film transistor 30 may be a stack of silicon oxide and silicon nitride, and the thicknesses are 80nm and 40nm in turn, the first thin film transistor The thickness of the gate of 30 is 220nm, the thickness of the first electrode 41 of the capacitance structure 40 is 220nm, the thickness of the second insulating layer 13 silicon nitride is 100nm, the source drain electrode 33 of the first thin film transistor 30 and the second thin film transistor The source and drain electrodes 53 of the 50 can be Ti, Al, and Ti metal stacks with thicknesses of 70nm, 400nm, and 50nm respectively, the thickness of the silicon oxide layer 170 protecting the passivation layer 17 is 100nm, and the thickness of the silicon nitride layer 171 is 150nm. , the thickness of the organic planar layer 18 is 2 μm, and the anode 19 is exemplarily a stack of ITO, Ag, and ITO, with thicknesses of 80 nm, 150 nm, and 100 nm, respectively.

It should be noted that, except that the first thin film transistor 30 adopts a top gate structure and the second thin film transistor 50 adopts a bottom gate structure, in other embodiments, the bottom gate structure and the top gate structure of the first thin film transistor and the second thin film transistor Other combinations of settings can also be made, for example, the first thin film transistor has a bottom gate structure, and the second thin film transistor has a bottom gate structure; or the first thin film transistor has a bottom gate structure, and the second thin film transistor has a top gate structure; or the first thin film transistor has a bottom gate structure; The thin film transistor has a top gate structure, and the second thin film transistor has a top gate structure.

In the array substrate shown in FIG. 6 , the first thin film transistor 30 has a bottom gate structure, and the second thin film transistor 50 has a bottom gate structure. In the array substrate shown in FIG. 7 , the first thin film transistor 30 has a bottom gate structure, and the second thin film transistor 50 has a top gate structure. In the array substrate shown in FIG. 8 , the first thin film transistor 30 has a top gate structure, and the second thin film transistor 50 has a top gate structure.

It should be noted that the selection of the top gate structure and the bottom gate structure of the first thin film transistor 30 and the second thin film transistor 50 are different, and the distance between the two electrodes of the capacitor structure 40 will be different. Those skilled in the art can select the structure types of the first thin film transistor 30 and the second thin film transistor 50 according to the actual requirements of product design.

The embodiment of the present invention also provides a display panel. FIG. 9 is a schematic structural diagram of a display panel provided by an embodiment of the present invention. As shown in FIG. 9 , the display panel includes the array substrate 100 in the above embodiments. The display panel provided by the embodiment of the present invention includes the array substrate in the above-mentioned embodiment, so the display panel provided by the embodiment of the present invention also has the beneficial effects described in the above-mentioned embodiment, which will not be repeated here. It should be noted that the display panel provided in the embodiment of the present invention may be an organic light emitting display panel, or may be a liquid crystal display panel. Exemplarily, the organic light emitting display panel may be any product or component with a display function such as a notebook computer, a tablet computer, or a monitor.

Based on the same idea and invention, an embodiment of the present invention also provides a method for preparing an array substrate. The preparation method includes:

A plurality of first thin film transistors and a plurality of second thin film transistors are formed above the base substrate. Wherein, the active layer of the first thin film transistor is low temperature polysilicon, the active layer of the second thin film transistor is an oxide semiconductor; the first thin film transistor is located in the peripheral circuit area of the array substrate, and the second thin film transistor is located in the peripheral circuit area of the array substrate. Two thin film transistors are located in the display area of the array substrate.

The gate of the first thin film transistor and the gate of the second thin film transistor are located in different layers, and the gate of the first thin film transistor and the source and drain electrodes of the second thin film transistor are located in the same layer.

An embodiment of the present invention provides a method for fabricating an array substrate by forming a plurality of first thin film transistors and a plurality of second thin film transistors above a base substrate. The gate of the first thin film transistor and the gate of the second thin film transistor are located in different layers, and the source and drain electrodes of the first thin film transistor and the source and drain electrodes of the second thin film transistor are located in the same layer, which can ensure that the first thin film transistor and the second thin film transistor The thickness of each film layer of the thin film transistor is in its respective optimal range, which solves the problem of incompatibility of the optimal film thicknesses of the first thin film transistor and the second thin film transistor in the array substrate in the prior art, and makes full use of the first thin film transistor and the optimal effect of the second thin film transistor in the array substrate.

Optionally, taking the schematic cross-sectional structure of the array substrate shown in FIG. Two thin film transistors also include:

forming a plurality of capacitive structures 40;

Wherein, the first electrode 41 of the capacitor structure 40 is formed at the same time as the gate 32 of the first thin film transistor 30 is formed; the capacitor structure 40 is formed at the same time as the gate 51 of the second thin film transistor 50 is formed. The second electrode 42.

The benefit of setting the capacitor structure 40 is to facilitate the maintenance of the driving potential during the process of the display panel emitting light. In addition, in this embodiment, the first electrode 41 of the capacitive structure 40 is arranged on the same layer as the gate 32 of the first thin film transistor 30, and the second electrode 42 of the capacitive structure 40 is arranged on the same layer as the gate 51 of the second thin film transistor 50, namely When manufacturing the thin film transistor, the capacitor structure 40 is manufactured at the same time, so as to achieve the effect of simplifying the process flow and reducing the cost.

Taking FIG. 3 as an example, FIG. 10 is a schematic flowchart of a method for manufacturing an array substrate provided by an embodiment of the present invention. The method for forming a plurality of first thin film transistors 30 and a plurality of second thin film transistors 50 above the base substrate 10 includes:

Step 101, forming a buffer layer on a base substrate.

The buffer layer 11 is formed on the base substrate 10 . The base substrate 10 can be, for example, a flexible substrate, and the material can be polyimide, for example. Exemplarily, the buffer layer 11 may be silicon oxide and silicon nitride, or may also be a stack of silicon oxide and silicon nitride.

Step 102 , forming an active layer of the first thin film transistor on the film layer where the buffer layer is located.

An active layer is formed on the film layer where the buffer layer 11 is located, and is patterned to form the active layer 31 of the first thin film transistor 30 .

Step 103 , forming a first insulating layer above the film layer where the active layer of the first thin film transistor is located.

The first insulating layer 13 is formed on the film layer where the active layer 31 of the first thin film transistor 30 is located. Exemplarily, the first insulating layer 13 is a stack of one or more inorganic materials.

Step 104 , forming the gate of the first thin film transistor on the film layer where the first insulating layer is located.

The gate of the first thin film transistor 30 is formed above the film layer where the first insulating layer 13 is located.

Step 105 , forming a second insulating layer above the film layer where the gate of the first thin film transistor is located.

The second insulating layer 13 is formed on the film layer where the gate 32 of the first thin film transistor 30 is located.

Step 106 , forming the gate of the second thin film transistor on the film layer where the second insulating layer is located.

The gate 51 of the second thin film transistor 50 is formed above the film layer where the second insulating layer 13 is located.

Step 107, forming a third insulating layer above the film layer where the gate of the second thin film transistor is located.

The third insulating layer 14 is formed above the film layer where the gate 51 of the second thin film transistor 50 is located. The third insulating layer 14 provides a gate oxide layer for the second thin film transistor 50 .

Step 108 , forming an active layer of the second thin film transistor on the film layer where the third insulating layer is located.

The active layer 52 of the second thin film transistor 50 is formed on the film layer where the third insulating layer 14 is located.

Step 109 , forming source-drain electrodes of the first thin-film transistor and source-drain electrodes of the second thin-film transistor on the film layer where the active layer of the second thin-film transistor is located.

The source and drain electrodes 33 of the first thin film transistor 30 and the source and drain electrodes 53 of the second thin film transistor 50 are formed above the film layer where the active layer 52 of the second thin film transistor 50 is located. The electrode material of the source and drain electrodes may be, for example, a metal stack of Ti and Al.

Optionally, the third insulating layer 14 includes a silicon nitride layer 140 and a silicon oxide layer 141 that are stacked;

Forming the third insulating layer 14 above the film layer where the gate 51 of the second thin film transistor 50 is located includes: sequentially forming a silicon nitride layer 140 and a silicon oxide layer 141 above the film layer where the gate 51 of the second thin film transistor 50 is located, so as to The silicon oxide layer 141 in the third insulating layer is in contact with the active layer 52 of the second thin film transistor 50 .

The sequence of forming the third insulating layer 14 is to form the silicon nitride layer 140 first, and then form the silicon oxide 141 . After the silicon oxide 141 is formed, hydrogenation treatment is performed on the first thin film transistor under certain temperature conditions, that is, under high temperature conditions, the hydrogen in the silicon nitride layer 140 of the third insulating layer 14 is activated and diffuses to the first thin film transistor at high temperature. In the active layer 31 of the thin film transistor 30 . After the hydrogenation is completed, the active layer 52 of the second thin film transistor 50 is formed. In the embodiment of the present invention, the silicon oxide layer 141 is set in contact with the active layer 52 of the second thin film transistor 50 instead of the silicon nitride layer 140 directly contacting the active layer 52, which can avoid the high hydrogen content in the hydrogenation process of the first thin film transistor After the hydrogen molecules in the silicon nitride layer 140 are activated, the activated hydrogen ions affect the electrical properties of the oxide semiconductor active layer 52 in the second thin film transistor 50 .

Optionally, referring to FIG. 1 , before step 109, the source and drain electrodes 33 of the first thin film transistor 30 and the source and drain electrodes of the second thin film transistor 50 are formed above the film layer where the active layer 52 of the second thin film transistor 50 is located. Before 53, also includes:

On the active layer 52 of the second thin film transistor 50, an etching barrier layer 15 is formed, and the etching barrier layer 15 is etched to form a via hole, so that the source and drain electrodes of the second thin film transistor are connected to the active layer of the second thin film transistor 50 through the via hole. The source layer 52 is connected.

Referring to FIG. 2 , optionally, before step 109, the source and drain electrodes 33 of the first thin film transistor 30 and the source and drain electrodes 33 of the second thin film transistor 50 are formed on the film layer where the active layer 52 of the second thin film transistor 50 is located. Before the electrode and the drain 53, it also includes:

An etch stopper layer 15 is formed on the active layer 52 of the second thin film transistor 50, so that the source, drain, and electrode 53 of the second thin film transistor 50 are partially aligned with the active layer 53 of the second thin film transistor 50. The source layer 52 is in direct contact.

It should be noted that the etching stopper layer 15 is provided on the active layer 52 of the second thin film transistor 50 of the array substrate shown in FIG. 3 and FIG. 4 to protect the active layer 52 of the second thin film transistor 50. Avoid corrosion of the active layer by the etchant when the source and drain metals are etched.

Optionally, the material of the etch stop layer 15 includes silicon oxide. Since the etch stop layer 15 is directly in contact with the active layer 52 of the second thin film transistor 50 , silicon oxide can be selected as the representative inorganic material for the material selection of the etch stop layer 15 .

Optionally, taking FIG. 5 as an example, after step 109, the source and drain electrodes 33 of the first thin film transistor 30 and the second thin film transistor 30 are formed on the film layer where the active layer 52 of the second thin film transistor 50 is located. After the source and drain electrodes 53 of the transistor 50, it also includes:

A protective passivation layer 17 is formed above the source-drain electrodes 33 of the first TFT 30 and the source-drain electrodes 53 of the second TFT 50 .

Optionally, the material of the protective passivation layer 17 includes silicon oxide.

Optionally, the protective passivation layer 17 includes a silicon nitride layer 171 and a silicon oxide layer 170 that are stacked;

Forming the protective passivation layer 17 above the source and drain electrodes 33 of the first thin film transistor 30 and the source and drain electrodes 53 of the second thin film transistor 50 includes:

A silicon nitride layer 171 and a silicon oxide layer 170 are sequentially formed over the source and drain electrodes 33 of the first thin film transistor 30 and the source and drain electrodes 53 of the second thin film transistor 50; wherein the protective passivation layer 17 The silicon oxide layer 170 is in contact with the source-drain electrodes 33 of the first TFT 30 and the source-drain electrodes 53 of the second TFT 50 .

The protective passivation layer has the advantages of excellent thermal stability, chemical stability, water resistance, insulation, small thermal expansion coefficient, strong adhesion with organic film and not easy to fall off. It should be noted that, for example, above the protective passivation layer 17 are an organic planar layer 18 , an anode 19 , a light emitting device layer 20 , a pixel defining layer 21 and a cathode 22 .

Optionally, after step 107 and before step 108, after the third insulating layer 14 is formed on the film layer where the gate 51 of the second thin film transistor 50 is located, the third insulating layer 14 is formed on the film layer where the third insulating layer 14 is located. Before the active layer 52 of the second thin film transistor 50, it also includes: hydrogenating the first thin film transistor under certain temperature conditions, that is, under high temperature conditions, the silicon nitride layer 140 of the third insulating layer 14 The hydrogen is activated and diffused into the active layer 31 of the first thin film transistor 30 at a high temperature. After the hydrogenation is completed, the active layer 52 of the second thin film transistor 50 is formed. The electrical performance of the hydrogenated first thin film transistor 30 is improved. In the embodiment of the present invention, the silicon oxide layer 141 is set in contact with the active layer 52 of the second thin film transistor 50 instead of the silicon nitride layer 140 directly contacting the active layer 52, which can avoid the high hydrogen content in the hydrogenation process of the first thin film transistor After the hydrogen molecules in the silicon nitride layer 140 are activated, the activated hydrogen ions affect the electrical properties of the oxide semiconductor active layer 52 in the second thin film transistor 50 .

Optionally, the temperature of the hydrotreatment is greater than 300°C. The hydrogen in the silicon nitride is activated and can diffuse to hydrogenate the low-temperature polysilicon in the first thin film transistor.

Optionally, the active layer of the second thin film transistor 50 is formed above the film layer where the third insulating layer 14 is located, because metal oxides tend to lose the inherent electrical properties of semiconductor materials in a temperature environment greater than 350° C. The production temperature in the production method after 52 is less than or equal to 350°C.

Optionally, the fabrication temperature of the silicon nitride layer 141 in the protective passivation layer 17 is less than or equal to 300°C. The fabrication temperature of the silicon nitride layer 141 in the protective passivation layer 17 is less than or equal to 300°C, because in a temperature environment greater than 300°C, the hydrogen in the silicon nitride will be activated, and it is easy to hydrogenate the first layer adjacent to the protective passivation layer. Two metal oxide semiconductor layers in a thin film transistor.

Optionally, taking the array substrate shown in FIG. 6 as an example, the first thin film transistor 30 has a bottom gate structure, and the second thin film transistor 50 has a bottom gate structure. The manufacturing method of the array substrate shown in FIG. 6 includes: forming a buffer layer 61 on the base substrate 60; Form the fourth insulating layer 62 above the film layer where the fourth insulating layer 62 is located; form the active layer 31 of the first thin film transistor 30 above the film layer where the fourth insulating layer 62 is located; form the first thin film transistor 30 above the film layer where the active layer 31 is located. Five insulating layers 63; the gate 51 of the second thin film transistor is formed above the film layer where the fifth insulating layer 63 is located; the sixth insulating layer 64 is formed above the film layer where the gate 51 of the second thin film transistor 50 is located; the sixth insulating layer 64 includes a silicon nitride layer 640 and a silicon oxide layer 641 stacked, wherein the silicon oxide layer 641 is in contact with the active layer 52 of the second thin film transistor 50; the second thin film transistor is formed above the film layer where the sixth insulating layer 64 is located. The active layer 52 of 50; the source and drain electrodes 33 of the first thin film transistor and the source and drain electrodes 53 of the second thin film transistor are formed on the film layer where the active layer 52 of the second thin film transistor is located. Optionally, before the source-drain electrodes 33 of the first thin-film transistor and the source-drain electrodes 53 of the second thin-film transistor are formed on the film layer where the active layer 52 of the second thin-film transistor is located, the active layer 52 of the second thin-film transistor An etch stop layer 66 is formed thereon.

Optionally, taking the array substrate shown in FIG. 7 as an example, the first thin film transistor 30 has a bottom gate structure, and the second thin film transistor 50 has a top gate structure. The manufacturing method of the array substrate shown in FIG. 7 includes: forming a buffer layer 71 on the base substrate 70; Form the seventh insulating layer 72 above the film layer where 32 is located; form the active layer 31 of the first thin film transistor 30 above the film layer where the seventh insulating layer 72 is located; form the active layer 31 above the film layer where the first thin film transistor 30 is located The eighth insulating layer 73, the eighth insulating layer 73 includes a silicon nitride layer 730 and a silicon oxide layer 731 stacked, wherein the silicon oxide layer 731 is in contact with the active layer 52 of the second thin film transistor 50; The active layer 51 of the second thin film transistor 50 is formed above the film layer where 73 is located; the ninth insulating layer 74 is formed above the film layer where the active layer 51 of the second thin film transistor 50 is located, and the ninth insulating layer 74 includes stacked A silicon oxide layer 740 and a silicon nitride layer 741, wherein the silicon oxide layer 740 is in contact with the active layer 52 of the second thin film transistor 50; the second thin film transistor is formed above the film layer where the ninth insulating layer 74 of the second thin film transistor 50 is located The gate 52 of 50; the tenth insulating layer 75 is formed above the film layer where the gate 52 of the second thin film transistor 50 is located; the source drain electrode 33 of the first thin film transistor 30 and the first The source and drain electrodes 53 of the two thin film transistors 50 .

Optionally, taking the array substrate shown in FIG. 8 as an example, the first thin film transistor 30 has a top gate structure, and the second thin film transistor 50 has a top gate structure. The manufacturing method of the array substrate shown in FIG. 8 includes: forming a buffer layer 81 on the base substrate 80; forming the active layer 31 of the first thin film transistor 30 on the film layer where the buffer layer 81 is located; The eleventh insulating layer 82 is formed on the film layer where the active layer 31 is located; the gate 32 of the first thin film transistor 30 is formed on the film layer where the eleventh insulating layer 82 is located; A twelfth insulating layer 83 is formed above the layer, and the twelfth insulating layer 83 includes a silicon nitride layer 830 and a silicon oxide layer 831 stacked in layers, wherein the silicon oxide layer 831 is in contact with the active layer 52 of the second thin film transistor 50; The active layer 52 of the second thin film transistor 50 is formed above the film layer where the twelfth insulating layer 83 is located; the thirteenth insulating layer 84 is formed above the film layer where the active layer 52 of the second thin film transistor 50 is located. The insulating layer 84 includes a silicon oxide layer 840 and a silicon nitride layer 841 stacked in layers, wherein the silicon oxide layer 840 is in contact with the active layer 52 of the second thin film transistor 50; the thirteenth insulating layer 84 of the second thin film transistor 50 The gate 51 of the second thin film transistor 50 is formed above the film layer; the fourteenth insulating layer 85 is formed above the film layer where the gate 51 of the second thin film transistor 50 is located; the fourth insulating layer 85 is formed above the film layer where the fourteenth insulating layer 85 is located. A source-drain electrode 33 of a TFT 30 and a source-drain electrode 53 of a second TFT 50 .

The array substrate shown in FIG. 6 , FIG. 7 and FIG. 8 is different from the array substrate shown in FIG. 6 in that the selection of the top gate and the bottom gate of the first thin film transistor 30 and the second thin film transistor 50 are different, Consequently, the capacitance structure 40 and the parasitic capacitance of the TFT will be different. The common point is that since the gates of the first thin film transistor 30 and the second thin film transistor 50 are on the same layer, and the source and drain electrodes are also on the same layer, the gates of the first thin film transistor 30 and the second thin film transistor 50 are located on different layers. The drain electrodes are located on the same layer, which can ensure that the thickness of each film layer of the first thin film transistor 30 and the second thin film transistor 50 is in their respective optimal ranges, so that the first thin film transistor 30 and the second thin film transistor 50 can be fully utilized in the array. Optimum effects in substrates, unaffected by each other. It should be noted that, for the capacitive structure 40 in the array substrate shown in FIG. 6 , FIG. 7 and FIG. The second electrode 42 is provided on the same layer as the gate 51 of the second thin film transistor 50 . Relevant practitioners can also fabricate the two electrodes of the capacitor structure 40 and other metal layers in the array substrate in the same layer according to actual needs, which is not limited here. Fabricating the two electrodes of the capacitor structure 40 and the metal layer of the array substrate on the same layer is for simplifying the process and saving costs. As for the selection of the metal layer fabricated on the same layer as the electrodes, it can be selected according to the capacitance required in the array substrate. When the selected metal layer is different from the two electrodes of the capacitor structure, the distance between the two electrodes of the capacitor structure will be different, thereby affecting the capacitance value.

An array substrate and a manufacturing method thereof provided by an embodiment of the present invention are formed by forming a plurality of first thin film transistors and a plurality of second thin film transistors above a base substrate. The first thin film transistor is located in the peripheral circuit area of the array substrate and is used to provide timing signals for the driving circuit. The active layer of the first thin film transistor is low-temperature polysilicon. Such a thin film transistor has a high electron mobility, which is consistent with the peripheral circuit of the display device. The requirements of high electron mobility and fast electrical performance in the area. The second thin film transistor is located in the display area of the array substrate, and is used for providing a driving signal for the display area. The active layer of the second thin film transistor is an oxide semiconductor, which has high carrier mobility and good electrical performance uniformity, which can meet the high stability requirements of the display area of the display device, and is transparent to visible light, low process temperature and With the advantages of large-area production, the application of metal oxide thin film transistors to the display area of the array substrate can effectively improve the pixel density, aperture ratio and brightness of the display area, and at the same time improve the stability of the metal oxide thin film transistors. The display quality of the panel can avoid problems such as image afterimages or uneven brightness. During the manufacturing process, the gate of the first thin film transistor and the gate of the second thin film transistor are located in different layers, and the gate of the first thin film transistor and the source and drain electrodes of the second thin film transistor are located in the same layer. It can ensure that the thickness of each film layer of the first thin film transistor and the second thin film transistor is in their optimal range, which solves the incompatibility of the optimal film thickness of the first thin film transistor and the second thin film transistor in the array substrate in the prior art problem, to give full play to the optimal effect of the first thin film transistor and the second thin film transistor in the array substrate.

Note that the above are only preferred embodiments of the present invention and applied technical principles. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the protection scope of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and can also include more other equivalent embodiments without departing from the concept of the present invention, and the present invention The scope is determined by the scope of the appended claims.

Claims (26)

1. An array substrate, characterized in that, comprising: Substrate substrate; A plurality of first thin film transistors and a plurality of second thin film transistors; the first thin film transistors and the second thin film transistors are formed above the base substrate; the active layer of the first thin film transistors is low temperature polysilicon , the active layer of the second thin film transistor is an oxide semiconductor; the first thin film transistor is located in the peripheral circuit area of the array substrate, and the second thin film transistor is located in the display area of the array substrate; The gate of the first thin film transistor and the gate of the second thin film transistor are located in different layers, and the source and drain electrodes of the first thin film transistor and the source and drain electrodes of the second thin film transistor are located in the same layer. 2. The array substrate according to claim 1, further comprising: Multiple capacitor structures; Wherein, the first electrode of the capacitive structure is disposed on the same layer as the gate of the first thin film transistor, and the second electrode of the capacitive structure is disposed on the same layer as the gate of the second thin film transistor. 3. The array substrate according to claim 1, wherein a buffer layer, an active layer of the first thin film transistor, a first insulating layer, and the first thin film transistor are sequentially arranged on the base substrate. The gate of the second insulating layer, the gate of the second thin film transistor, the third insulating layer, the active layer of the second thin film transistor, the source and drain electrodes of the first thin film transistor, and the second The source and drain electrodes of the thin film transistor. 4. The array substrate according to claim 3, wherein the third insulating layer comprises a silicon nitride layer and a silicon oxide layer stacked; The active layer contact of the second thin film transistor. 5. The array substrate according to claim 3, wherein an etching stopper layer is disposed between the active layer of the second thin film transistor and the source and drain electrodes of the second thin film transistor; The etching barrier layer is provided with a via hole, and the source and drain electrodes of the second thin film transistor are connected to the active layer of the second thin film transistor through the via hole. 6. The array substrate according to claim 3, wherein an etching stopper layer is disposed on the active layer of the second thin film transistor; Partial regions of the source and drain electrodes of the second thin film transistor are in direct contact with the active layer of the second thin film transistor. 7. The array substrate according to claim 5 or 6, wherein the material of the etching stopper layer comprises silicon oxide. 8. The array substrate according to claim 3, wherein a protective passivation layer is disposed on the source and drain electrodes of the first thin film transistor and the source and drain electrodes of the second thin film transistor. 9. The array substrate according to claim 8, wherein the material of the protective passivation layer comprises silicon oxide. 10. The array substrate according to claim 8, wherein the protective passivation layer comprises a silicon nitride layer and a silicon oxide layer stacked; wherein the silicon oxide layer and the first thin film transistor The source and drain electrodes are in contact with the source and drain electrodes of the second thin film transistor. 11. The array substrate according to claim 4, characterized in that, The silicon nitride layer in the third insulating layer has a thickness ranging from 50nm to 400nm. 12. The array substrate according to claim 4, characterized in that, The silicon oxide layer in the third insulating layer has a thickness ranging from 30nm to 200nm. 13. The array substrate according to claim 1, characterized in that, The active layer of the second thin film transistor has a thickness of 20-100 nm. 14. The array substrate according to claim 5 or 6, characterized in that, The thickness of the etching barrier layer is 50-250nm. 15. The array substrate according to claim 1, characterized in that, The first thin film transistor has a bottom gate structure, and the second thin film transistor has a bottom gate structure; or the first thin film transistor has a bottom gate structure, and the second thin film transistor has a top gate structure; or the first thin film transistor has a bottom gate structure, and the second thin film transistor has a top gate structure; The thin film transistor has a top gate structure, and the second thin film transistor has a top gate structure. 16. A display panel, comprising the array substrate according to any one of claims 1-15. 17. The display panel according to claim 16, wherein the display panel comprises an organic light emitting display panel or a liquid crystal display panel. 18. A method for manufacturing an array substrate, comprising: forming a plurality of first thin film transistors and a plurality of second thin film transistors above the base substrate; Wherein, the active layer of the first thin film transistor is low temperature polysilicon, the active layer of the second thin film transistor is an oxide semiconductor; the first thin film transistor is located in the peripheral circuit area of the array substrate, and the second thin film transistor is located in the peripheral circuit area of the array substrate. Two thin film transistors are located in the display area of the array substrate; The gate of the first thin film transistor and the gate of the second thin film transistor are located in different layers, and the gate of the first thin film transistor and the source and drain electrodes of the second thin film transistor are located in the same layer. 19. The manufacturing method according to claim 18, characterized in that, while forming a plurality of first thin film transistors and a plurality of second thin film transistors above the base substrate, further comprising: Form multiple capacitive structures; Wherein, the first electrode of the capacitance structure is formed at the same time as the gate of the first thin film transistor is formed; the second electrode of the capacitance structure is formed at the same time as the gate of the second thin film transistor is formed; The source and drain electrodes of the first thin film transistor simultaneously form the source and drain electrodes of the second thin film transistor. 20. The manufacturing method according to claim 18, wherein forming a plurality of first thin film transistors and a plurality of second thin film transistors above the base substrate comprises: forming a buffer layer on the base substrate; forming an active layer of the first thin film transistor on the film layer where the buffer layer is located; forming a first insulating layer above the film layer where the active layer of the first thin film transistor is located; forming the gate of the first thin film transistor above the film layer where the first insulating layer is located; forming a second insulating layer above the film layer where the gate of the first thin film transistor is located; forming the gate of the second thin film transistor on the film layer where the second insulating layer is located; forming a third insulating layer above the film layer where the gate of the second thin film transistor is located; forming an active layer of the second thin film transistor on the film layer where the third insulating layer is located; The source-drain electrodes of the first thin-film transistor and the source-drain electrodes of the second thin-film transistor are formed above the film layer where the active layer of the second thin-film transistor is located. 21. The manufacturing method according to claim 20, characterized in that, after the third insulating layer is formed on the film layer where the gate of the second thin film transistor is located, the third insulating layer is formed on the film layer where the third insulating layer is located. Before the active layer of the second thin film transistor, it also includes: Hydrogenation is carried out. 22. The manufacturing method according to claim 21, characterized in that, The temperature of the hydrogenation treatment is greater than 300°C. 23. The manufacturing method according to claim 20, characterized in that, The manufacturing temperature in the manufacturing method after forming the active layer of the second thin film transistor on the film layer where the third insulating layer is located is less than or equal to 350°C. 24. The method according to claim 18, wherein forming a plurality of first thin film transistors and a plurality of second thin film transistors above the base substrate comprises: The first thin film transistor has a bottom gate structure, and the second thin film transistor has a bottom gate structure; forming a buffer layer on the base substrate; forming the gate of the first thin film transistor above the film layer of the buffer layer; forming a fourth insulating layer above the film layer where the gate of the first thin film transistor is located; forming the active layer of the first thin film transistor 30 above the film layer where the fourth insulating layer is located; forming a fifth insulating layer above the film layer where the active layer of the first thin film transistor is located; forming the gate of the second thin film transistor on the film layer where the fifth insulating layer is located; forming the sixth insulating layer above the film layer where the gate of the second thin film transistor is located; forming an active layer of the second thin film transistor on the film layer where the sixth insulating layer is located; The source-drain electrodes of the first thin-film transistor and the source-drain electrodes of the second thin-film transistor are formed above the film layer where the active layer of the second thin-film transistor is located. 25. The method according to claim 18, wherein forming a plurality of first thin film transistors and a plurality of second thin film transistors above the base substrate comprises: The first thin film transistor has a bottom gate structure, and the second thin film transistor has a top gate structure; forming a buffer layer on the base substrate; forming the gate of the first thin film transistor above the film layer of the buffer layer; forming a seventh insulating layer above the film layer where the gate of the first thin film transistor is located; forming the active layer of the first thin film transistor 30 above the film layer where the seventh insulating layer is located; forming an eighth insulating layer above the film layer where the active layer of the first thin film transistor is located; forming an active layer of the second thin film transistor on the film layer where the eighth insulating layer is located; forming a ninth insulating layer above the film layer where the active layer of the second thin film transistor is located; forming the gate of the second thin film transistor on the film layer where the ninth insulating layer of the second thin film transistor is located; forming a tenth insulating layer above the film layer where the gate of the second thin film transistor is located; The source and drain electrodes 33 of the first thin film transistor and the source and drain electrodes of the second thin film transistor are formed above the film layer where the tenth insulating layer is located. 26. The method according to claim 18, wherein forming a plurality of first thin film transistors and a plurality of second thin film transistors above the base substrate comprises: The first thin film transistor has a top gate structure, and the second thin film transistor has a top gate structure; forming a buffer layer on the base substrate; forming an active layer of the first thin film transistor on the film layer where the buffer layer is located; forming an eleventh insulating layer above the film layer where the active layer of the first thin film transistor is located; forming the gate of the first thin film transistor above the film layer where the eleventh insulating layer is located; forming a twelfth insulating layer above the film layer where the gate of the first thin film transistor is located; forming an active layer of the second thin film transistor on the film layer where the twelfth insulating layer is located; forming a thirteenth insulating layer above the film layer where the active layer of the second thin film transistor is located; forming the gate of the second thin film transistor above the film layer where the thirteenth insulating layer of the second thin film transistor is located; forming a fourteenth insulating layer above the film layer where the gate of the second thin film transistor is located; The source and drain electrodes of the first thin film transistor and the source and drain electrodes of the second thin film transistor are formed above the film layer where the fourteenth insulating layer is located.