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CN100432811C - Pixel structure of TFT-LCD device and its manufacturing method - Google Patents

Pixel structure of TFT-LCD device and its manufacturing method Download PDF

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CN100432811C
CN100432811C CNB2006101441986A CN200610144198A CN100432811C CN 100432811 C CN100432811 C CN 100432811C CN B2006101441986 A CNB2006101441986 A CN B2006101441986A CN 200610144198 A CN200610144198 A CN 200610144198A CN 100432811 C CN100432811 C CN 100432811C
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electrode
transparent film
layer
pixel electrode
pixel
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CN1971389A (en
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陈旭
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BOE Technology Group Co Ltd
Gaochuang Suzhou Electronics Co Ltd
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BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
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Abstract

The invention discloses a pixel construction of the thin film transistor liquid crystal display that comprises insulating substrate, grid line, gate electrode, grid insulating layer, Silicon Island, source electrode, drain, datawire, passive layer and pixel electrode, a transparent film that its shape is same as the pixel electrode is formed above the pixel electrode. The invention discloses a producing method of the thin film transistor liquid crystal display, a transparent film is deposited after the deposition of the pixel electrode, the pixel electrode can be obtained after mask plate, exposure and etching, the transparent film above the pixel electrode is reserved at the same time. The improved construction and craft can effectively improve the various kinds of Mura (the quality of image is imperfect) phenomenon generated by friction, the contrast can be increased, redundancy of craft can be extended, service life of the material can be extended, defective workmanship can be decreased, the quality of image can be improved.

Description

Pixel structure for thin film transistor liquid crystal display and manufacture method thereof
Technical field
The present invention relates to Thin Film Transistor-LCD (TFT LCD) dot structure and manufacture method thereof, relate in particular to the white Mura of a kind of improvement (a kind of picture quality is bad), increase technology redundancy (Margin), prolong material serviceable life, reduce defective workmanship, improve contrast, improve the thin film transistor pixel structure and the manufacture method thereof of picture quality phenomenon.
Background technology
In recent years, along with popularizing of digital to television, traditional CRT shows because its digitizing difficulty, and volume is big, weight is big and shortcoming such as radiation is arranged, and the trend that substituted by display technique of new generation occurred, and representational new display technique has PDP, OLED, LCD etc.Wherein, LCD (LCD) since have in light weight, volume thin, radiationless, power consumption is little and the display resolution advantages of higher, has begun in a large number universal, and begins to become main product.
But existing LCD technology still has much room for improvement.In order to make liquid crystal molecule have the optics anisotropic, the liquid crystal molecule pre-dumping angle certain in the alignment films upper edge arranged, in the present stage molding process, adopt the processing step of friction orientation, just adopt friction cloth friction orientation film, form orientation angles, because the affinity that the propylene chain produces between alignment films and liquid crystal molecule, make liquid crystal molecule have being attached on the alignment films of directivity, after the ground floor liquid crystal molecular orientation on the alignment films finishes, be subjected to the influence of affinity between liquid crystal, liquid crystal molecule forms the continuous arrangement that has certain orientation, but, when array base palte carries out alignment films coating and friction process step, because array base palte is in traditional handicraft manufacturing process, the thickness of grid line (GateLine) and data line (Data Line) is considerably beyond the thickness of pixel electrode ITO, causes in the array base palte pixel between the grid line and pixel electrode (ITO) and exists bigger end poor between data line and the pixel electrode ITO, and the array base palte surface smoothness is bad.
Fig. 1 a is depicted as a prior art array plane structural drawing, and the sectional view that A-A ' locates among Fig. 1 a is shown in Fig. 1 b, and the sectional view that B-B ' locates among Fig. 1 a is shown in Fig. 1 c.This array structure comprises: dielectric substrate is formed on the public electrode 11 on the dielectric substrate; Be formed on grid line 1, gate electrode 2 on the dielectric substrate; Be formed on the gate insulation layer 4 on the gate electrode 2; Be formed on the silicon island 3 on the gate insulation layer 4; Be formed on source, the top electrode 6 and the drain electrode 7 of silicon island 3; Data line 5 is structure as a whole with the source electrode 6 of source-drain electrode; Be formed on passivation layer 8 on the source-drain electrode, and cover whole base plate; Form the passivation layer via hole 9 on the drain electrode 7; Pixel electrode 10 links to each other with drain electrode 7 by passivation layer via hole 9.
The manufacture craft flow process that it is concrete, at first deposition ITO layer on glass substrate forms public electrode 11 by common photoetching and etching technics; Deposit the grid metal level then, form grid line 1, gate electrode 2 by common photoetching and etching technics; Then, deposition gate insulation layer 4, semiconductor layer (active layer and ohmic contact layer) form active silicon island 3 by common photoetching and etching technics; Afterwards, sedimentary origin leaks metallic film, forms source electrode 6 and drain electrode 7 by common photoetching and etching; Subsequently, deposit passivation layer 8, and by common photoetching and etching formation passivation layer via hole 9; At last, the pixel deposition electrode film, and by photoetching formation pixel electrode 10, wherein pixel electrode 10 links to each other with drain electrode 7 by passivation layer via hole 9, promptly finishes the making of matrix structure, shown in Fig. 1 a, 1b, 1c.
By Fig. 1 b and 1c as can be seen, finish on the array base palte of matrix structure making, reason owing to grid line and data line, there is end difference S between pixel region and grid line and pixel region and the data line, after array base palte being carried out the alignment films coating, when carrying out friction process, near rough grid line and data line, can't realize liquid crystal aligning preferably; Simultaneously, along with the carrying out that produces, be easy to cause the damage of friction cloth, these all can cause the liquid crystal aligning confusion, show as uncertain Mura phenomenon on picture quality, the Mura that causes of reason is called friction Mura thus, especially in this wide viewing angle technology of FFS, friction Mura causes contrast (CR) low, has a strong impact on picture quality.
Summary of the invention
The objective of the invention is defective at prior art, a kind of improved thin film transistor pixel structure and manufacture method thereof are provided, by this structure-improved, can effectively improve friction Mura phenomenon, can increase technology redundancy (Margin), prolong material serviceable life, reduce defective workmanship, improve picture quality.
To achieve these goals, the invention provides a kind of pixel structure for thin film transistor liquid crystal display, comprise: dielectric substrate, grid line, gate electrode, gate insulation layer, silicon island, source electrode, drain electrode, data line, passivation layer, pixel electrode and a transparent film layer, described transparent film layer, be formed on the pixel electrode top, shape is identical with pixel electrode shape; The material of transparent film layer is identical with the material of the material of passivation layer or gate insulation layer, and the thickness of described transparent film layer is
Figure C20061014419800051
Arrive
Figure C20061014419800052
In the such scheme, described grid line and gate electrode are the monofilm of AlNd, Al, Cu, Mo, MoW or Cr, perhaps the composite membrane that is constituted for AlNd, Al, Cu, Mo, MoW and Cr combination in any.Described gate insulation layer, passivation layer or transparent film layer are the monofilm of SiNx, SiOx or SiOxNy, perhaps are the composite membrane that SiNx, SiOx and SiOxNy combination in any are constituted.The monofilm of described source electrode, data line or leak electricity very Mo, MoW or Cr, the perhaps composite membrane that is constituted for Mo, MoW and Cr combination in any.
To achieve these goals, the present invention provides a kind of manufacture method of pixel structure for thin film transistor liquid crystal display simultaneously, comprising:
Step 1 forms grid line, gate electrode, gate insulation layer, silicon island, data line, source electrode and drain electrode, passivation layer and via hole thereof on transparent substrates;
Step 2, pixel deposition electrode layer and transparent film layer successively on the substrate of completing steps one, the transparent film layer materials of described deposition is the monofilm of SiNx, SiOx or SiOxNy, is the composite membrane that SiNx, SiOx and SiOxNy combination in any are constituted perhaps, and the thickness of described transparent film layer is Arrive
Figure C20061014419800054
Obtain pixel electrode by mask mask, exposure and etching, and keep the transparent film layer of pixel electrode top simultaneously.
The present invention is with respect to prior art, owing on pixel electrode ITO layer, increased the transparent film layer of a step compensating action, the end that has reduced between pixel electrode area and grid line and the data line is poor, increase the flatness of array base palte, thereby realized the liquid crystal aligning of homogeneous, effectively improved friction Mura, reduce defective workmanship, improve picture quality, can reduce damage simultaneously, prolong the serviceable life of friction cloth friction cloth.
Below in conjunction with the drawings and specific embodiments the present invention is further illustrated in more detail.
Description of drawings
Fig. 1 a is the pixel planes graph structure of prior art;
Fig. 1 b is the sectional view that A-A ' locates among Fig. 1 a;
Fig. 1 c is the sectional view that B-B ' locates among Fig. 1 a;
Fig. 2 a is a pixel planes structural drawing of the present invention;
Fig. 2 b is the sectional view that C-C ' locates among Fig. 2 a;
Fig. 2 c is the sectional view that D-D ' locates among Fig. 2 a;
Fig. 3 a is the floor map after the present invention forms public electrode;
Fig. 3 b is the sectional view that E-E ' locates among Fig. 3 a;
Fig. 4 a is the floor map after the present invention forms grid line and gate electrode;
Fig. 4 b is the sectional view that F-F ' locates among Fig. 4 a;
Fig. 5 a is the floor map after the present invention forms the silicon island;
Fig. 5 b is the sectional view that G-G ' locates among Fig. 5 a;
Fig. 6 a is the floor map after the present invention forms data line and source-drain electrode;
Fig. 6 b is the sectional view that H-H ' locates among Fig. 6 a;
Fig. 7 a is the floor map after the present invention forms via hole;
Fig. 7 b is the sectional view that I-I ' locates among Fig. 7 a;
Fig. 8 a is the post-depositional floor map of pixel electrode of the present invention;
Fig. 8 b is the sectional view that J-J ' locates among Fig. 8 a.
Mark among the figure: 1, grid line; 2, gate electrode; 3, silicon island; 4, gate insulation layer; 5, data line; 6, source electrode; 7, drain electrode; 8, passivation layer; 9, passivation layer via hole; 10, pixel electrode; 11, public electrode; 12, transparent film layer.
Embodiment
Fig. 2 a is depicted as of the present invention one concrete pixel planes structural drawing.Shown in Fig. 2 a, this dot structure comprises: dielectric substrate; Be formed on the public electrode 11 on the dielectric substrate and be formed on grid line 1, gate electrode 2 on the dielectric substrate; Be formed on the gate insulation layer 4 on the gate electrode 2; Be formed on the silicon island 3 of gate insulation layer 4; Be formed on the source electrode 6 and the drain electrode 7 of 3 tops, silicon island; Data line 5 is structure as a whole with the source electrode 6 of source-drain electrode; Be formed on the passivation layer 8 on the source-drain electrode, and cover whole base plate; Form the passivation layer via hole 9 on the drain electrode 7; Pixel electrode 10 links to each other with drain electrode 7 by passivation layer via hole 9.These parts and prior art indifference, this dot structure is different from prior art and is characterised in that, and the transparent film layer 12 of one deck and pixel electrode 10 same shapes is formed on the pixel electrode.The sectional view that C-C ' locates among Fig. 2 a is shown in Fig. 2 b, and the sectional view that D-D ' locates among Fig. 2 a is shown in Fig. 2 c.After carrying out pixel electrode 10 deposition, deposition layer of transparent rete 12 on pixel electrode again, its thickness can be according to grid line 1, data line 5 or design factor such as the influence of memory capacitance decided, its scope exists
Figure C20061014419800071
Arrive Between, adopt the pixel electrode mask to carry out photoetching then, carry out transparent film layer etching and pixel electrode etching afterwards continuously.Adopt this structure improved pixel, owing on pixel electrode, increased the transparent film layer of a step compensating action, reduced the end difference s between pixel electrode area and grid line and the data line, increase the flatness of array base palte, thereby realized the liquid crystal aligning of homogeneous, effectively improved friction Mura, reduced defective workmanship, improved picture quality, can reduce damage simultaneously, prolonged the serviceable life of friction cloth friction cloth.
Wherein, the material of transparent film layer 12 can be identical with gate insulation layer or passivation material, is specifically as follows monofilm or one of SiNx, SiOx or SiOxNy or any composite film of forming of SiNx, SiOx or SiOxNy.Grid line 1 and gate electrode 2 can be the monofilm of AlNd, Al, Cu, Mo, MoW or Cr, also can adopt among AlNd, Al, the Cu one of or arbitrarily and one of Mo, MoW or Cr or any composite membrane of forming, as Mo/AlND/Mo, AlNd/Mo.Gate insulation layer 4 or passivation layer 8 can be one of the monofilm of SiNx, SiOx or SiOxNy or SiNx, SiOx, SiOxNy or any composite membrane of forming.Source electrode 6 and drain electrode 7 can be the monofilm of Mo, MoW or Cr, perhaps for one of Mo, MoW, Cr or form composite membrane arbitrarily.
Fig. 3 a to 8b has provided above-mentioned one pixel structure process method.
At first, shown in Fig. 3 a, adopting magnetically controlled sputter method deposition public electrode (ITO) layer on the glass substrate or on other substrates, by common photoetching and etching, form the figure of public electrode 11, the sectional view that E-E ' locates among Fig. 3 a is shown in Fig. 3 b.
Then, shown in Fig. 4 a, adopt magnetically controlled sputter method deposition grid metallic film on the glass substrate or on other substrates, that the grid metallic film adopts is the Mo/AlND/Mo (400/4000/ of three-decker
Figure C20061014419800081
), or the AlND/Mo (3000/ of double-layer structure
Figure C20061014419800082
), forming grid line 1, gate electrode 2 by common photoetching and etching technics, the sectional view that F-F ' locates among Fig. 4 a is shown in Fig. 4 b.
Grid metallic film in this step can be the monofilm of AlNd, Al, Cu, Mo, MoW or Cr, also can adopt among AlNd, Al, the Cu one of or arbitrarily and one of Mo, MoW or Cr or any composite membrane of forming, as Mo/AlND/Mo, AlNd/Mo.
Then, shown in Fig. 5 a, the deposition grid insulating film (
Figure C20061014419800083
SiNx), semiconductive thin film (comprise active layer (
Figure C20061014419800084
Amorphous silicon layer) with ohmic contact layer (N+ silicon layer
Figure C20061014419800085
)), forming silicon island 3 by common mask etching, the sectional view that G-G ' locates among Fig. 5 a is shown in Fig. 5 b.
Grid insulating film in this step can be one of the monofilm of SiNx, SiOx or SiOxNy or SiNx, SiOx, SiOxNy or any composite membrane of forming.
Then, shown in Fig. 6 a, sedimentary origin leaks metallic film, source leakage metal level employing Mo (
Figure C20061014419800086
), forming source electrode 6 and drain electrode 7 by common photoetching and etching, the sectional view that H-H ' locates among Fig. 6 a is shown in Fig. 6 b;
The monofilm that metallic film can be Mo, MoW or Cr is leaked in this step source, perhaps for one of Mo, MoW, Cr or form composite membrane arbitrarily.
Subsequently, shown in Fig. 7 a, deposition passivation protection film ( PVX), form via hole 9 by passivation layer mask and passivation layer etching, the sectional view that I-I ' locates among Fig. 7 a is shown in Fig. 7 b;
Afterwards, shown in Fig. 8 a, successive sedimentation pixel electrode ITO layer and transparent film layer, the sectional view that J-J ' locates among Figure 14 a is shown in Fig. 8 b;
The material of this step transparent film layer can be identical with gate insulation layer or passivation material, is specifically as follows one of the monofilm of SiNx, SiOx or SiOxNy or SiNx, SiOx, SiOxNy or any composite film of forming.
At last, by the pixel electrode mask with carry out pixel electrode passivating film etching and pixel electrode etching continuously and form pixel electrode 10 and make pixel electrode 10 contact conducting with source electrode 6 by via hole, on pixel electrode, form transparent film layer simultaneously with the onesize shape of pixel electrode, obtain complete dot structure after finishing photoresist lift off at last, shown in Fig. 2 a, 2b, 2c.
Said structure and manufacture method provide as specific embodiment for the present invention is directed to a specific pixel structure and manufacture method, spirit of the present invention is the transparent film layer that has increased a step compensating action on pixel electrode ITO layer, the end that has reduced between pixel electrode area and grid line and the data line is poor, increased the flatness of array base palte, thereby realize the liquid crystal aligning of homogeneous, effectively improve friction Mura, improve contrast, reduce defective workmanship, improve picture quality, can reduce simultaneously damage, prolong the serviceable life of friction cloth friction cloth.Can be as for the dot structure concrete form with of the prior art any identical, dot structure promptly of the present invention can carry out various conversion, as: change the thin-film transistor structure of dot structure, change the shape of public electrode, change the shape of pixel electrode etc.Manufacture method also can be with of the prior art any identical, as various 3 photoetching processes of the prior art or 4 technology is identical all can realize the present invention.
It should be noted that at last, above embodiment is only unrestricted in order to technical scheme of the present invention to be described, although the present invention is had been described in detail with reference to preferred embodiment, those of ordinary skill in the art should can use different materials and equipment to realize it as required, promptly can make amendment or be equal to replacement, and not break away from the spirit and scope of technical solution of the present invention technical scheme of the present invention.

Claims (5)

1, a kind of pixel structure for thin film transistor liquid crystal display, comprise: dielectric substrate, grid line, gate electrode, gate insulation layer, silicon island, source electrode, drain electrode, data line, passivation layer, pixel electrode and a transparent film layer, described transparent film layer is formed on the pixel electrode top, and shape is identical with pixel electrode shape; It is characterized in that: the material of transparent film layer is identical with the material of the material of passivation layer or gate insulation layer, and the thickness of described transparent film layer is
Figure C2006101441980002C1
Arrive
2, dot structure according to claim 1 is characterized in that: described grid line and gate electrode are the monofilm of AlNd, Al, Cu, Mo, MoW or Cr, perhaps the composite membrane that is constituted for AlNd, Al, Cu, Mo, MoW and Cr combination in any.
3, dot structure according to claim 1 is characterized in that: described gate insulation layer, passivation layer or transparent film layer are the monofilm of SiNx, SiOx or SiOxNy, perhaps are the composite membrane that SiNx, SiOx and SiOxNy combination in any are constituted.
4, dot structure according to claim 1 is characterized in that: the monofilm of described source electrode, data line or leak electricity very Mo, MoW or Cr, the perhaps composite membrane that is constituted for Mo, MoW and Cr combination in any.
5, a kind of manufacture method of pixel structure for thin film transistor liquid crystal display is characterized in that, comprising:
Step 1 is at the via hole that forms on the transparent substrates on grid line, gate electrode, gate insulation layer, silicon island, data line, source electrode and drain electrode, passivation layer and the passivation layer;
Step 2, pixel deposition electrode layer and transparent film layer successively on the substrate of completing steps one, the transparent film layer materials of described deposition is the monofilm of SiNx, SiOx or SiOxNy, is the composite membrane that SiNx, SiOx and SiOxNy combination in any are constituted perhaps, and the thickness of described transparent film layer is Arrive
Figure C2006101441980002C4
Obtain pixel electrode by mask mask, exposure and etching, and keep the transparent film layer of pixel electrode top simultaneously.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1178099C (en) * 2001-11-07 2004-12-01 株式会社日立制作所 Liquid crystal display device
WO2005027187A2 (en) * 2003-09-18 2005-03-24 Samsung Electronics Co., Ltd. Thin film transistor array panel and method of manufacturing the same
CN1667477A (en) * 2004-03-11 2005-09-14 Lg.菲利浦Lcd株式会社 In-plane switching mode liquid crystal display device and fabrication method thereof
CN1794068A (en) * 2004-12-24 2006-06-28 Lg.菲利浦Lcd株式会社 Liquid crystal display device and method of fabricating the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1178099C (en) * 2001-11-07 2004-12-01 株式会社日立制作所 Liquid crystal display device
WO2005027187A2 (en) * 2003-09-18 2005-03-24 Samsung Electronics Co., Ltd. Thin film transistor array panel and method of manufacturing the same
CN1667477A (en) * 2004-03-11 2005-09-14 Lg.菲利浦Lcd株式会社 In-plane switching mode liquid crystal display device and fabrication method thereof
CN1794068A (en) * 2004-12-24 2006-06-28 Lg.菲利浦Lcd株式会社 Liquid crystal display device and method of fabricating the same

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